Two instances of CPU (RV32, RV64). Need to implement RV64 specific instructions.
This commit is contained in:
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acf38332d5
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176
inc/CPU.h
176
inc/CPU.h
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@ -28,13 +28,28 @@
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namespace riscv_tlm {
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/**
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* @brief ISC_V CPU model
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* @param name name of the module
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*/
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class CPU : sc_core::sc_module {
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class CPU : sc_core::sc_module {
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public:
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/* Constructors */
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explicit CPU(sc_core::sc_module_name const &name, bool debug);
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CPU() noexcept = delete;
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CPU(const CPU& other) noexcept = delete;
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CPU(CPU && other) noexcept = delete;
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CPU& operator=(const CPU& other) noexcept = delete;
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CPU& operator=(CPU&& other) noexcept = delete;
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/* Destructors */
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~CPU() override = default;
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/**
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* @brief Perform one instruction step
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* @return Breackpoint found (TBD, always true)
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*/
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virtual bool CPU_step() = 0;
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/**
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* @brief Instruction Memory bus socket
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* @param trans transction to perfoem
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@ -49,60 +64,87 @@ namespace riscv_tlm {
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*/
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tlm_utils::simple_target_socket<CPU> irq_line_socket;
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/**
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* @brief DMI pointer is not longer valid
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* @param start memory address region start
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* @param end memory address region end
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*/
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void invalidate_direct_mem_ptr(sc_dt::uint64 start, sc_dt::uint64 end);
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/**
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* @brief CPU main thread
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*/
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[[noreturn]] void CPU_thread();
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/**
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* @brief Process and triggers IRQ if all conditions met
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* @return true if IRQ is triggered, false otherwise
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*/
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virtual bool cpu_process_IRQ() = 0;
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/**
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* @brief callback for IRQ simple socket
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* @param trans transaction to perform (empty)
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* @param delay time to annotate
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*
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* it triggers an IRQ when called
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*/
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virtual void call_interrupt(tlm::tlm_generic_payload &trans,
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sc_core::sc_time &delay) = 0;
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public:
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MemoryInterface *mem_intf;
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protected:
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Performance *perf;
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std::shared_ptr<spdlog::logger> logger;
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tlm_utils::tlm_quantumkeeper *m_qk;
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Instruction inst;
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bool interrupt;
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bool irq_already_down;
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sc_core::sc_time default_time;
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bool dmi_ptr_valid;
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tlm::tlm_generic_payload trans;
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unsigned char *dmi_ptr = nullptr;
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};
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/**
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* @brief RISC_V CPU 32 bits model
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* @param name name of the module
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*/
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class RV32 : public CPU {
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public:
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using BaseType = std::uint32_t;
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/**
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* @brief Constructor
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* @param name Module name
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* @param PC Program Counter initialize value
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* @param debug To start debugging
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*/
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CPU(sc_core::sc_module_name const &name, std::uint32_t PC, bool debug);
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RV32(sc_core::sc_module_name const &name, BaseType PC, bool debug);
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/**
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* @brief Destructor
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*/
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~CPU() override;
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~RV32() override;
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MemoryInterface *mem_intf;
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bool CPU_step();
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Registers<std::uint32_t> *getRegisterBank() { return register_bank; }
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bool CPU_step() override;
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Registers<BaseType> *getRegisterBank() { return register_bank; }
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private:
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Registers<std::uint32_t> *register_bank;
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Performance *perf;
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std::shared_ptr<spdlog::logger> logger;
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C_extension<std::uint32_t> *c_inst;
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M_extension<std::uint32_t> *m_inst;
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A_extension<std::uint32_t> *a_inst;
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BASE_ISA<std::uint32_t> *exec;
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tlm_utils::tlm_quantumkeeper *m_qk;
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Instruction inst;
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bool interrupt;
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std::uint32_t int_cause;
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bool irq_already_down;
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sc_core::sc_time default_time;
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bool dmi_ptr_valid;
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tlm::tlm_generic_payload trans;
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std::uint32_t INSTR;
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unsigned char *dmi_ptr = nullptr;
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Registers<BaseType> *register_bank;
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C_extension<BaseType> *c_inst;
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M_extension<BaseType> *m_inst;
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A_extension<BaseType> *a_inst;
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BASE_ISA<BaseType> *exec;
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BaseType int_cause;
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BaseType INSTR;
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/**
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*
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* @brief Process and triggers IRQ if all conditions met
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* @return true if IRQ is triggered, false otherwise
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*/
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bool cpu_process_IRQ();
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/**
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* main thread for CPU simulation
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* @brief CPU mai thread
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*/
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[[noreturn]] void CPU_thread();
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bool cpu_process_IRQ() override;
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/**
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* @brief callback for IRQ simple socket
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@ -113,14 +155,58 @@ namespace riscv_tlm {
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*/
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void call_interrupt(tlm::tlm_generic_payload &trans,
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sc_core::sc_time &delay);
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}; // RV32 class
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/**
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* @brief RISC_V CPU 64 bits model
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* @param name name of the module
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*/
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class RV64 : public CPU {
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public:
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using BaseType = std::uint64_t;
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/**
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* DMI pointer is not longer valid
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* @param start memory address region start
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* @param end memory address region end
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* @brief Constructor
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* @param name Module name
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* @param PC Program Counter initialize value
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* @param debug To start debugging
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*/
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void invalidate_direct_mem_ptr(sc_dt::uint64 start, sc_dt::uint64 end);
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};
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RV64(sc_core::sc_module_name const &name, BaseType PC, bool debug);
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/**
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* @brief Destructor
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*/
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~RV64() override;
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bool CPU_step() override;
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Registers<BaseType> *getRegisterBank() { return register_bank; }
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private:
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Registers<BaseType> *register_bank;
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C_extension<BaseType> *c_inst;
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M_extension<BaseType> *m_inst;
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A_extension<BaseType> *a_inst;
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BASE_ISA<BaseType> *exec;
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BaseType int_cause;
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BaseType INSTR;
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/**
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*
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* @brief Process and triggers IRQ if all conditions met
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* @return true if IRQ is triggered, false otherwise
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*/
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bool cpu_process_IRQ() override;
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/**
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* @brief callback for IRQ simple socket
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* @param trans transaction to perform (empty)
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* @param delay time to annotate
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*
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* it triggers an IRQ when called
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*/
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void call_interrupt(tlm::tlm_generic_payload &trans,
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sc_core::sc_time &delay);
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}; // RV64 class
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}
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#endif
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@ -25,7 +25,7 @@ namespace riscv_tlm {
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class Debug : sc_core::sc_module {
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public:
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Debug(riscv_tlm::CPU *cpu, Memory *mem);
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Debug(riscv_tlm::RV32 *cpu, Memory *mem);
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~Debug() override;
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@ -41,7 +41,7 @@ namespace riscv_tlm {
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static constexpr size_t bufsize = 1024 * 8;
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char iobuf[bufsize]{};
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int conn;
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riscv_tlm::CPU *dbg_cpu;
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riscv_tlm::RV32 *dbg_cpu;
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Memory *dbg_mem;
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tlm::tlm_generic_payload dbg_trans;
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unsigned char pyld_array[128]{};
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@ -407,11 +407,14 @@ namespace riscv_tlm {
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Performance *perf;
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void initCSR();
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/*
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void initCSR() {
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CSR[CSR_MISA] = MISA_MXL | MISA_M_EXTENSION | MISA_C_EXTENSION
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| MISA_A_EXTENSION | MISA_I_BASE;
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CSR[CSR_MSTATUS] = MISA_MXL;
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}
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*/
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};
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}
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#endif
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@ -80,7 +80,7 @@ namespace riscv_tlm {
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}
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/* pure virtual functions */
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virtual T opcode() const = 0;
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virtual std::uint32_t opcode() const = 0;
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virtual unsigned int get_rd() const {
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return m_instr.range(11, 7);
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194
src/CPU.cpp
194
src/CPU.cpp
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SC_HAS_PROCESS(CPU);
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CPU::CPU(sc_core::sc_module_name const &name, std::uint32_t PC, bool debug) :
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sc_module(name), instr_bus("instr_bus"), inst(0),
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default_time(10, sc_core::SC_NS), INSTR(0) {
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register_bank = new Registers<std::uint32_t>();
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mem_intf = new MemoryInterface();
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CPU::CPU(sc_core::sc_module_name const &name, bool debug) : sc_module(name), instr_bus("instr_bus"), inst(0), default_time(10, sc_core::SC_NS) {
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perf = Performance::getInstance();
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register_bank->setPC(PC);
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register_bank->setValue(Registers<std::uint32_t>::sp, (Memory::SIZE / 4) - 1);
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irq_line_socket.register_b_transport(this, &CPU::call_interrupt);
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interrupt = false;
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int_cause = 0;
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irq_already_down = false;
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dmi_ptr_valid = false;
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instr_bus.register_invalidate_direct_mem_ptr(this,
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&CPU::invalidate_direct_mem_ptr);
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exec = new BASE_ISA<std::uint32_t>(0, register_bank, mem_intf);
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c_inst = new C_extension<std::uint32_t>(0, register_bank, mem_intf);
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m_inst = new M_extension<std::uint32_t>(0, register_bank, mem_intf);
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a_inst = new A_extension<std::uint32_t>(0, register_bank, mem_intf);
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logger = spdlog::get("my_logger");
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m_qk = new tlm_utils::tlm_quantumkeeper();
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m_qk->reset();
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dmi_ptr_valid = false;
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irq_already_down = false;
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interrupt = false;
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irq_line_socket.register_b_transport(this, &CPU::call_interrupt);
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trans.set_command(tlm::TLM_READ_COMMAND);
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trans.set_data_ptr(reinterpret_cast<unsigned char *>(&INSTR));
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trans.set_data_length(4);
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trans.set_streaming_width(4); // = data_length to indicate no streaming
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trans.set_byte_enable_ptr(nullptr); // 0 indicates unused
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if (!debug) {
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SC_THREAD(CPU_thread);
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}
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};
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logger = spdlog::get("my_logger");
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}
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CPU::~CPU() {
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delete register_bank;
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delete mem_intf;
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delete exec;
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delete c_inst;
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delete m_inst;
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delete a_inst;
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delete m_qk;
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}
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bool CPU::cpu_process_IRQ() {
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std::uint32_t csr_temp;
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bool ret_value = false;
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if (interrupt) {
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csr_temp = register_bank->getCSR(CSR_MSTATUS);
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if ((csr_temp & MSTATUS_MIE) == 0) {
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logger->debug("{} ns. PC: 0x{:x}. Interrupt delayed", sc_core::sc_time_stamp().value(),
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register_bank->getPC());
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return ret_value;
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}
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csr_temp = register_bank->getCSR(CSR_MIP);
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if ((csr_temp & MIP_MEIP) == 0) {
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csr_temp |= MIP_MEIP; // MEIP bit in MIP register (11th bit)
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register_bank->setCSR(CSR_MIP, csr_temp);
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logger->debug("{} ns. PC: 0x{:x}. Interrupt!", sc_core::sc_time_stamp().value(),
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register_bank->getPC());
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/* updated MEPC register */
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std::uint32_t old_pc = register_bank->getPC();
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register_bank->setCSR(CSR_MEPC, old_pc);
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logger->debug("{} ns. PC: 0x{:x}. Old PC Value 0x{:x}", sc_core::sc_time_stamp().value(),
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register_bank->getPC(),
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old_pc);
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/* update MCAUSE register */
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register_bank->setCSR(CSR_MCAUSE, 0x80000000);
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/* set new PC address */
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std::uint32_t new_pc = register_bank->getCSR(CSR_MTVEC);
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//new_pc = new_pc & 0xFFFFFFFC; // last two bits always to 0
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logger->debug("{} ns. PC: 0x{:x}. NEW PC Value 0x{:x}", sc_core::sc_time_stamp().value(),
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register_bank->getPC(),
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new_pc);
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register_bank->setPC(new_pc);
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ret_value = true;
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interrupt = false;
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irq_already_down = false;
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}
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} else {
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if (!irq_already_down) {
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csr_temp = register_bank->getCSR(CSR_MIP);
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csr_temp &= ~MIP_MEIP;
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register_bank->setCSR(CSR_MIP, csr_temp);
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irq_already_down = true;
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}
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}
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return ret_value;
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}
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bool CPU::CPU_step() {
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bool PC_not_affected = false;
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/* Get new PC value */
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if (dmi_ptr_valid) {
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/* if memory_offset at Memory module is set, this won't work */
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std::memcpy(&INSTR, dmi_ptr + register_bank->getPC(), 4);
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} else {
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sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
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tlm::tlm_dmi dmi_data;
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trans.set_address(register_bank->getPC());
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instr_bus->b_transport(trans, delay);
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if (trans.is_response_error()) {
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SC_REPORT_ERROR("CPU base", "Read memory");
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}
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if (trans.is_dmi_allowed()) {
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dmi_ptr_valid = instr_bus->get_direct_mem_ptr(trans, dmi_data);
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if (dmi_ptr_valid) {
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std::cout << "Get DMI_PTR " << std::endl;
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dmi_ptr = dmi_data.get_dmi_ptr();
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}
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}
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}
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perf->codeMemoryRead();
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inst.setInstr(INSTR);
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bool breakpoint = false;
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/* check what type of instruction is and execute it */
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switch (inst.check_extension()) {
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[[likely]] case BASE_EXTENSION:
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PC_not_affected = exec->process_instruction(inst, &breakpoint);
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if (PC_not_affected) {
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register_bank->incPC();
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}
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break;
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case C_EXTENSION:
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PC_not_affected = c_inst->process_instruction(inst, &breakpoint);
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if (PC_not_affected) {
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register_bank->incPCby2();
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}
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break;
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case M_EXTENSION:
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PC_not_affected = m_inst->process_instruction(inst);
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if (PC_not_affected) {
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register_bank->incPC();
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}
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break;
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case A_EXTENSION:
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PC_not_affected = a_inst->process_instruction(inst);
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if (PC_not_affected) {
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register_bank->incPC();
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}
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break;
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[[unlikely]] default:
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std::cout << "Extension not implemented yet" << std::endl;
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inst.dump();
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exec->NOP();
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}
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if (breakpoint) {
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std::cout << "Breakpoint set to true\n";
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}
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perf->instructionsInc();
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return breakpoint;
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void CPU::invalidate_direct_mem_ptr(sc_dt::uint64 start, sc_dt::uint64 end) {
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(void) start;
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(void) end;
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dmi_ptr_valid = false;
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}
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[[noreturn]] void CPU::CPU_thread() {
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#endif
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} // while(1)
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} // CPU_thread
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void CPU::call_interrupt(tlm::tlm_generic_payload &m_trans,
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sc_core::sc_time &delay) {
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interrupt = true;
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/* Socket caller send a cause (its id) */
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memcpy(&int_cause, m_trans.get_data_ptr(), sizeof(std::uint32_t));
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delay = sc_core::SC_ZERO_TIME;
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}
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void CPU::invalidate_direct_mem_ptr(sc_dt::uint64 start, sc_dt::uint64 end) {
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(void) start;
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(void) end;
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dmi_ptr_valid = false;
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}
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}
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@ -23,7 +23,7 @@ namespace riscv_tlm {
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constexpr char nibble_to_hex[16] = {'0', '1', '2', '3', '4', '5', '6', '7',
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'8', '9', 'a', 'b', 'c', 'd', 'e', 'f'};
|
||||
|
||||
Debug::Debug(riscv_tlm::CPU *cpu, Memory *mem) : sc_module(sc_core::sc_module_name("Debug")) {
|
||||
Debug::Debug(riscv_tlm::RV32 *cpu, Memory *mem) : sc_module(sc_core::sc_module_name("Debug")) {
|
||||
dbg_cpu = cpu;
|
||||
dbg_mem = mem;
|
||||
|
||||
|
@ -120,7 +120,7 @@ namespace riscv_tlm {
|
|||
send_packet(conn, stream.str());
|
||||
} else if (boost::starts_with(msg, "p")) {
|
||||
long n = strtol(msg.c_str() + 1, 0, 16);
|
||||
unsigned int reg_value;
|
||||
std::uint64_t reg_value;
|
||||
if (n < 32) {
|
||||
reg_value = register_bank->getValue(n);
|
||||
} else if (n == 32) {
|
||||
|
|
|
@ -0,0 +1,187 @@
|
|||
/*!
|
||||
\file CPU.cpp
|
||||
\brief Main CPU class
|
||||
\author Màrius Montón
|
||||
\date August 2018
|
||||
*/
|
||||
// SPDX-License-Identifier: GPL-3.0-or-later
|
||||
#include "CPU.h"
|
||||
|
||||
namespace riscv_tlm {
|
||||
|
||||
SC_HAS_PROCESS(RV32);
|
||||
|
||||
RV32::RV32(sc_core::sc_module_name const &name, BaseType PC, bool debug) :
|
||||
CPU(name, debug), INSTR(0) {
|
||||
|
||||
register_bank = new Registers<BaseType>();
|
||||
mem_intf = new MemoryInterface();
|
||||
register_bank->setPC(PC);
|
||||
register_bank->setValue(Registers<BaseType>::sp, (Memory::SIZE / 4) - 1);
|
||||
|
||||
int_cause = 0;
|
||||
|
||||
instr_bus.register_invalidate_direct_mem_ptr(this,
|
||||
&RV32::invalidate_direct_mem_ptr);
|
||||
|
||||
exec = new BASE_ISA<BaseType>(0, register_bank, mem_intf);
|
||||
c_inst = new C_extension<BaseType>(0, register_bank, mem_intf);
|
||||
m_inst = new M_extension<BaseType>(0, register_bank, mem_intf);
|
||||
a_inst = new A_extension<BaseType>(0, register_bank, mem_intf);
|
||||
|
||||
trans.set_data_ptr(reinterpret_cast<unsigned char *>(&INSTR));
|
||||
|
||||
logger->info("Created RV32 CPU");
|
||||
std::cout << "Created RV32 CPU" << std::endl;
|
||||
}
|
||||
|
||||
RV32::~RV32() {
|
||||
delete register_bank;
|
||||
delete mem_intf;
|
||||
delete exec;
|
||||
delete c_inst;
|
||||
delete m_inst;
|
||||
delete a_inst;
|
||||
delete m_qk;
|
||||
}
|
||||
|
||||
bool RV32::cpu_process_IRQ() {
|
||||
BaseType csr_temp;
|
||||
bool ret_value = false;
|
||||
|
||||
if (interrupt) {
|
||||
csr_temp = register_bank->getCSR(CSR_MSTATUS);
|
||||
if ((csr_temp & MSTATUS_MIE) == 0) {
|
||||
logger->debug("{} ns. PC: 0x{:x}. Interrupt delayed", sc_core::sc_time_stamp().value(),
|
||||
register_bank->getPC());
|
||||
|
||||
return ret_value;
|
||||
}
|
||||
|
||||
csr_temp = register_bank->getCSR(CSR_MIP);
|
||||
|
||||
if ((csr_temp & MIP_MEIP) == 0) {
|
||||
csr_temp |= MIP_MEIP; // MEIP bit in MIP register (11th bit)
|
||||
register_bank->setCSR(CSR_MIP, csr_temp);
|
||||
|
||||
logger->debug("{} ns. PC: 0x{:x}. Interrupt!", sc_core::sc_time_stamp().value(),
|
||||
register_bank->getPC());
|
||||
|
||||
/* updated MEPC register */
|
||||
BaseType old_pc = register_bank->getPC();
|
||||
register_bank->setCSR(CSR_MEPC, old_pc);
|
||||
|
||||
logger->debug("{} ns. PC: 0x{:x}. Old PC Value 0x{:x}", sc_core::sc_time_stamp().value(),
|
||||
register_bank->getPC(),
|
||||
old_pc);
|
||||
|
||||
/* update MCAUSE register */
|
||||
register_bank->setCSR(CSR_MCAUSE, 0x80000000);
|
||||
|
||||
/* set new PC address */
|
||||
BaseType new_pc = register_bank->getCSR(CSR_MTVEC);
|
||||
//new_pc = new_pc & 0xFFFFFFFC; // last two bits always to 0
|
||||
logger->debug("{} ns. PC: 0x{:x}. NEW PC Value 0x{:x}", sc_core::sc_time_stamp().value(),
|
||||
register_bank->getPC(),
|
||||
new_pc);
|
||||
register_bank->setPC(new_pc);
|
||||
|
||||
ret_value = true;
|
||||
interrupt = false;
|
||||
irq_already_down = false;
|
||||
}
|
||||
} else {
|
||||
if (!irq_already_down) {
|
||||
csr_temp = register_bank->getCSR(CSR_MIP);
|
||||
csr_temp &= ~MIP_MEIP;
|
||||
register_bank->setCSR(CSR_MIP, csr_temp);
|
||||
irq_already_down = true;
|
||||
}
|
||||
}
|
||||
|
||||
return ret_value;
|
||||
}
|
||||
|
||||
bool RV32::CPU_step() {
|
||||
bool PC_not_affected = false;
|
||||
|
||||
/* Get new PC value */
|
||||
if (dmi_ptr_valid) {
|
||||
/* if memory_offset at Memory module is set, this won't work */
|
||||
std::memcpy(&INSTR, dmi_ptr + register_bank->getPC(), 4);
|
||||
} else {
|
||||
sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
|
||||
tlm::tlm_dmi dmi_data;
|
||||
trans.set_address(register_bank->getPC());
|
||||
instr_bus->b_transport(trans, delay);
|
||||
|
||||
if (trans.is_response_error()) {
|
||||
SC_REPORT_ERROR("CPU base", "Read memory");
|
||||
}
|
||||
|
||||
if (trans.is_dmi_allowed()) {
|
||||
dmi_ptr_valid = instr_bus->get_direct_mem_ptr(trans, dmi_data);
|
||||
if (dmi_ptr_valid) {
|
||||
std::cout << "Get DMI_PTR " << std::endl;
|
||||
dmi_ptr = dmi_data.get_dmi_ptr();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
perf->codeMemoryRead();
|
||||
inst.setInstr(INSTR);
|
||||
bool breakpoint = false;
|
||||
|
||||
/* check what type of instruction is and execute it */
|
||||
switch (inst.check_extension()) {
|
||||
[[likely]] case BASE_EXTENSION:
|
||||
PC_not_affected = exec->process_instruction(inst, &breakpoint);
|
||||
if (PC_not_affected) {
|
||||
register_bank->incPC();
|
||||
}
|
||||
break;
|
||||
case C_EXTENSION:
|
||||
PC_not_affected = c_inst->process_instruction(inst, &breakpoint);
|
||||
if (PC_not_affected) {
|
||||
register_bank->incPCby2();
|
||||
}
|
||||
break;
|
||||
case M_EXTENSION:
|
||||
PC_not_affected = m_inst->process_instruction(inst);
|
||||
if (PC_not_affected) {
|
||||
register_bank->incPC();
|
||||
}
|
||||
break;
|
||||
case A_EXTENSION:
|
||||
PC_not_affected = a_inst->process_instruction(inst);
|
||||
if (PC_not_affected) {
|
||||
register_bank->incPC();
|
||||
}
|
||||
break;
|
||||
[[unlikely]] default:
|
||||
std::cout << "Extension not implemented yet" << std::endl;
|
||||
inst.dump();
|
||||
exec->NOP();
|
||||
}
|
||||
|
||||
if (breakpoint) {
|
||||
std::cout << "Breakpoint set to true\n";
|
||||
}
|
||||
|
||||
perf->instructionsInc();
|
||||
|
||||
return breakpoint;
|
||||
}
|
||||
|
||||
|
||||
|
||||
void RV32::call_interrupt(tlm::tlm_generic_payload &m_trans,
|
||||
sc_core::sc_time &delay) {
|
||||
interrupt = true;
|
||||
/* Socket caller send a cause (its id) */
|
||||
memcpy(&int_cause, m_trans.get_data_ptr(), sizeof(BaseType));
|
||||
delay = sc_core::SC_ZERO_TIME;
|
||||
}
|
||||
|
||||
|
||||
}
|
|
@ -0,0 +1,183 @@
|
|||
/*!
|
||||
\file CPU.cpp
|
||||
\brief Main CPU class
|
||||
\author Màrius Montón
|
||||
\date August 2018
|
||||
*/
|
||||
// SPDX-License-Identifier: GPL-3.0-or-later
|
||||
#include "CPU.h"
|
||||
|
||||
namespace riscv_tlm {
|
||||
|
||||
RV64::RV64(sc_core::sc_module_name const &name, BaseType PC, bool debug) :
|
||||
CPU(name, debug), INSTR(0) {
|
||||
|
||||
register_bank = new Registers<BaseType>();
|
||||
mem_intf = new MemoryInterface();
|
||||
register_bank->setPC(PC);
|
||||
register_bank->setValue(Registers<BaseType>::sp, (Memory::SIZE / 4) - 1);
|
||||
|
||||
int_cause = 0;
|
||||
|
||||
instr_bus.register_invalidate_direct_mem_ptr(this,
|
||||
&RV64::invalidate_direct_mem_ptr);
|
||||
|
||||
exec = new BASE_ISA<BaseType>(0, register_bank, mem_intf);
|
||||
c_inst = new C_extension<BaseType>(0, register_bank, mem_intf);
|
||||
m_inst = new M_extension<BaseType>(0, register_bank, mem_intf);
|
||||
a_inst = new A_extension<BaseType>(0, register_bank, mem_intf);
|
||||
|
||||
trans.set_data_ptr(reinterpret_cast<unsigned char *>(&INSTR));
|
||||
|
||||
logger->info("Created RV64 CPU");
|
||||
std::cout << "Created RV64 CPU" << std::endl;
|
||||
}
|
||||
|
||||
RV64::~RV64() {
|
||||
delete register_bank;
|
||||
delete mem_intf;
|
||||
delete exec;
|
||||
delete c_inst;
|
||||
delete m_inst;
|
||||
delete a_inst;
|
||||
delete m_qk;
|
||||
}
|
||||
|
||||
bool RV64::cpu_process_IRQ() {
|
||||
BaseType csr_temp;
|
||||
bool ret_value = false;
|
||||
|
||||
if (interrupt) {
|
||||
csr_temp = register_bank->getCSR(CSR_MSTATUS);
|
||||
if ((csr_temp & MSTATUS_MIE) == 0) {
|
||||
logger->debug("{} ns. PC: 0x{:x}. Interrupt delayed", sc_core::sc_time_stamp().value(),
|
||||
register_bank->getPC());
|
||||
|
||||
return ret_value;
|
||||
}
|
||||
|
||||
csr_temp = register_bank->getCSR(CSR_MIP);
|
||||
|
||||
if ((csr_temp & MIP_MEIP) == 0) {
|
||||
csr_temp |= MIP_MEIP; // MEIP bit in MIP register (11th bit)
|
||||
register_bank->setCSR(CSR_MIP, csr_temp);
|
||||
|
||||
logger->debug("{} ns. PC: 0x{:x}. Interrupt!", sc_core::sc_time_stamp().value(),
|
||||
register_bank->getPC());
|
||||
|
||||
/* updated MEPC register */
|
||||
BaseType old_pc = register_bank->getPC();
|
||||
register_bank->setCSR(CSR_MEPC, old_pc);
|
||||
|
||||
logger->debug("{} ns. PC: 0x{:x}. Old PC Value 0x{:x}", sc_core::sc_time_stamp().value(),
|
||||
register_bank->getPC(),
|
||||
old_pc);
|
||||
|
||||
/* update MCAUSE register */
|
||||
register_bank->setCSR(CSR_MCAUSE, 0x80000000);
|
||||
|
||||
/* set new PC address */
|
||||
BaseType new_pc = register_bank->getCSR(CSR_MTVEC);
|
||||
//new_pc = new_pc & 0xFFFFFFFC; // last two bits always to 0
|
||||
logger->debug("{} ns. PC: 0x{:x}. NEW PC Value 0x{:x}", sc_core::sc_time_stamp().value(),
|
||||
register_bank->getPC(),
|
||||
new_pc);
|
||||
register_bank->setPC(new_pc);
|
||||
|
||||
ret_value = true;
|
||||
interrupt = false;
|
||||
irq_already_down = false;
|
||||
}
|
||||
} else {
|
||||
if (!irq_already_down) {
|
||||
csr_temp = register_bank->getCSR(CSR_MIP);
|
||||
csr_temp &= ~MIP_MEIP;
|
||||
register_bank->setCSR(CSR_MIP, csr_temp);
|
||||
irq_already_down = true;
|
||||
}
|
||||
}
|
||||
|
||||
return ret_value;
|
||||
}
|
||||
|
||||
bool RV64::CPU_step() {
|
||||
bool PC_not_affected = false;
|
||||
|
||||
/* Get new PC value */
|
||||
if (dmi_ptr_valid) {
|
||||
/* if memory_offset at Memory module is set, this won't work */
|
||||
std::memcpy(&INSTR, dmi_ptr + register_bank->getPC(), 4);
|
||||
} else {
|
||||
sc_core::sc_time delay = sc_core::SC_ZERO_TIME;
|
||||
tlm::tlm_dmi dmi_data;
|
||||
trans.set_address(register_bank->getPC());
|
||||
instr_bus->b_transport(trans, delay);
|
||||
|
||||
if (trans.is_response_error()) {
|
||||
SC_REPORT_ERROR("CPU base", "Read memory");
|
||||
}
|
||||
|
||||
if (trans.is_dmi_allowed()) {
|
||||
dmi_ptr_valid = instr_bus->get_direct_mem_ptr(trans, dmi_data);
|
||||
if (dmi_ptr_valid) {
|
||||
std::cout << "Get DMI_PTR " << std::endl;
|
||||
dmi_ptr = dmi_data.get_dmi_ptr();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
perf->codeMemoryRead();
|
||||
inst.setInstr(INSTR);
|
||||
bool breakpoint = false;
|
||||
|
||||
/* check what type of instruction is and execute it */
|
||||
switch (inst.check_extension()) {
|
||||
[[likely]] case BASE_EXTENSION:
|
||||
PC_not_affected = exec->process_instruction(inst, &breakpoint);
|
||||
if (PC_not_affected) {
|
||||
register_bank->incPC();
|
||||
}
|
||||
break;
|
||||
case C_EXTENSION:
|
||||
PC_not_affected = c_inst->process_instruction(inst, &breakpoint);
|
||||
if (PC_not_affected) {
|
||||
register_bank->incPCby2();
|
||||
}
|
||||
break;
|
||||
case M_EXTENSION:
|
||||
PC_not_affected = m_inst->process_instruction(inst);
|
||||
if (PC_not_affected) {
|
||||
register_bank->incPC();
|
||||
}
|
||||
break;
|
||||
case A_EXTENSION:
|
||||
PC_not_affected = a_inst->process_instruction(inst);
|
||||
if (PC_not_affected) {
|
||||
register_bank->incPC();
|
||||
}
|
||||
break;
|
||||
[[unlikely]] default:
|
||||
std::cout << "Extension not implemented yet" << std::endl;
|
||||
inst.dump();
|
||||
exec->NOP();
|
||||
}
|
||||
|
||||
if (breakpoint) {
|
||||
std::cout << "Breakpoint set to true\n";
|
||||
}
|
||||
|
||||
perf->instructionsInc();
|
||||
|
||||
return breakpoint;
|
||||
}
|
||||
|
||||
void RV64::call_interrupt(tlm::tlm_generic_payload &m_trans,
|
||||
sc_core::sc_time &delay) {
|
||||
interrupt = true;
|
||||
/* Socket caller send a cause (its id) */
|
||||
memcpy(&int_cause, m_trans.get_data_ptr(), sizeof(BaseType));
|
||||
delay = sc_core::SC_ZERO_TIME;
|
||||
}
|
||||
|
||||
|
||||
}
|
|
@ -6,4 +6,21 @@
|
|||
*/
|
||||
// SPDX-License-Identifier: GPL-3.0-or-later
|
||||
|
||||
#include "Registers.h"
|
||||
|
||||
namespace riscv_tlm {
|
||||
/* Specialization for each XLEN (RV32, RV64)*/
|
||||
template<>
|
||||
void Registers<std::uint32_t>::initCSR() {
|
||||
CSR[CSR_MISA] = MISA_MXL | MISA_M_EXTENSION | MISA_C_EXTENSION
|
||||
| MISA_A_EXTENSION | MISA_I_BASE;
|
||||
CSR[CSR_MSTATUS] = MISA_MXL;
|
||||
}
|
||||
|
||||
template<>
|
||||
void Registers<std::uint64_t>::initCSR() {
|
||||
CSR[CSR_MISA] = (((std::uint64_t) 0x02) << 30) | MISA_M_EXTENSION | MISA_C_EXTENSION
|
||||
| MISA_A_EXTENSION | MISA_I_BASE;
|
||||
CSR[CSR_MSTATUS] = MISA_MXL;
|
||||
}
|
||||
}
|
|
@ -24,12 +24,16 @@
|
|||
#include "spdlog/spdlog.h"
|
||||
#include "spdlog/sinks/basic_file_sink.h"
|
||||
|
||||
typedef enum {RV32, RV64} cpu_types_t;
|
||||
|
||||
std::string filename;
|
||||
bool debug_session = false;
|
||||
bool mem_dump = false;
|
||||
uint32_t dump_addr_st = 0;
|
||||
uint32_t dump_addr_end = 0;
|
||||
|
||||
cpu_types_t cpu_type_opt = RV32;
|
||||
|
||||
/**
|
||||
* @class Simulator
|
||||
* This class instantiates all necessary modules, connects its ports and starts
|
||||
|
@ -45,13 +49,17 @@ public:
|
|||
riscv_tlm::peripherals::Trace *trace;
|
||||
riscv_tlm::peripherals::Timer *timer;
|
||||
|
||||
explicit Simulator(sc_core::sc_module_name const &name): sc_module(name) {
|
||||
explicit Simulator(sc_core::sc_module_name const &name, cpu_types_t cpu_type): sc_module(name) {
|
||||
std::uint32_t start_PC;
|
||||
|
||||
MainMemory = new riscv_tlm::Memory("Main_Memory", filename);
|
||||
start_PC = MainMemory->getPCfromHEX();
|
||||
|
||||
cpu = new riscv_tlm::CPU("cpu", start_PC, debug_session);
|
||||
if (cpu_type == RV32) {
|
||||
cpu = new riscv_tlm::RV32("cpu", start_PC, debug_session);
|
||||
} else {
|
||||
cpu = new riscv_tlm::RV64("cpu", start_PC, debug_session);
|
||||
}
|
||||
|
||||
Bus = new riscv_tlm::BusCtrl("BusCtrl");
|
||||
trace = new riscv_tlm::peripherals::Trace("Trace");
|
||||
|
@ -67,7 +75,7 @@ public:
|
|||
timer->irq_line.bind(cpu->irq_line_socket);
|
||||
|
||||
if (debug_session) {
|
||||
riscv_tlm::Debug debug(cpu, MainMemory);
|
||||
//riscv_tlm::Debug debug(cpu, MainMemory);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -83,7 +91,7 @@ public:
|
|||
}
|
||||
|
||||
private:
|
||||
void MemoryDump() {
|
||||
void MemoryDump() const {
|
||||
std::cout << "********** MEMORY DUMP ***********\n";
|
||||
tlm::tlm_generic_payload trans;
|
||||
tlm::tlm_dmi dmi_data;
|
||||
|
@ -134,8 +142,9 @@ void process_arguments(int argc, char *argv[]) {
|
|||
int debug_level;
|
||||
|
||||
debug_session = false;
|
||||
cpu_type_opt = RV32;
|
||||
|
||||
while ((c = getopt(argc, argv, "DTE:B:L:f:?")) != -1) {
|
||||
while ((c = getopt(argc, argv, "DTE:B:L:f:R:?")) != -1) {
|
||||
switch (c) {
|
||||
case 'D':
|
||||
debug_session = true;
|
||||
|
@ -173,6 +182,13 @@ void process_arguments(int argc, char *argv[]) {
|
|||
case 'f':
|
||||
filename = std::string(optarg);
|
||||
break;
|
||||
case 'R':
|
||||
if (strcmp(optarg, "RV32") == 0) {
|
||||
cpu_type_opt = RV32;
|
||||
} else {
|
||||
cpu_type_opt = RV64;
|
||||
}
|
||||
break;
|
||||
case '?':
|
||||
std::cout << "Call ./RISCV_TLM -D -L <debuglevel> (0..3) filename.hex"
|
||||
<< std::endl;
|
||||
|
@ -199,15 +215,15 @@ int sc_main(int argc, char *argv[]) {
|
|||
/* SystemC time resolution set to 1 ns*/
|
||||
sc_core::sc_set_time_resolution(1, sc_core::SC_NS);
|
||||
|
||||
spdlog::filename_t filename = SPDLOG_FILENAME_T("newlog.txt");
|
||||
logger = spdlog::create<spdlog::sinks::basic_file_sink_mt>("my_logger", filename);
|
||||
spdlog::filename_t log_filename = SPDLOG_FILENAME_T("newlog.txt");
|
||||
logger = spdlog::create<spdlog::sinks::basic_file_sink_mt>("my_logger", log_filename);
|
||||
logger->set_pattern("%v");
|
||||
logger->set_level(spdlog::level::info);
|
||||
|
||||
/* Parse and process program arguments. -f is mandatory */
|
||||
process_arguments(argc, argv);
|
||||
|
||||
top = new Simulator("top");
|
||||
top = new Simulator("top", cpu_type_opt);
|
||||
|
||||
auto start = std::chrono::steady_clock::now();
|
||||
sc_core::sc_start();
|
||||
|
|
Loading…
Reference in New Issue