8 Commits

Author	SHA1	Message	Date
colin.liang	8f3d66097c	Enable build.	2022-10-13 19:23:28 +08:00
Màrius Montón	a1098ad81f	Better git and compile options	2022-09-15 12:49:12 +02:00
mariusmonton	5d30416955	Fixed some warnings from coverity	2020-04-10 16:43:22 +02:00
mariusmonton	9961f080c9	examples updated	2018-09-20 12:24:07 +02:00
mariusmonton	8dcbf09589	Lot of changes: ... * memory module parses 03 field and sets Program Counter (PC) to right value * almost all RV32I instructions implemented * added Trace module to mimic ARM ITM module * added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals * lot of minor changes	2018-09-19 23:44:38 +02:00
mariusmonton	53b6234ecb	minor changes	2018-09-12 13:08:48 +02:00
mariusmonton	35e688837a	initial import	2018-09-10 18:44:54 +02:00
Màrius Montón	26e67681f0	Initial commit	2018-09-10 18:41:14 +02:00