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risc-v-tlm
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4 Commits

Author SHA1 Message Date
mariusmonton aa526943b9 Added instructions to pass riscv-tests 2018-10-15 13:51:41 +02:00
mariusmonton f17b3b75d5 new setters to Instruction class 2018-10-10 18:58:08 +02:00
mariusmonton 08044ac626 * Instruction: changed name to accessors 
* CPU: moved huge switch case to a new function
* Execute: changed to use instruction new accessors
 2018-10-10 12:08:53 +02:00
mariusmonton 35e688837a initial import 2018-09-10 18:44:54 +02:00