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4 Commits

Author SHA1 Message Date
mariusmonton d42d67b991 DMI access added (if available) 2019-03-28 22:52:36 +01:00
mariusmonton a4a1be7386 IRQ implemented 2019-01-13 01:30:49 +01:00
mariusmonton afbf317941 updated documentation 2018-09-21 11:23:31 +02:00
mariusmonton 8dcbf09589 Lot of changes: 
* memory module parses 03 field and sets Program Counter (PC) to right value
* almost all RV32I instructions implemented
* added Trace module to mimic ARM ITM module
* added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals
* lot of minor changes
 2018-09-19 23:44:38 +02:00