risc-v-tlm

Commit Graph

Author	SHA1	Message	Date
mariusmonton	4114f482d6	Doxygen	2018-11-24 23:46:01 +01:00
mariusmonton	afbf317941	updated documentation	2018-09-21 11:23:31 +02:00
mariusmonton	8dcbf09589	Lot of changes: * memory module parses 03 field and sets Program Counter (PC) to right value * almost all RV32I instructions implemented * added Trace module to mimic ARM ITM module * added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals * lot of minor changes	2018-09-19 23:44:38 +02:00

Author

SHA1

Message

Date

mariusmonton

4114f482d6

Doxygen

2018-11-24 23:46:01 +01:00

mariusmonton

afbf317941

updated documentation

2018-09-21 11:23:31 +02:00

mariusmonton

8dcbf09589

Lot of changes:

* memory module parses 03 field and sets Program Counter (PC) to right value
* almost all RV32I instructions implemented
* added Trace module to mimic ARM ITM module
* added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals
* lot of minor changes

2018-09-19 23:44:38 +02:00

3 Commits