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7 Commits

Author SHA1 Message Date
mariusmonton b9e26e4dea first implementation supporting exceptions 2018-11-22 14:38:31 +01:00
mariusmonton 6726b59c3c bug on SLLI 2018-11-22 12:39:16 +01:00
mariusmonton 0cd34f9f3b fixed CSRRS and CSRRC bug 2018-11-22 12:08:16 +01:00
mariusmonton 5ae765b304 Proper initialization of sp register 2018-10-15 17:32:37 +02:00
mariusmonton 981b84a5eb Better register dump 2018-09-20 15:29:22 +02:00
mariusmonton 8dcbf09589 Lot of changes: 
* memory module parses 03 field and sets Program Counter (PC) to right value
* almost all RV32I instructions implemented
* added Trace module to mimic ARM ITM module
* added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals
* lot of minor changes
 2018-09-19 23:44:38 +02:00
mariusmonton 35e688837a initial import 2018-09-10 18:44:54 +02:00