risc-v-tlm

Commit Graph

Author	SHA1	Message	Date
mariusmonton	8dcbf09589	Lot of changes: * memory module parses 03 field and sets Program Counter (PC) to right value * almost all RV32I instructions implemented * added Trace module to mimic ARM ITM module * added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals * lot of minor changes	2018-09-19 23:44:38 +02:00
mariusmonton	1c9bfe8c60	Added Data Memory bus. Implemented LW & SW instructions.	2018-09-17 12:21:26 +02:00
mariusmonton	35e688837a	initial import	2018-09-10 18:44:54 +02:00

Author

SHA1

Message

Date

mariusmonton

8dcbf09589

Lot of changes:

* memory module parses 03 field and sets Program Counter (PC) to right value
* almost all RV32I instructions implemented
* added Trace module to mimic ARM ITM module
* added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals
* lot of minor changes

2018-09-19 23:44:38 +02:00

mariusmonton

1c9bfe8c60

Added Data Memory bus. Implemented LW & SW instructions.

2018-09-17 12:21:26 +02:00

mariusmonton

35e688837a

initial import

2018-09-10 18:44:54 +02:00

3 Commits