9a46e9d0a5
add missing break for case
2020-05-29 16:03:45 +02:00
d62892e3dc
minor changes, better code
2019-02-11 20:26:23 +01:00
a2a9c95546
Added A Extensions
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Added SFENCE instruction
2018-12-12 18:14:35 +01:00
ed7be704f9
implementation of all remaining C extension
2018-11-19 15:56:08 +01:00
adc30178ab
fixed detection of M extension
2018-11-14 23:14:06 +01:00
a8bdc37c12
all tests passed!
2018-11-14 19:14:57 +01:00
aa526943b9
Added instructions to pass riscv-tests
2018-10-15 13:51:41 +02:00
08044ac626
* Instruction: changed name to accessors
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* CPU: moved huge switch case to a new function
* Execute: changed to use instruction new accessors
2018-10-10 12:08:53 +02:00
8dcbf09589
Lot of changes:
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* memory module parses 03 field and sets Program Counter (PC) to right value
* almost all RV32I instructions implemented
* added Trace module to mimic ARM ITM module
* added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals
* lot of minor changes
2018-09-19 23:44:38 +02:00
35e688837a
initial import
2018-09-10 18:44:54 +02:00
Màrius Montón