colin
/
risc-v-tlm
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
166 Commits 1 Branch 0 Tags 2.1 MiB
Commit Graph

5 Commits

Author SHA1 Message Date
mariusmonton 5d30416955 Fixed some warnings from coverity 2020-04-10 16:43:22 +02:00
Màrius Montón 0415ba3c66 added xterm window for trace output 2019-09-08 11:41:06 +02:00
mariusmonton 4114f482d6 Doxygen 2018-11-24 23:46:01 +01:00
mariusmonton 8e8418e3e2 Better logging output 2018-09-20 12:21:15 +02:00
mariusmonton 8dcbf09589 Lot of changes: 
* memory module parses 03 field and sets Program Counter (PC) to right value
* almost all RV32I instructions implemented
* added Trace module to mimic ARM ITM module
* added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals
* lot of minor changes
 2018-09-19 23:44:38 +02:00