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6 Commits

Author SHA1 Message Date
mariusmonton aa526943b9 Added instructions to pass riscv-tests 2018-10-15 13:51:41 +02:00
mariusmonton 21003e2fa9 remove unused SC_THREAD 2018-09-21 09:24:49 +02:00
mariusmonton 11fae01cba Changed memory to be addressable to byte instead to word (32bits) 2018-09-20 12:22:13 +02:00
mariusmonton 8dcbf09589 Lot of changes: 
* memory module parses 03 field and sets Program Counter (PC) to right value
* almost all RV32I instructions implemented
* added Trace module to mimic ARM ITM module
* added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals
* lot of minor changes
 2018-09-19 23:44:38 +02:00
mariusmonton 1c9bfe8c60 Added Data Memory bus. Implemented LW & SW instructions. 2018-09-17 12:21:26 +02:00
mariusmonton 35e688837a initial import 2018-09-10 18:44:54 +02:00