783 lines
15 KiB
C++
783 lines
15 KiB
C++
/*!
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\file C_extension.cpp
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\brief Implement C extensions part of the RISC-V
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\author Màrius Montón
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\date August 2018
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*/
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#include "C_extension.h"
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op_C_Codes C_extension::decode() const {
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switch (opcode()) {
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case 0b00:
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switch (get_funct3()) {
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case C_ADDI4SPN:
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return OP_C_ADDI4SPN;
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break;
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case C_FLD:
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return OP_C_FLD;
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break;
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case C_LW:
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return OP_C_LW;
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break;
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case C_FLW:
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return OP_C_FLW;
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break;
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case C_FSD:
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return OP_C_FSD;
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break;
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case C_SW:
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return OP_C_SW;
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break;
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case C_FSW:
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return OP_C_FSW;
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break;
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[[unlikely]] default:
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return OP_C_ERROR;
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break;
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}
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break;
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case 0b01:
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switch (get_funct3()) {
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case C_ADDI:
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return OP_C_ADDI;
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break;
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case C_JAL:
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return OP_C_JAL;
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break;
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case C_LI:
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return OP_C_LI;
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break;
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case C_ADDI16SP:
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return OP_C_ADDI16SP;
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break;
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case C_SRLI:
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switch (m_instr.range(11, 10)) {
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case C_2_SRLI:
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return OP_C_SRLI;
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break;
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case C_2_SRAI:
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return OP_C_SRAI;
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break;
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case C_2_ANDI:
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return OP_C_ANDI;
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break;
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case C_2_SUB:
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switch (m_instr.range(6, 5)) {
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case C_3_SUB:
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return OP_C_SUB;
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break;
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case C_3_XOR:
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return OP_C_XOR;
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break;
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case C_3_OR:
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return OP_C_OR;
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break;
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case C_3_AND:
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return OP_C_AND;
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break;
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}
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}
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break;
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case C_J:
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return OP_C_J;
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break;
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case C_BEQZ:
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return OP_C_BEQZ;
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break;
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case C_BNEZ:
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return OP_C_BNEZ;
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break;
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[[unlikely]] default:
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return OP_C_ERROR;
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break;
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}
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break;
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case 0b10:
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switch (get_funct3()) {
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case C_SLLI:
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return OP_C_SLLI;
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break;
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case C_FLDSP:
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case C_LWSP:
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return OP_C_LWSP;
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break;
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case C_FLWSP:
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return OP_C_FLWSP;
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break;
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case C_JR:
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if (m_instr[12] == 0) {
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if (m_instr.range(6, 2) == 0) {
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return OP_C_JR;
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} else {
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return OP_C_MV;
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}
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} else {
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if (m_instr.range(11, 2) == 0) {
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return OP_C_EBREAK;
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} else if (m_instr.range(6, 2) == 0) {
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return OP_C_JALR;
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} else {
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return OP_C_ADD;
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}
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}
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break;
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case C_FDSP:
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break;
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case C_SWSP:
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return OP_C_SWSP;
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break;
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case C_FWWSP:
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[[unlikely]] default:
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return OP_C_ERROR;
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break;
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}
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break;
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[[unlikely]] default:
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return OP_C_ERROR;
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break;
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}
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return OP_C_ERROR;
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}
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bool C_extension::Exec_C_JR() {
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uint32_t mem_addr;
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int rs1;
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int new_pc;
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rs1 = get_rs1();
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mem_addr = 0;
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new_pc = static_cast<int32_t>(static_cast<int32_t>((regs->getValue(rs1)) + static_cast<int32_t>(mem_addr)) & 0xFFFFFFFE);
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regs->setPC(new_pc);
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if (log->getLogLevel() >= Log::INFO) {
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log->SC_log(Log::INFO) << "JR: PC <- 0x" << std::hex << new_pc << "\n";
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}
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return true;
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}
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bool C_extension::Exec_C_MV() {
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int rd, rs1, rs2;
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uint32_t calc;
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rd = get_rd();
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rs1 = 0;
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rs2 = get_rs2();
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calc = regs->getValue(rs1) + regs->getValue(rs2);
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regs->setValue(rd, static_cast<int32_t>(calc));
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if (log->getLogLevel() >= Log::INFO) {
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log->SC_log(Log::INFO) << "C.MV: x" << std::dec << rs1 << "(0x" << std::hex
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<< regs->getValue(rs1) << ") + x" << std::dec << rs2 << "(0x"
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<< std::hex << regs->getValue(rs2) << ") -> x" << std::dec << rd
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<< "(0x" << std::hex << calc << ")" << "\n";
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}
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return true;
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}
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bool C_extension::Exec_C_ADD() {
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int rd, rs1, rs2;
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uint32_t calc;
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rd = get_rs1();
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rs1 = get_rs1();
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rs2 = get_rs2();
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calc = regs->getValue(rs1) + regs->getValue(rs2);
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regs->setValue(rd, static_cast<int32_t>(calc));
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if (log->getLogLevel() >= Log::INFO) {
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log->SC_log(Log::INFO) << "C.ADD: x" << std::dec << rs1 << " + x" << rs2
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<< " -> x" << rd << "(0x" << std::hex << calc << ")" << "\n";
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}
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return true;
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}
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bool C_extension::Exec_C_LWSP() {
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uint32_t mem_addr;
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int rd, rs1;
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int32_t imm;
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uint32_t data;
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// lw rd, offset[7:2](x2)
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rd = get_rd();
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rs1 = 2;
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imm = get_imm_LWSP();
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mem_addr = imm + regs->getValue(rs1);
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data = mem_intf->readDataMem(mem_addr, 4);
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perf->dataMemoryRead();
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regs->setValue(rd, static_cast<int32_t>(data));
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if (log->getLogLevel() >= Log::INFO) {
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log->SC_log(Log::INFO) << "C.LWSP: x" << std::dec << rs1 << " + " << imm
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<< " (@0x" << std::hex << mem_addr << std::dec << ") -> x" << rd
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<< "(" << std::hex << data << ")" << std::dec << "\n";
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}
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return true;
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}
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bool C_extension::Exec_C_ADDI4SPN() {
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int rd, rs1;
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int32_t imm;
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int32_t calc;
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rd = get_rdp();
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rs1 = 2;
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imm = get_imm_ADDI4SPN();
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if (imm == 0) {
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RaiseException(EXCEPTION_CAUSE_ILLEGAL_INSTRUCTION, m_instr);
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return false;
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}
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calc = regs->getValue(rs1) + imm;
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regs->setValue(rd, calc);
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if (log->getLogLevel() >= Log::INFO) {
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log->SC_log(Log::INFO) << std::dec << "C.ADDI4SPN: x" << rs1 << "(0x"
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<< std::hex << regs->getValue(rs1) << ") + " << std::dec << imm
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<< " -> x" << rd << "(0x" << std::hex << calc << ")" << "\n";
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}
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return true;
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}
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bool C_extension::Exec_C_ADDI16SP() {
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// addi x2, x2, nzimm[9:4]
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int rd;
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int32_t imm;
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if (get_rd() == 2) {
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int rs1;
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int32_t calc;
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rd = 2;
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rs1 = 2;
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imm = get_imm_ADDI16SP();
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calc = regs->getValue(rs1) + imm;
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regs->setValue(rd, calc);
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log->SC_log(Log::INFO) << std::dec << "C.ADDI16SP: x" << rs1 << " + "
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<< std::dec << imm << " -> x" << rd << "(0x" << std::hex << calc
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<< ")" << "\n";
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} else {
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/* C.LUI OPCODE */
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rd = get_rd();
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imm = get_imm_LUI();
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regs->setValue(rd, imm);
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log->SC_log(Log::INFO) << std::dec << "C.LUI x" << rd << " <- 0x"
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<< std::hex << imm << "\n";
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}
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return true;
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}
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bool C_extension::Exec_C_SWSP() {
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// sw rs2, offset(x2)
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uint32_t mem_addr;
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int rs1, rs2;
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int32_t imm;
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uint32_t data;
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rs1 = 2;
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rs2 = get_rs2();
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imm = get_imm_CSS();
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mem_addr = imm + regs->getValue(rs1);
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data = regs->getValue(rs2);
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mem_intf->writeDataMem(mem_addr, data, 4);
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perf->dataMemoryWrite();
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if (log->getLogLevel() >= Log::INFO) {
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log->SC_log(Log::INFO) << std::dec << "C.SWSP: x" << rs2 << "(0x"
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<< std::hex << data << ") -> x" << std::dec << rs1 << " + " << imm
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<< " (@0x" << std::hex << mem_addr << std::dec << ")" << "\n";
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}
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return true;
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}
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bool C_extension::Exec_C_BEQZ() {
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int rs1;
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int new_pc;
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uint32_t val1;
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rs1 = get_rs1p();
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val1 = regs->getValue(rs1);
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if (val1 == 0) {
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new_pc = static_cast<int32_t>(regs->getPC()) + get_imm_CB();
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regs->setPC(new_pc);
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} else {
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regs->incPC(true); //PC <- PC + 2
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new_pc = static_cast<int32_t>(regs->getPC());
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}
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if (log->getLogLevel() >= Log::INFO) {
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log->SC_log(Log::INFO) << "C.BEQZ: x" << std::dec << rs1 << "(" << val1
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<< ") == 0? -> PC (0x" << std::hex << new_pc << ")" << std::dec
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<< "\n";
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}
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return true;
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}
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bool C_extension::Exec_C_BNEZ() {
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int rs1;
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int new_pc;
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uint32_t val1;
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rs1 = get_rs1p();
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val1 = regs->getValue(rs1);
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if (val1 != 0) {
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new_pc = static_cast<int32_t>(regs->getPC()) + get_imm_CB();
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regs->setPC(new_pc);
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} else {
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regs->incPC(true); //PC <- PC +2
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new_pc = static_cast<int32_t>(regs->getPC());
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}
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if (log->getLogLevel() >= Log::INFO) {
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log->SC_log(Log::INFO) << "C.BNEZ: x" << std::dec << rs1 << "(0x"
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<< std::hex << val1 << ") != 0? -> PC (0x" << std::hex << new_pc
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<< ")" << std::dec << "\n";
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}
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return true;
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}
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bool C_extension::Exec_C_LI() {
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int rd, rs1;
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int32_t imm;
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int32_t calc;
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rd = get_rd();
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rs1 = 0;
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imm = get_imm_ADDI();
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calc = regs->getValue(rs1) + imm;
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regs->setValue(rd, calc);
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if (log->getLogLevel() >= Log::INFO) {
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log->SC_log(Log::INFO) << std::dec << "C.LI: x" << rs1 << "("
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<< regs->getValue(rs1) << ") + " << imm << " -> x" << rd << "("
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<< calc << ")" << "\n";
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}
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return true;
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}
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bool C_extension::Exec_C_SRLI() {
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int rd, rs1, rs2;
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uint32_t shift;
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uint32_t calc;
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rd = get_rs1p();
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rs1 = get_rs1p();
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rs2 = get_rs2();
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shift = rs2 & 0x1F;
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calc = ((uint32_t) regs->getValue(rs1)) >> shift;
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regs->setValue(rd, static_cast<int32_t>(calc));
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if (log->getLogLevel() >= Log::INFO) {
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log->SC_log(Log::INFO) << "C.SRLI: x" << rs1 << " >> " << shift << " -> x"
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<< rd << "\n";
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}
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return true;
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}
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bool C_extension::Exec_C_SRAI() {
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int rd, rs1, rs2;
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uint32_t shift;
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int32_t calc;
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rd = get_rs1p();
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rs1 = get_rs1p();
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rs2 = get_rs2();
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shift = rs2 & 0x1F;
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calc = (int32_t) regs->getValue(rs1) >> shift;
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regs->setValue(rd, calc);
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if (log->getLogLevel() >= Log::INFO) {
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log->SC_log(Log::INFO) << "C.SRAI: x" << rs1 << " >> " << std::dec << shift
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<< " -> x" << rd << "(" << calc << ")" << "\n";
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}
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return true;
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}
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bool C_extension::Exec_C_SLLI() {
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int rd, rs1, rs2;
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uint32_t shift;
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uint32_t calc;
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rd = get_rs1p();
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rs1 = get_rs1p();
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rs2 = get_imm_ADDI();
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shift = rs2 & 0x1F;
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calc = ((uint32_t) regs->getValue(rs1)) << shift;
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regs->setValue(rd, static_cast<int32_t>(calc));
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if (log->getLogLevel() >= Log::INFO) {
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log->SC_log(Log::INFO) << "C.SLLI: x" << std::dec << rs1 << " << " << shift
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<< " -> x" << rd << "(0x" << calc << ")" << "\n";
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}
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return true;
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}
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bool C_extension::Exec_C_ANDI() {
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int rd, rs1;
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uint32_t imm;
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uint32_t aux;
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uint32_t calc;
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rd = get_rs1p();
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rs1 = get_rs1p();
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imm = get_imm_ADDI();
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aux = regs->getValue(rs1);
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calc = aux & imm;
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regs->setValue(rd, static_cast<int32_t>(calc));
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if (log->getLogLevel() >= Log::INFO) {
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log->SC_log(Log::INFO) << "C.ANDI: x" << rs1 << "(" << aux << ") AND "
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<< imm << " -> x" << rd << "\n";
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}
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return true;
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}
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bool C_extension::Exec_C_SUB() {
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int rd, rs1, rs2;
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uint32_t calc;
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rd = get_rs1p();
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rs1 = get_rs1p();
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rs2 = get_rs2p();
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calc = regs->getValue(rs1) - regs->getValue(rs2);
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regs->setValue(rd, static_cast<int32_t>(calc));
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if (log->getLogLevel() >= Log::INFO) {
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log->SC_log(Log::INFO) << "C.SUB: x" << std::dec << rs1 << " - x" << rs2
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<< " -> x" << rd << "\n";
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}
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return true;
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}
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bool C_extension::Exec_C_XOR() {
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int rd, rs1, rs2;
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uint32_t calc;
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rd = get_rs1p();
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rs1 = get_rs1p();
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rs2 = get_rs2p();
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calc = regs->getValue(rs1) ^ regs->getValue(rs2);
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regs->setValue(rd, static_cast<int32_t>(calc));
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if (log->getLogLevel() >= Log::INFO) {
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log->SC_log(Log::INFO) << "C.XOR: x" << std::dec << rs1 << " XOR x" << rs2
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<< "-> x" << rd << "\n";
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}
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return true;
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}
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bool C_extension::Exec_C_OR() {
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int rd, rs1, rs2;
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uint32_t calc;
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rd = get_rs1p();
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rs1 = get_rs1p();
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rs2 = get_rs2p();
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calc = regs->getValue(rs1) | regs->getValue(rs2);
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regs->setValue(rd, static_cast<int32_t>(calc));
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if (log->getLogLevel() >= Log::INFO) {
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log->SC_log(Log::INFO) << "C_OR: x" << std::dec << rs1 << " OR x" << rs2
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<< "-> x" << rd << "\n";
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}
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return true;
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}
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bool C_extension::Exec_C_AND() {
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int rd, rs1, rs2;
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uint32_t calc;
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rd = get_rs1p();
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rs1 = get_rs1p();
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rs2 = get_rs2p();
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calc = regs->getValue(rs1) & regs->getValue(rs2);
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regs->setValue(rd, static_cast<int32_t>(calc));
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if (log->getLogLevel() >= Log::INFO) {
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|
log->SC_log(Log::INFO) << "C.AND: x" << std::dec << rs1 << " AND x" << rs2
|
|
<< "-> x" << rd << "\n";
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool C_extension::Exec_C_ADDI() const {
|
|
int rd, rs1;
|
|
int32_t imm;
|
|
int32_t calc;
|
|
|
|
rd = get_rd();
|
|
rs1 = rd;
|
|
imm = get_imm_ADDI();
|
|
|
|
calc = regs->getValue(rs1) + imm;
|
|
regs->setValue(rd, calc);
|
|
|
|
if (log->getLogLevel() >= Log::INFO) {
|
|
log->SC_log(Log::INFO) << "C.ADDI: x" << std::dec << rs1 << " + " << imm
|
|
<< " -> x" << std::dec << rd << "(0x" << std::hex << calc << ")"
|
|
<< "\n";
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool C_extension::Exec_C_JALR() {
|
|
uint32_t mem_addr = 0;
|
|
int rd, rs1;
|
|
int new_pc, old_pc;
|
|
|
|
rd = 1;
|
|
rs1 = get_rs1();
|
|
|
|
old_pc = static_cast<int32_t>(regs->getPC());
|
|
regs->setValue(rd, old_pc + 2);
|
|
|
|
new_pc = static_cast<int32_t>((regs->getValue(rs1) + mem_addr) & 0xFFFFFFFE);
|
|
regs->setPC(new_pc);
|
|
|
|
if (log->getLogLevel() >= Log::INFO) {
|
|
log->SC_log(Log::INFO) << "C.JALR: x" << std::dec << rd << " <- 0x"
|
|
<< std::hex << old_pc + 4 << " PC <- 0x" << std::hex << new_pc
|
|
<< "\n";
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool C_extension::Exec_C_LW() {
|
|
uint32_t mem_addr;
|
|
int rd, rs1;
|
|
int32_t imm;
|
|
uint32_t data;
|
|
|
|
rd = get_rdp();
|
|
rs1 = get_rs1p();
|
|
imm = get_imm_L();
|
|
|
|
mem_addr = imm + regs->getValue(rs1);
|
|
data = mem_intf->readDataMem(mem_addr, 4);
|
|
perf->dataMemoryRead();
|
|
regs->setValue(rd, static_cast<int32_t>(data));
|
|
|
|
if (log->getLogLevel() >= Log::INFO) {
|
|
log->SC_log(Log::INFO) << std::dec << "C.LW: x" << rs1 << "(0x" << std::hex
|
|
<< regs->getValue(rs1) << ") + " << std::dec << imm << " (@0x"
|
|
<< std::hex << mem_addr << std::dec << ") -> x" << rd << std::hex
|
|
<< " (0x" << data << ")" << "\n";
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool C_extension::Exec_C_SW() {
|
|
uint32_t mem_addr;
|
|
int rs1, rs2;
|
|
int32_t imm;
|
|
uint32_t data;
|
|
|
|
rs1 = get_rs1p();
|
|
rs2 = get_rs2p();
|
|
imm = get_imm_L();
|
|
|
|
mem_addr = imm + regs->getValue(rs1);
|
|
data = regs->getValue(rs2);
|
|
|
|
mem_intf->writeDataMem(mem_addr, data, 4);
|
|
perf->dataMemoryWrite();
|
|
|
|
if (log->getLogLevel() >= Log::INFO) {
|
|
log->SC_log(Log::INFO) << "C.SW: x" << std::dec << rs2 << "(0x" << std::hex
|
|
<< data << ") -> x" << std::dec << rs1 << " + 0x" << std::hex << imm
|
|
<< " (@0x" << std::hex << mem_addr << std::dec << ")" << "\n";
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool C_extension::Exec_C_JAL(int m_rd) {
|
|
int32_t mem_addr;
|
|
int rd;
|
|
int new_pc, old_pc;
|
|
|
|
rd = m_rd;
|
|
mem_addr = get_imm_J();
|
|
old_pc = static_cast<int32_t>(regs->getPC());
|
|
|
|
new_pc = old_pc + mem_addr;
|
|
regs->setPC(new_pc);
|
|
|
|
old_pc = old_pc + 2;
|
|
regs->setValue(rd, old_pc);
|
|
|
|
if (log->getLogLevel() >= Log::INFO) {
|
|
log->SC_log(Log::INFO) << "C.JAL: x" << std::dec << rd << " <- 0x"
|
|
<< std::hex << old_pc << std::dec << ". PC + 0x" << std::hex
|
|
<< mem_addr << " -> PC (0x" << new_pc << ")" << "\n";
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
bool C_extension::Exec_C_EBREAK() {
|
|
|
|
log->SC_log(Log::INFO) << "C.EBREAK" << "\n";
|
|
std::cout << "\n" << "C.EBRAK Instruction called, dumping information"
|
|
<< "\n";
|
|
regs->dump();
|
|
std::cout << "Simulation time " << sc_core::sc_time_stamp() << "\n";
|
|
perf->dump();
|
|
|
|
sc_core::sc_stop();
|
|
|
|
return true;
|
|
}
|
|
|
|
bool C_extension::process_instruction(Instruction *inst, bool *breakpoint) {
|
|
bool PC_not_affected = true;
|
|
|
|
*breakpoint = false;
|
|
|
|
setInstr(inst->getInstr());
|
|
|
|
switch (decode()) {
|
|
case OP_C_ADDI4SPN:
|
|
PC_not_affected = Exec_C_ADDI4SPN();
|
|
break;
|
|
case OP_C_LW:
|
|
Exec_C_LW();
|
|
break;
|
|
case OP_C_SW:
|
|
Exec_C_SW();
|
|
break;
|
|
case OP_C_ADDI:
|
|
Exec_C_ADDI();
|
|
break;
|
|
case OP_C_JAL:
|
|
Exec_C_JAL(1);
|
|
PC_not_affected = false;
|
|
break;
|
|
case OP_C_J:
|
|
Exec_C_JAL(0);
|
|
PC_not_affected = false;
|
|
break;
|
|
case OP_C_LI:
|
|
Exec_C_LI();
|
|
break;
|
|
case OP_C_SLLI:
|
|
Exec_C_SLLI();
|
|
break;
|
|
case OP_C_LWSP:
|
|
Exec_C_LWSP();
|
|
break;
|
|
case OP_C_JR:
|
|
Exec_C_JR();
|
|
PC_not_affected = false;
|
|
break;
|
|
case OP_C_MV:
|
|
Exec_C_MV();
|
|
break;
|
|
case OP_C_JALR:
|
|
Exec_C_JALR();
|
|
PC_not_affected = false;
|
|
break;
|
|
case OP_C_ADD:
|
|
Exec_C_ADD();
|
|
break;
|
|
case OP_C_SWSP:
|
|
Exec_C_SWSP();
|
|
break;
|
|
case OP_C_ADDI16SP:
|
|
Exec_C_ADDI16SP();
|
|
break;
|
|
case OP_C_BEQZ:
|
|
Exec_C_BEQZ();
|
|
PC_not_affected = false;
|
|
break;
|
|
case OP_C_BNEZ:
|
|
Exec_C_BNEZ();
|
|
PC_not_affected = false;
|
|
break;
|
|
case OP_C_SRLI:
|
|
Exec_C_SRLI();
|
|
break;
|
|
case OP_C_SRAI:
|
|
Exec_C_SRAI();
|
|
break;
|
|
case OP_C_ANDI:
|
|
Exec_C_ANDI();
|
|
break;
|
|
case OP_C_SUB:
|
|
Exec_C_SUB();
|
|
break;
|
|
case OP_C_XOR:
|
|
Exec_C_XOR();
|
|
break;
|
|
case OP_C_OR:
|
|
Exec_C_OR();
|
|
break;
|
|
case OP_C_AND:
|
|
Exec_C_AND();
|
|
break;
|
|
case OP_C_EBREAK:
|
|
Exec_C_EBREAK();
|
|
std::cout << "C_EBREAK" << std::endl;
|
|
*breakpoint = true;
|
|
break;
|
|
[[unlikely]] default:
|
|
std::cout << "C instruction not implemented yet" << "\n";
|
|
inst->dump();
|
|
NOP();
|
|
break;
|
|
}
|
|
|
|
return PC_not_affected;
|
|
}
|