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risc-v-tlm/inc
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mariusmonton 8dcbf09589 Lot of changes: 
* memory module parses 03 field and sets Program Counter (PC) to right value
* almost all RV32I instructions implemented
* added Trace module to mimic ARM ITM module
* added BusCtrl module as bus controler (very simple) to allow CPU & RISC_V_execute to access memory & peripherals
* lot of minor changes
 		2018-09-19 23:44:38 +02:00
..
BusCtrl.h Lot of changes: 2018-09-19 23:44:38 +02:00
CPU.h Lot of changes: 2018-09-19 23:44:38 +02:00
Instruction.h initial import 2018-09-10 18:44:54 +02:00
Log.h Lot of changes: 2018-09-19 23:44:38 +02:00
Memory.h Lot of changes: 2018-09-19 23:44:38 +02:00
Performance.h initial import 2018-09-10 18:44:54 +02:00
RISC_V_execute.h Added Data Memory bus. Implemented LW & SW instructions. 2018-09-17 12:21:26 +02:00
Registers.h Lot of changes: 2018-09-19 23:44:38 +02:00
Trace.h Lot of changes: 2018-09-19 23:44:38 +02:00