515 lines
11 KiB
C++
515 lines
11 KiB
C++
#include "CPU.h"
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SC_HAS_PROCESS(CPU);
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CPU::CPU(sc_module_name name, uint32_t PC): sc_module(name)
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, instr_bus("instr_bus")
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{
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register_bank = new Registers();
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exec = new Execute("Execute", register_bank);
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perf = Performance::getInstance();
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log = Log::getInstance();
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register_bank->setPC(PC);
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register_bank->setValue(Registers::sp, (0xD0000 / 4) - 1);
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//register_bank->setValue(Registers::sp, (0x10000000 / 4) - 1);
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irq_line_socket.register_b_transport(this, &CPU::call_interrupt);
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interrupt = false;
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SC_THREAD(CPU_thread);
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}
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CPU::~CPU() {
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cout << "*********************************************" << endl;
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register_bank->dump();
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cout << "end time: " << sc_time_stamp() << endl;
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perf->dump();
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cout << "*********************************************" << endl;
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}
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bool CPU::cpu_process_IRQ() {
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uint32_t csr_temp;
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uint32_t new_pc, old_pc;
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bool ret_value = false;
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if (interrupt == true){
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csr_temp = register_bank->getCSR(CSR_MIP);
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if ( (csr_temp & (1 << 11) ) == 0 ) {
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csr_temp |= (1 << 11); // MEIP bit in MIP register (11th bit)
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register_bank->setCSR(CSR_MIP, csr_temp);
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// cout << "time: " << sc_time_stamp() << ". CPU: interrupt" << endl;
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log->SC_log(Log::DEBUG) << "Interrupt!" << endl;
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/* updated MEPC register */
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old_pc = register_bank->getPC();
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register_bank->setCSR(CSR_MEPC, old_pc);
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log->SC_log(Log::INFO) << "Old PC Value 0x" << hex << old_pc << endl;
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/* update MCAUSE register */
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register_bank->setCSR(CSR_MCAUSE, 0x8000000);
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/* set new PC address */
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new_pc = register_bank->getCSR(CSR_MTVEC);
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new_pc = new_pc & 0xFFFFFFFC; // last two bits always to 0
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log->SC_log(Log::DEBUG) << "NEW PC Value 0x" << hex << new_pc << endl;
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register_bank->setPC(new_pc);
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ret_value = true;
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interrupt = false;
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}
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} else {
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csr_temp = register_bank->getCSR(CSR_MIP);
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csr_temp &= ~(1 << 11);
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register_bank->setCSR(CSR_MIP, csr_temp);
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}
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return ret_value;
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}
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bool CPU::process_c_instruction(Instruction &inst) {
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bool PC_not_affected = true;
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C_Instruction c_inst(inst.getInstr());
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switch(c_inst.decode()) {
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case OP_C_ADDI4SPN:
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PC_not_affected = exec->C_ADDI4SPN(inst);
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break;
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case OP_C_LW:
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exec->LW(inst, true);
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break;
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case OP_C_SW:
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exec->SW(inst, true);
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break;
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case OP_C_ADDI:
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exec->ADDI(inst, true);
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break;
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case OP_C_JAL:
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exec->JAL(inst, true, 1);
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PC_not_affected = false;
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break;
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case OP_C_J:
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exec->JAL(inst, true, 0);
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PC_not_affected = false;
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break;
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case OP_C_LI:
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exec->C_LI(inst);
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break;
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case OP_C_SLLI:
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exec->C_SLLI(inst);
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break;
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case OP_C_LWSP:
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exec->C_LWSP(inst);
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break;
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case OP_C_JR:
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exec->C_JR(inst);
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PC_not_affected = false;
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break;
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case OP_C_MV:
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exec->C_MV(inst);
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break;
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case OP_C_JALR:
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exec->JALR(inst, true);
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PC_not_affected = false;
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break;
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case OP_C_ADD:
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exec->C_ADD(inst);
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break;
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case OP_C_SWSP:
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exec->C_SWSP(inst);
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break;
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case OP_C_ADDI16SP:
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exec->C_ADDI16SP(inst);
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break;
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case OP_C_BEQZ:
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exec->C_BEQZ(inst);
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PC_not_affected = false;
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break;
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case OP_C_BNEZ:
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exec->C_BNEZ(inst);
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PC_not_affected = false;
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break;
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case OP_C_SRLI:
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exec->C_SRLI(inst);
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break;
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case OP_C_SRAI:
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exec->C_SRAI(inst);
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break;
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case OP_C_ANDI:
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exec->C_ANDI(inst);
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break;
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case OP_C_SUB:
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exec->C_SUB(inst);
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break;
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case OP_C_XOR:
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exec->C_XOR(inst);
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break;
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case OP_C_OR:
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exec->C_OR(inst);
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break;
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case OP_C_AND:
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exec->C_AND(inst);
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break;
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default:
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std::cout << "C instruction not implemented yet" << endl;
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inst.dump();
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exec->NOP(inst);
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//sc_stop();
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break;
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}
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return PC_not_affected;
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}
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bool CPU::process_m_instruction(Instruction &inst) {
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bool PC_not_affected = true;
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M_Instruction m_inst(inst.getInstr());
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switch(m_inst.decode()) {
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case OP_M_MUL:
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exec->M_MUL(inst);
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break;
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case OP_M_MULH:
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exec->M_MULH(inst);
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break;
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case OP_M_MULHSU:
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exec->M_MULHSU(inst);
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break;
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case OP_M_MULHU:
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exec->M_MULHU(inst);
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break;
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case OP_M_DIV:
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exec->M_DIV(inst);
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break;
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case OP_M_DIVU:
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exec->M_DIVU(inst);
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break;
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case OP_M_REM:
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exec->M_REM(inst);
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break;
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case OP_M_REMU:
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exec->M_REMU(inst);
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break;
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default:
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std::cout << "M instruction not implemented yet" << endl;
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inst.dump();
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exec->NOP(inst);
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break;
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}
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return PC_not_affected;
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}
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bool CPU::process_a_instruction(Instruction inst) {
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bool PC_not_affected = true;
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A_Instruction a_inst(inst.getInstr());
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switch(a_inst.decode()) {
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case OP_A_LR:
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exec->A_LR(inst);
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break;
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case OP_A_SC:
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exec->A_SC(inst);
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break;
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case OP_A_AMOSWAP:
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exec->A_AMOSWAP(inst);
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break;
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case OP_A_AMOADD:
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exec->A_AMOADD(inst);
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break;
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case OP_A_AMOXOR:
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exec->A_AMOXOR(inst);
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break;
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case OP_A_AMOAND:
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exec->A_AMOAND(inst);
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break;
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case OP_A_AMOOR:
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exec->A_AMOOR(inst);
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break;
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case OP_A_AMOMIN:
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exec->A_AMOMIN(inst);
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break;
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case OP_A_AMOMAX:
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exec->A_AMOMAX(inst);
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break;
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case OP_A_AMOMINU:
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exec->A_AMOMINU(inst);
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break;
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case OP_A_AMOMAXU:
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exec->A_AMOMAXU(inst);
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break;
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default:
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std::cout << "A instruction not implemented yet" << endl;
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inst.dump();
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exec->NOP(inst);
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break;
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}
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return PC_not_affected;
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}
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bool CPU::process_base_instruction(Instruction &inst) {
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bool PC_not_affected = true;
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switch(inst.decode()) {
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case OP_LUI:
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exec->LUI(inst);
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break;
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case OP_AUIPC:
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exec->AUIPC(inst);
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break;
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case OP_JAL:
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exec->JAL(inst);
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PC_not_affected = false;
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break;
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case OP_JALR:
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exec->JALR(inst);
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PC_not_affected = false;
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break;
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case OP_BEQ:
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exec->BEQ(inst);
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PC_not_affected = false;
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break;
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case OP_BNE:
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exec->BNE(inst);
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PC_not_affected = false;
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break;
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case OP_BLT:
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exec->BLT(inst);
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PC_not_affected = false;
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break;
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case OP_BGE:
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exec->BGE(inst);
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PC_not_affected = false;
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break;
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case OP_BLTU:
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exec->BLTU(inst);
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PC_not_affected = false;
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break;
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case OP_BGEU:
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exec->BGEU(inst);
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PC_not_affected = false;
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break;
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case OP_LB:
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exec->LB(inst);
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break;
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case OP_LH:
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exec->LH(inst);
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break;
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case OP_LW:
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exec->LW(inst);
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break;
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case OP_LBU:
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exec->LBU(inst);
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break;
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case OP_LHU:
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exec->LHU(inst);
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break;
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case OP_SB:
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exec->SB(inst);
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break;
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case OP_SH:
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exec->SH(inst);
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break;
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case OP_SW:
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exec->SW(inst);
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break;
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case OP_ADDI:
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exec->ADDI(inst);
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break;
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case OP_SLTI:
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exec->SLTI(inst);
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break;
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case OP_SLTIU:
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exec->SLTIU(inst);
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break;
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case OP_XORI:
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exec->XORI(inst);
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break;
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case OP_ORI:
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exec->ORI(inst);
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break;
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case OP_ANDI:
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exec->ANDI(inst);
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break;
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case OP_SLLI:
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PC_not_affected = exec->SLLI(inst);
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break;
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case OP_SRLI:
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exec->SRLI(inst);
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break;
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case OP_SRAI:
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exec->SRAI(inst);
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break;
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case OP_ADD:
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exec->ADD(inst);
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break;
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case OP_SUB:
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exec->SUB(inst);
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break;
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case OP_SLL:
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exec->SLL(inst);
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break;
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case OP_SLT:
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exec->SLT(inst);
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break;
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case OP_SLTU:
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exec->SLTU(inst);
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break;
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case OP_XOR:
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exec->XOR(inst);
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break;
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case OP_SRL:
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exec->SRL(inst);
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break;
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case OP_SRA:
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exec->SRA(inst);
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break;
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case OP_OR:
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exec->OR(inst);
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break;
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case OP_AND:
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exec->AND(inst);
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break;
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case OP_FENCE:
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exec->FENCE(inst);
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break;
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case OP_ECALL:
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exec->ECALL(inst);
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break;
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case OP_EBREAK:
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exec->EBREAK(inst);
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break;
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case OP_CSRRW:
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exec->CSRRW(inst);
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break;
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case OP_CSRRS:
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exec->CSRRS(inst);
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break;
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case OP_CSRRC:
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exec->CSRRC(inst);
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break;
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case OP_CSRRWI:
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exec->CSRRWI(inst);
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break;
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case OP_CSRRSI:
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exec->CSRRSI(inst);
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break;
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case OP_CSRRCI:
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exec->CSRRCI(inst);
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break;
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case OP_MRET:
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exec->MRET(inst);
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PC_not_affected = false;
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break;
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case OP_SRET:
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exec->SRET(inst);
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PC_not_affected = false;
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break;
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case OP_WFI:
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exec->WFI(inst);
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break;
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case OP_SFENCE:
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exec->SFENCE(inst);
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break;
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default:
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std::cout << "Wrong instruction" << endl;
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inst.dump();
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exec->NOP(inst);
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//sc_stop();
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break;
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}
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return PC_not_affected;
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}
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/**
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* main thread for CPU simulation
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* @brief CPU mai thread
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*/
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void CPU::CPU_thread(void) {
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tlm::tlm_generic_payload* trans = new tlm::tlm_generic_payload;
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uint32_t INSTR;
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sc_time delay = SC_ZERO_TIME;
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bool PC_not_affected = false;
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bool incPCby2 = false;
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trans->set_command( tlm::TLM_READ_COMMAND );
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trans->set_data_ptr( reinterpret_cast<unsigned char*>(&INSTR) );
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trans->set_data_length( 4 );
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trans->set_streaming_width( 4 ); // = data_length to indicate no streaming
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trans->set_byte_enable_ptr( 0 ); // 0 indicates unused
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trans->set_dmi_allowed( false ); // Mandatory initial value
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trans->set_response_status( tlm::TLM_INCOMPLETE_RESPONSE );
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//register_bank->dump();
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while(1) {
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/* Get new PC value */
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//cout << "CPU: PC 0x" << hex << (uint32_t) register_bank->getPC() << endl;
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trans->set_address( register_bank->getPC() );
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instr_bus->b_transport( *trans, delay);
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perf->codeMemoryRead();
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if ( trans->is_response_error() ) {
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SC_REPORT_ERROR("CPU base", "Read memory");
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} else {
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log->SC_log(Log::INFO) << "PC: 0x" << hex
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<< register_bank->getPC() << ". ";
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Instruction inst(INSTR);
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/* check what type of instruction is and execute it */
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switch(inst.check_extension()) {
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case BASE_EXTENSION:
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PC_not_affected = process_base_instruction(inst);
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incPCby2 = false;
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break;
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case C_EXTENSION:
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PC_not_affected = process_c_instruction(inst);
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incPCby2 = true;
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break;
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case M_EXTENSION:
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PC_not_affected = process_m_instruction(inst);
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incPCby2 = false;
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break;
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case A_EXTENSION:
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PC_not_affected = process_a_instruction(inst);
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incPCby2 = false;
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break;
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default:
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std::cout << "Extension not implemented yet" << std::endl;
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inst.dump();
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exec->NOP(inst);
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} // switch (inst.check_extension())
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}
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perf->instructionsInc();
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if (PC_not_affected == true) {
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register_bank->incPC(incPCby2);
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}
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/* Process IRQ (if any) */
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cpu_process_IRQ();
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/* Fixed instruction time to 10 ns (i.e. 100 MHz)*/
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sc_core::wait(10, SC_NS);
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} // while(1)
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} // CPU_thread
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void CPU::call_interrupt(tlm::tlm_generic_payload &trans, sc_time &delay) {
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interrupt = true;
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}
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