347 lines
6.2 KiB
C++
347 lines
6.2 KiB
C++
/*!
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\file BASE_ISA.h
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\brief RISC-V ISA implementation
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\author Màrius Montón
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\date August 2018
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*/
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// SPDX-License-Identifier: GPL-3.0-or-later
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#ifndef Execute_H
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#define Execute_H
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#define SC_INCLUDE_DYNAMIC_PROCESSES
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#include "systemc"
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#include "tlm.h"
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#include "tlm_utils/simple_initiator_socket.h"
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#include "memory.h"
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#include "MemoryInterface.h"
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#include "Instruction.h"
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#include "C_extension.h"
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#include "M_extension.h"
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#include "A_extension.h"
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#include "Registers.h"
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typedef enum {
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OP_LUI,
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OP_AUIPC,
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OP_JAL,
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OP_JALR,
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OP_BEQ,
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OP_BNE,
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OP_BLT,
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OP_BGE,
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OP_BLTU,
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OP_BGEU,
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OP_LB,
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OP_LH,
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OP_LW,
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OP_LBU,
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OP_LHU,
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OP_SB,
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OP_SH,
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OP_SW,
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OP_ADDI,
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OP_SLTI,
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OP_SLTIU,
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OP_XORI,
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OP_ORI,
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OP_ANDI,
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OP_SLLI,
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OP_SRLI,
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OP_SRAI,
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OP_ADD,
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OP_SUB,
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OP_SLL,
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OP_SLT,
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OP_SLTU,
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OP_XOR,
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OP_SRL,
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OP_SRA,
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OP_OR,
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OP_AND,
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OP_FENCE,
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OP_ECALL,
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OP_EBREAK,
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OP_CSRRW,
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OP_CSRRS,
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OP_CSRRC,
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OP_CSRRWI,
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OP_CSRRSI,
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OP_CSRRCI,
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OP_URET,
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OP_SRET,
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OP_MRET,
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OP_WFI,
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OP_SFENCE,
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OP_ERROR
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} opCodes;
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/**
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* @brief Risc_V execute module
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*/
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class BASE_ISA: public extension_base {
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public:
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/**
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* @brief Constructor, same as base class
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*/
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using extension_base::extension_base;
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/**
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* @brief Access to funct7 field
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* @return funct7 field
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*/
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inline std::int32_t get_funct7() const {
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return m_instr.range(31, 25);
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}
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/**
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* @brief Sets func7 field
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* @param value desired func7 value
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*/
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inline void set_func7(std::int32_t value) {
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m_instr.range(31, 25) = value;
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}
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/**
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* @brief Gets immediate field value for I-type
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* @return immediate_I field
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*/
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inline std::int32_t get_imm_I() const {
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std::int32_t aux = 0;
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aux = m_instr.range(31, 20);
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/* sign extension (optimize) */
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if (m_instr[31] == 1) {
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aux |= (0b11111111111111111111) << 12;
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}
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return aux;
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}
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/**
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* @brief Sets immediate field for I-type
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* @param value desired I value
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*/
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inline void set_imm_I(std::int32_t value) {
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m_instr.range(31, 20) = value;
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}
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/**
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* @brief Gets immediate field value for S-type
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* @return immediate_S field
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*/
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inline std::int32_t get_imm_S() const {
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std::int32_t aux = 0;
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aux = m_instr.range(31, 25) << 5;
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aux |= m_instr.range(11, 7);
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if (m_instr[31] == 1) {
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aux |= (0b11111111111111111111) << 12;
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}
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return aux;
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}
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/**
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* @brief Gets immediate field value for U-type
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* @return immediate_U field
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*/
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inline std::int32_t get_imm_U() const {
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return m_instr.range(31, 12);
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}
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/**
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* @brief Sets immediate field for U-type
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* @param value desired U value
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*/
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inline void set_imm_U(std::int32_t value) {
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m_instr.range(31, 12) = (value << 12);
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}
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/**
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* @brief Gets immediate field value for B-type
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* @return immediate_B field
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*/
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inline std::int32_t get_imm_B() const {
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std::int32_t aux = 0;
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aux |= m_instr[7] << 11;
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aux |= m_instr.range(30, 25) << 5;
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aux |= m_instr[31] << 12;
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aux |= m_instr.range(11, 8) << 1;
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if (m_instr[31] == 1) {
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aux |= (0b11111111111111111111) << 12;
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}
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return aux;
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}
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/**
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* @brief Sets immediate field for B-type
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* @param value desired B value
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*/
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inline void set_imm_B(std::int32_t value) {
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sc_dt::sc_uint<32> aux = value;
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m_instr[31] = aux[12];
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m_instr.range(30, 25) = aux.range(10, 5);
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m_instr.range(11, 7) = aux.range(4, 1);
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m_instr[6] = aux[11];
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}
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/**
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* @brief Gets immediate field value for J-type
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* @return immediate_J field
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*/
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inline std::int32_t get_imm_J() const {
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std::int32_t aux = 0;
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aux = m_instr[31] << 20;
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aux |= m_instr.range(19, 12) << 12;
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aux |= m_instr[20] << 11;
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aux |= m_instr.range(30, 21) << 1;
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/* bit extension (better way to do that?) */
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if (m_instr[31] == 1) {
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aux |= (0b111111111111) << 20;
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}
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return aux;
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}
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/**
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* @brief Sets immediate field for J-type
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* @param value desired J value
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*/
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inline void set_imm_J(std::int32_t value) {
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sc_dt::sc_uint<32> aux = (value << 20);
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m_instr[31] = aux[20];
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m_instr.range(30, 21) = aux.range(10, 1);
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m_instr[20] = aux[11];
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m_instr.range(19, 12) = aux.range(19, 12);
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}
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/**
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* @brief Returns shamt field for Shifts instructions
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* @return value corresponding to inst(25:20)
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*/
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inline std::int32_t get_shamt() const {
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return static_cast<std::int32_t>(m_instr.range(25, 20));
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}
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/**
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* @brief Returns CSR field for CSR instructions
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* @return value corresponding to instr(31:20)
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*/
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inline std::int32_t get_csr() const {
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std::int32_t aux = 0;
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aux = static_cast<std::int32_t>(m_instr.range(31, 20));
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return aux;
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}
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/**
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* @brief Access to opcode field
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* @return return opcode field
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*/
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inline std::int32_t opcode() const override {
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return static_cast<std::int32_t>(m_instr.range(6, 0));
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}
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bool Exec_LUI() const;
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bool Exec_AUIPC() const;
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bool Exec_JAL() const;
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bool Exec_JALR();
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bool Exec_BEQ() const;
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bool Exec_BNE() const;
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bool Exec_BLT() const;
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bool Exec_BGE() const;
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bool Exec_BLTU() const;
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bool Exec_BGEU() const;
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bool Exec_LB() const;
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bool Exec_LH() const;
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bool Exec_LW() const;
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bool Exec_LBU() const;
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bool Exec_LHU() const;
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bool Exec_SB() const;
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bool Exec_SH() const;
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bool Exec_SW() const;
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bool Exec_SBU() const;
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bool Exec_SHU() const;
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bool Exec_ADDI() const;
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bool Exec_SLTI() const;
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bool Exec_SLTIU() const;
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bool Exec_XORI() const;
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bool Exec_ORI() const;
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bool Exec_ANDI() const;
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bool Exec_SLLI();
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bool Exec_SRLI() const;
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bool Exec_SRAI() const;
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bool Exec_ADD() const;
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bool Exec_SUB() const;
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bool Exec_SLL() const;
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bool Exec_SLT() const;
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bool Exec_SLTU() const;
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bool Exec_XOR() const;
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bool Exec_SRL() const;
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bool Exec_SRA() const;
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bool Exec_OR() const;
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bool Exec_AND() const;
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bool Exec_FENCE() const;
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bool Exec_ECALL();
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bool Exec_EBREAK();
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bool Exec_CSRRW() const;
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bool Exec_CSRRS() const;
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bool Exec_CSRRC() const;
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bool Exec_CSRRWI() const;
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bool Exec_CSRRSI() const;
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bool Exec_CSRRCI() const;
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/*********************** Privileged Instructions ******************************/
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bool Exec_MRET() const;
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bool Exec_SRET() const;
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bool Exec_WFI() const;
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bool Exec_SFENCE() const;
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/**
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* @brief Executes default ISA instruction
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* @param inst instruction to execute
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* @return true if PC is affected by instruction
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*/
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bool process_instruction(Instruction &inst, bool *breakpoint = nullptr);
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/**
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* @brief Decodes opcode of instruction
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* @return opcode of instruction
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*/
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opCodes decode();
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};
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#endif
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