66 lines
1.8 KiB
C++
66 lines
1.8 KiB
C++
/**
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@file BusCtrl.cpp
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@brief Basic TLM-2 Bus controller
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@author Màrius Montón
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@date September 2018
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*/
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// SPDX-License-Identifier: GPL-3.0-or-later
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#include "BusCtrl.h"
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SC_HAS_PROCESS(BusCtrl);
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BusCtrl::BusCtrl(sc_core::sc_module_name const name) :
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sc_module(name), cpu_instr_socket("cpu_instr_socket"), cpu_data_socket(
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"cpu_data_socket"), memory_socket("memory_socket"), trace_socket(
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"trace_socket") {
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cpu_instr_socket.register_b_transport(this, &BusCtrl::b_transport);
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cpu_data_socket.register_b_transport(this, &BusCtrl::b_transport);
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log = Log::getInstance();
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cpu_instr_socket.register_get_direct_mem_ptr(this,
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&BusCtrl::instr_direct_mem_ptr);
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memory_socket.register_invalidate_direct_mem_ptr(this,
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&BusCtrl::invalidate_direct_mem_ptr);
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}
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void BusCtrl::b_transport(tlm::tlm_generic_payload &trans,
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sc_core::sc_time &delay) {
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sc_dt::uint64 adr = trans.get_address() / 4;
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switch (adr) {
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case TIMER_MEMORY_ADDRESS_HI / 4:
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case TIMER_MEMORY_ADDRESS_LO / 4:
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case TIMERCMP_MEMORY_ADDRESS_HI / 4:
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case TIMERCMP_MEMORY_ADDRESS_LO / 4:
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timer_socket->b_transport(trans, delay);
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break;
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case TRACE_MEMORY_ADDRESS / 4:
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trace_socket->b_transport(trans, delay);
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break;
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[[likely]] default:
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memory_socket->b_transport(trans, delay);
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break;
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}
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#if 0
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if (cmd == tlm::TLM_READ_COMMAND) {
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log->SC_log(Log::DEBUG) << "RD Address: @0x" << hex << adr << dec << endl;
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} else {
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log->SC_log(Log::DEBUG) << "WR Address: @0x" << hex << adr << dec << endl;
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}
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#endif
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trans.set_response_status(tlm::TLM_OK_RESPONSE);
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}
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bool BusCtrl::instr_direct_mem_ptr(tlm::tlm_generic_payload &gp,
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tlm::tlm_dmi &dmi_data) {
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return memory_socket->get_direct_mem_ptr(gp, dmi_data);
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}
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void BusCtrl::invalidate_direct_mem_ptr(sc_dt::uint64 start,
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sc_dt::uint64 end) {
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cpu_instr_socket->invalidate_direct_mem_ptr(start, end);
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}
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