83 lines
1.8 KiB
C++
83 lines
1.8 KiB
C++
/**
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@file BusCtrl.h
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@brief Basic TLM-2 Bus controller
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@author Màrius Montón
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@date September 2018
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*/
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#ifndef __BUSCTRL_H__
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#define __BUSCTRL_H__
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#include <iostream>
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#include <fstream>
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#define SC_INCLUDE_DYNAMIC_PROCESSES
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#include "systemc"
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#include "tlm.h"
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#include "tlm_utils/simple_initiator_socket.h"
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#include "tlm_utils/simple_target_socket.h"
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#include "Log.h"
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using namespace sc_core;
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using namespace sc_dt;
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using namespace std;
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/**
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* Memory mapped Trace peripheral address
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*/
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#define TRACE_MEMORY_ADDRESS 0x40000000
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/**
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* @brief Simple bus controller
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*
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* This module manages instructon & data bus. It has 2 target ports,
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* cpu_instr_socket and cpu_data_socket that receives accesses from CPU and
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* has 2 initiator ports to access main Memory and Trace module.
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* It will be expanded with more ports when required (for DMA,
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* other peripherals, etc.)
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*/
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class BusCtrl: sc_module {
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public:
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/**
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* @brief TLM target socket CPU instruction memory bus
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*/
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tlm_utils::simple_target_socket<BusCtrl> cpu_instr_socket;
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/**
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* @brief TLM target socket CPU data memory bus
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*/
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tlm_utils::simple_target_socket<BusCtrl> cpu_data_socket;
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/**
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* @brief TLM initiator socket Main memory bus
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*/
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tlm_utils::simple_initiator_socket<BusCtrl> memory_socket;
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/**
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* @brief TLM initiator socket Trace module
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*/
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tlm_utils::simple_initiator_socket<BusCtrl> trace_socket;
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/**
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* @brief constructor
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* @param name module's name
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*/
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BusCtrl(sc_module_name name);
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/**
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* @brief TLM-2 blocking mechanism
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* @param trans transtractino to perform
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* @param delay delay associated to this transaction
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*/
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virtual void b_transport( tlm::tlm_generic_payload& trans, sc_time& delay );
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private:
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Log *log;
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};
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#endif
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