521 lines
14 KiB
C++
521 lines
14 KiB
C++
/*!
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\file A_extension.h
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\brief Implement A extensions part of the RISC-V
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\author Màrius Montón
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\date December 2018
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*/
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// SPDX-License-Identifier: GPL-3.0-or-later
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#ifndef A_EXTENSION__H
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#define A_EXTENSION__H
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#include "systemc"
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#include <unordered_set>
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#include "Registers.h"
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#include "MemoryInterface.h"
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#include "extension_base.h"
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namespace riscv_tlm {
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typedef enum {
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OP_A_LR,
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OP_A_SC,
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OP_A_AMOSWAP,
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OP_A_AMOADD,
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OP_A_AMOXOR,
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OP_A_AMOAND,
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OP_A_AMOOR,
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OP_A_AMOMIN,
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OP_A_AMOMAX,
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OP_A_AMOMINU,
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OP_A_AMOMAXU,
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OP_A_ERROR
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} op_A_Codes;
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typedef enum {
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A_LR = 0b00010,
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A_SC = 0b00011,
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A_AMOSWAP = 0b00001,
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A_AMOADD = 0b00000,
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A_AMOXOR = 0b00100,
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A_AMOAND = 0b01100,
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A_AMOOR = 0b01000,
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A_AMOMIN = 0b10000,
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A_AMOMAX = 0b10100,
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A_AMOMINU = 0b11000,
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A_AMOMAXU = 0b11100,
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} A_Codes;
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/**
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* @brief Instruction decoding and fields access
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*/
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template<typename T>
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class A_extension : public extension_base<T> {
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public:
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/**
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* @brief Constructor, same as base class
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*/
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using extension_base<T>::extension_base;
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/**
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* @brief Access to opcode field
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* @return return opcode field
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*/
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inline std::uint32_t opcode() const override {
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return static_cast<std::uint32_t>(this->m_instr.range(31, 27));
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}
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/**
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* @brief Decodes opcode of instruction
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* @return opcode of instruction
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*/
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op_A_Codes decode() const {
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switch (opcode()) {
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case A_LR:
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return OP_A_LR;
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break;
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case A_SC:
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return OP_A_SC;
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break;
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case A_AMOSWAP:
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return OP_A_AMOSWAP;
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break;
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case A_AMOADD:
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return OP_A_AMOADD;
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break;
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case A_AMOXOR:
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return OP_A_AMOXOR;
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break;
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case A_AMOAND:
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return OP_A_AMOAND;
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break;
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case A_AMOOR:
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return OP_A_AMOOR;
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break;
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case A_AMOMIN:
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return OP_A_AMOMIN;
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break;
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case A_AMOMAX:
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return OP_A_AMOMAX;
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break;
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case A_AMOMINU:
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return OP_A_AMOMINU;
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break;
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case A_AMOMAXU:
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return OP_A_AMOMAXU;
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break;
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[[unlikely]] default:
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return OP_A_ERROR;
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break;
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}
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return OP_A_ERROR;
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}
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inline void dump() const override {
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std::cout << std::hex << "0x" << this->m_instr << std::dec << std::endl;
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}
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bool Exec_A_LR() {
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std::uint32_t mem_addr = 0;
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int rd, rs1, rs2;
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std::uint32_t data;
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rd = this->get_rd();
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rs1 = this->get_rs1();
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rs2 = this->get_rs2();
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if (rs2 != 0) {
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std::cout << "ILEGAL INSTRUCTION, LR.W: rs2 != 0" << std::endl;
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this->RaiseException(EXCEPTION_CAUSE_ILLEGAL_INSTRUCTION, this->m_instr);
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return false;
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}
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mem_addr = this->regs->getValue(rs1);
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data = this->mem_intf->readDataMem(mem_addr, 4);
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this->perf->dataMemoryRead();
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this->regs->setValue(rd, static_cast<int32_t>(data));
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TLB_reserve(mem_addr);
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this->logger->debug("{} ns. PC: 0x{:x}. A.LR.W: x{:d}(0x{:x}) -> x{:d}(0x{:x}) ",
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sc_core::sc_time_stamp().value(),
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this->regs->getPC(),
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rs1, mem_addr, rd, data);
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return true;
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}
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bool Exec_A_SC() {
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std::uint32_t mem_addr;
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int rd, rs1, rs2;
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std::uint32_t data;
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rd = this->get_rd();
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rs1 = this->get_rs1();
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rs2 = this->get_rs2();
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mem_addr = this->regs->getValue(rs1);
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data = this->regs->getValue(rs2);
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if (TLB_reserved(mem_addr)) {
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this->mem_intf->writeDataMem(mem_addr, data, 4);
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this->perf->dataMemoryWrite();
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this->regs->setValue(rd, 0); // SC writes 0 to rd on success
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} else {
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this->regs->setValue(rd, 1); // SC writes nonzero on failure
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}
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this->logger->debug("{} ns. PC: 0x{:x}. A.SC.W: (0x{:x}) <- x{:d}(0x{:x}) ",
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sc_core::sc_time_stamp().value(),
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this->regs->getPC(),
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mem_addr, rs2, data);
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return true;
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}
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bool Exec_A_AMOSWAP() const {
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std::uint32_t mem_addr;
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int rd, rs1, rs2;
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std::uint32_t data;
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std::uint32_t aux;
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/* These instructions must be atomic */
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rd = this->get_rd();
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rs1 = this->get_rs1();
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rs2 = this->get_rs2();
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mem_addr = this->regs->getValue(rs1);
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data = this->mem_intf->readDataMem(mem_addr, 4);
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this->perf->dataMemoryRead();
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this->regs->setValue(rd, static_cast<int32_t>(data));
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// swap
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aux = this->regs->getValue(rs2);
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this->regs->setValue(rs2, static_cast<int32_t>(data));
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this->mem_intf->writeDataMem(mem_addr, aux, 4);
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this->perf->dataMemoryWrite();
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this->logger->debug("{} ns. PC: 0x{:x}. A.AMOSWAP");
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return true;
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}
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bool Exec_A_AMOADD() const {
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std::uint32_t mem_addr;
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int rd, rs1, rs2;
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std::uint32_t data;
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/* These instructions must be atomic */
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rd = this->get_rd();
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rs1 = this->get_rs1();
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rs2 = this->get_rs2();
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mem_addr = this->regs->getValue(rs1);
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data = this->mem_intf->readDataMem(mem_addr, 4);
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this->perf->dataMemoryRead();
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this->regs->setValue(rd, static_cast<int32_t>(data));
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// add
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data = data + this->regs->getValue(rs2);
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this->mem_intf->writeDataMem(mem_addr, data, 4);
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this->perf->dataMemoryWrite();
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this->logger->debug("{} ns. PC: 0x{:x}. A.AMOADD");
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return true;
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}
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bool Exec_A_AMOXOR() const {
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std::uint32_t mem_addr;
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int rd, rs1, rs2;
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std::uint32_t data;
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/* These instructions must be atomic */
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rd = this->get_rd();
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rs1 = this->get_rs1();
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rs2 = this->get_rs2();
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mem_addr = this->regs->getValue(rs1);
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data = this->mem_intf->readDataMem(mem_addr, 4);
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this->perf->dataMemoryRead();
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this->regs->setValue(rd, static_cast<int32_t>(data));
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// add
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data = data ^ this->regs->getValue(rs2);
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this->mem_intf->writeDataMem(mem_addr, data, 4);
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this->perf->dataMemoryWrite();
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this->logger->debug("{} ns. PC: 0x{:x}. A.AMOXOR");
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return true;
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}
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bool Exec_A_AMOAND() const {
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std::uint32_t mem_addr;
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int rd, rs1, rs2;
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std::uint32_t data;
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/* These instructions must be atomic */
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rd = this->get_rd();
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rs1 = this->get_rs1();
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rs2 = this->get_rs2();
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mem_addr = this->regs->getValue(rs1);
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data = this->mem_intf->readDataMem(mem_addr, 4);
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this->perf->dataMemoryRead();
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this->regs->setValue(rd, static_cast<int32_t>(data));
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// add
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data = data & this->regs->getValue(rs2);
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this->mem_intf->writeDataMem(mem_addr, data, 4);
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this->perf->dataMemoryWrite();
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this->logger->debug("{} ns. PC: 0x{:x}. A.AMOAND");
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return true;
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}
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bool Exec_A_AMOOR() const {
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std::uint32_t mem_addr;
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int rd, rs1, rs2;
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std::uint32_t data;
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/* These instructions must be atomic */
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rd = this->get_rd();
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rs1 = this->get_rs1();
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rs2 = this->get_rs2();
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mem_addr = this->regs->getValue(rs1);
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data = this->mem_intf->readDataMem(mem_addr, 4);
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this->perf->dataMemoryRead();
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this->regs->setValue(rd, static_cast<int32_t>(data));
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// add
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data = data | this->regs->getValue(rs2);
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this->mem_intf->writeDataMem(mem_addr, data, 4);
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this->perf->dataMemoryWrite();
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this->logger->debug("{} ns. PC: 0x{:x}. A.AMOOR");
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return true;
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}
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bool Exec_A_AMOMIN() const {
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std::uint32_t mem_addr;
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int rd, rs1, rs2;
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std::uint32_t data;
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std::uint32_t aux;
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/* These instructions must be atomic */
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rd = this->get_rd();
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rs1 = this->get_rs1();
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rs2 = this->get_rs2();
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mem_addr = this->regs->getValue(rs1);
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data = this->mem_intf->readDataMem(mem_addr, 4);
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this->perf->dataMemoryRead();
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this->regs->setValue(rd, static_cast<int32_t>(data));
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// min
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aux = this->regs->getValue(rs2);
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if ((int32_t) data < (int32_t) aux) {
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aux = data;
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}
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this->mem_intf->writeDataMem(mem_addr, aux, 4);
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this->perf->dataMemoryWrite();
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this->logger->debug("{} ns. PC: 0x{:x}. A.AMOMIN");
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return true;
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}
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bool Exec_A_AMOMAX() const {
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std::uint32_t mem_addr;
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int rd, rs1, rs2;
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std::uint32_t data;
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std::uint32_t aux;
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/* These instructions must be atomic */
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rd = this->get_rd();
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rs1 = this->get_rs1();
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rs2 = this->get_rs2();
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mem_addr = this->regs->getValue(rs1);
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data = this->mem_intf->readDataMem(mem_addr, 4);
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this->perf->dataMemoryRead();
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this->regs->setValue(rd, static_cast<int32_t>(data));
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// >
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aux = this->regs->getValue(rs2);
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if ((int32_t) data > (int32_t) aux) {
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aux = data;
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}
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this->mem_intf->writeDataMem(mem_addr, aux, 4);
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this->perf->dataMemoryWrite();
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this->logger->debug("{} ns. PC: 0x{:x}. A.AMOMAX");
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return true;
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}
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bool Exec_A_AMOMINU() const {
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std::uint32_t mem_addr;
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int rd, rs1, rs2;
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std::uint32_t data;
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std::uint32_t aux;
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/* These instructions must be atomic */
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rd = this->get_rd();
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rs1 = this->get_rs1();
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rs2 = this->get_rs2();
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mem_addr = this->regs->getValue(rs1);
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data = this->mem_intf->readDataMem(mem_addr, 4);
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this->perf->dataMemoryRead();
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this->regs->setValue(rd, static_cast<int32_t>(data));
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// min
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aux = this->regs->getValue(rs2);
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if (data < aux) {
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aux = data;
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}
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this->mem_intf->writeDataMem(mem_addr, aux, 4);
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this->perf->dataMemoryWrite();
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this->logger->debug("{} ns. PC: 0x{:x}. A.AMOMINU");
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return true;
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}
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bool Exec_A_AMOMAXU() const {
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std::uint32_t mem_addr;
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int rd, rs1, rs2;
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std::uint32_t data;
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std::uint32_t aux;
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/* These instructions must be atomic */
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rd = this->get_rd();
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rs1 = this->get_rs1();
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rs2 = this->get_rs2();
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mem_addr = this->regs->getValue(rs1);
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data = this->mem_intf->readDataMem(mem_addr, 4);
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this->perf->dataMemoryRead();
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this->regs->setValue(rd, static_cast<int32_t>(data));
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// max
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aux = this->regs->getValue(rs2);
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if (data > aux) {
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aux = data;
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}
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this->mem_intf->writeDataMem(mem_addr, aux, 4);
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this->perf->dataMemoryWrite();
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this->logger->debug("{} ns. PC: 0x{:x}. A.AMOMAXU");
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return true;
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}
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void TLB_reserve(std::uint32_t address) {
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TLB_A_Entries.insert(address);
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}
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bool TLB_reserved(std::uint32_t address) {
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if (TLB_A_Entries.count(address) == 1) {
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TLB_A_Entries.erase(address);
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return true;
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} else {
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return false;
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}
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}
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bool process_instruction(Instruction &inst) {
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bool PC_not_affected = true;
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this->setInstr(inst.getInstr());
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switch (decode()) {
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case OP_A_LR:
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Exec_A_LR();
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break;
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case OP_A_SC:
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Exec_A_SC();
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break;
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case OP_A_AMOSWAP:
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Exec_A_AMOSWAP();
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break;
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case OP_A_AMOADD:
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Exec_A_AMOADD();
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break;
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case OP_A_AMOXOR:
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Exec_A_AMOXOR();
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break;
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case OP_A_AMOAND:
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Exec_A_AMOAND();
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break;
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case OP_A_AMOOR:
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Exec_A_AMOOR();
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break;
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case OP_A_AMOMIN:
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Exec_A_AMOMIN();
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break;
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case OP_A_AMOMAX:
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Exec_A_AMOMAX();
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break;
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case OP_A_AMOMINU:
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Exec_A_AMOMINU();
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break;
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case OP_A_AMOMAXU:
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Exec_A_AMOMAXU();
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break;
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[[unlikely]] default:
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std::cout << "A instruction not implemented yet" << std::endl;
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inst.dump();
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this->NOP();
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break;
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}
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return PC_not_affected;
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}
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private:
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std::unordered_set<std::uint32_t> TLB_A_Entries;
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};
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}
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#endif
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