421 lines
13 KiB
C++
421 lines
13 KiB
C++
/*!
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\file Registers.h
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\brief Basic register file
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\author Màrius Montón
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\date August 2018
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*/
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// SPDX-License-Identifier: GPL-3.0-or-later
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#ifndef REGISTERS_H
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#define REGISTERS_H
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#define SC_INCLUDE_DYNAMIC_PROCESSES
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#include <iomanip>
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#include <unordered_map>
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#include "systemc"
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#include "tlm.h"
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#include "Performance.h"
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#include "Memory.h"
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namespace riscv_tlm {
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#define MISA_A_EXTENSION (1 << 0)
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#define MISA_B_EXTENSION (1 << 1)
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#define MISA_C_EXTENSION (1 << 2)
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#define MISA_I_BASE (1 << 8)
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#define MISA_M_EXTENSION (1 << 12)
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#define MISA_MXL (1 << 30)
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#define CSR_MVENDORID (0xF11)
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#define CSR_MARCHID (0xF12)
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#define CSR_MIMPID (0xF13)
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#define CSR_MHARTID (0xF14)
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#define CSR_MSTATUS (0x300)
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#define CSR_MISA (0x301)
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#define CSR_MEDELEG (0x302)
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#define CSR_MIDELEG (0x303)
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#define CSR_MIE (0x304)
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#define CSR_MTVEC (0x305)
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#define CSR_MCOUNTEREN (0x306)
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#define CSR_MSTATUSH (0x310)
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#define CSR_MSCRATCH (0x340)
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#define CSR_MEPC (0x341)
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#define CSR_MCAUSE (0x342)
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#define CSR_MTVAL (0x343)
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#define CSR_MIP (0x344)
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#define CSR_SSCRATCH (0x140)
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#define CSR_SEPC (0x141)
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#define CSR_SCAUSE (0x142)
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#define CSR_STVAL (0x143)
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#define CSR_SIP (0x144)
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#define CSR_MCYCLE (0xB00)
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#define CSR_MINSTRET (0xB02)
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#define CSR_MCYCLEH (0xB80)
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#define CSR_MINSTRETH (0xB82)
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#define CSR_CYCLE (0xC00)
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#define CSR_TIME (0xC01)
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#define CSR_INSTRET (0xC02)
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#define CSR_CYCLEH (0xC80)
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#define CSR_TIMEH (0xC81)
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#define CSR_INSTRETH (0xC02)
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#define CSR_STVEC (0x105)
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#define MSTATUS_UIE (1 << 0)
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#define MSTATUS_SIE (1 << 1)
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#define MSTATUS_MIE (1 << 3)
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#define MSTATUS_UPIE (1 << 4)
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#define MSTATUS_SPIE (1 << 5)
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#define MSTATUS_MPIE (1 << 7)
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#define MSTATUS_SPP (1 << 8)
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#define MSTATUS_MPP (1 << 11)
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#define MSTATUS_FS (1 << 13)
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#define MSTATUS_XS (1 << 15)
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#define MSTATUS_MPRV (1 << 17)
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#define MSTATUS_SUM (1 << 18)
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#define MSTATUS_MXR (1 << 19)
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#define MSTATUS_TVM (1 << 20)
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#define MSTATUS_TW (1 << 21)
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#define MSTATUS_TSR (1 << 22)
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#define MIP_USIP (1 << 0)
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#define MIP_SSIP (1 << 1)
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#define MIP_MSIP (1 << 3)
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#define MIP_UTIP (1 << 4)
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#define MIP_STIP (1 << 5)
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#define MIP_MTIP (1 << 7)
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#define MIP_UEIP (1 << 8)
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#define MIP_SEIP (1 << 9)
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#define MIP_MEIP (1 << 11)
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#define MIE_USIE (1 << 0)
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#define MIE_SSIE (1 << 1)
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#define MIE_MSIE (1 << 3)
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#define MIE_UTIE (1 << 4)
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#define MIE_STIE (1 << 5)
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#define MIE_MTIE (1 << 7)
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#define MIE_UEIE (1 << 8)
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#define MIE_SEIE (1 << 9)
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#define MIE_MEIE (1 << 11)
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/* 1 ns tick in CYCLE & TIME counters */
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#define TICKS_PER_SECOND (1000000)
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/**
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* @brief Register file implementation
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*/
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template<typename T>
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class Registers {
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public:
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enum {
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x0 = 0,
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x1 = 1,
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x2,
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x3,
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x4,
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x5,
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x6,
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x7,
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x8,
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x9,
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x10,
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x11,
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x12,
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x13,
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x14,
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x15,
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x16,
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x17,
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x18,
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x19,
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x20,
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x21,
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x22,
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x23,
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x24,
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x25,
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x26,
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x27,
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x28,
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x29,
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x30,
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x31,
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zero = x0,
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ra = x1,
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sp = x2,
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gp = x3,
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tp = x4,
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t0 = x5,
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t1 = x6,
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t2 = x7,
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s0 = x8,
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fp = x8,
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s1 = x9,
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a0 = x10,
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a1 = x11,
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a2 = x12,
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a3 = x13,
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a4 = x14,
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a5 = x15,
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a6 = x16,
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a7 = x17,
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s2 = x18,
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s3 = x19,
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s4 = x20,
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s5 = x21,
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s6 = x22,
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s7 = x23,
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s8 = x24,
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s9 = x25,
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s10 = x26,
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s11 = x27,
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t3 = x28,
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t4 = x29,
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t5 = x30,
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t6 = x31
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};
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/**
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* Default constructor
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*/
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Registers() {
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perf = Performance::getInstance();
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initCSR();
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register_bank[sp] = Memory::SIZE - 4; // default stack at the end of the memory
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register_PC = 0x80000000; // default _start address
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};
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/**
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* Set value for a register
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* @param reg_num register number
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* @param value register value
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*/
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void setValue(unsigned int reg_num, T value) {
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if ((reg_num != 0) && (reg_num < 32)) {
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register_bank[reg_num] = value;
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perf->registerWrite();
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}
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}
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/**
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* Returns register value
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* @param reg_num register number
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* @return register value
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*/
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T getValue(unsigned int reg_num) const {
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if (reg_num < 32) {
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perf->registerRead();
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return register_bank[reg_num];
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} else {
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/* Extend sign for any possible T type */
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return static_cast<T>(std::numeric_limits<T>::max());
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}
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}
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/**
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* Returns PC value
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* @return PC value
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*/
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T getPC() const {
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return register_PC;
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}
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/**
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* Sets arbitraty value to PC
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* @param new_pc new address to PC
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*/
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void setPC(T new_pc) {
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register_PC = new_pc;
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}
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/**
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* Increments PC couunter to next address
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*/
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inline void incPC() {
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register_PC += 4;
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}
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inline void incPCby2() {
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register_PC += 2;
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}
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/**
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* @brief Get CSR value
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* @param csr CSR number to access
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* @return CSR value
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*/
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T getCSR(int csr) {
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T ret_value;
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switch (csr) {
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case CSR_CYCLE:
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case CSR_MCYCLE:
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ret_value = static_cast<std::uint64_t>(sc_core::sc_time(
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sc_core::sc_time_stamp()
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- sc_core::sc_time(sc_core::SC_ZERO_TIME)).to_double())
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& 0x00000000FFFFFFFF;
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break;
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case CSR_CYCLEH:
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case CSR_MCYCLEH:
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ret_value = static_cast<std::uint32_t>((std::uint64_t) (sc_core::sc_time(
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sc_core::sc_time_stamp()
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- sc_core::sc_time(sc_core::SC_ZERO_TIME)).to_double())
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>> 32 & 0x00000000FFFFFFFF);
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break;
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case CSR_TIME:
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ret_value = static_cast<std::uint64_t>(sc_core::sc_time(
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sc_core::sc_time_stamp()
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- sc_core::sc_time(sc_core::SC_ZERO_TIME)).to_double())
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& 0x00000000FFFFFFFF;
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break;
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case CSR_TIMEH:
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ret_value = static_cast<std::uint32_t>((std::uint64_t) (sc_core::sc_time(
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sc_core::sc_time_stamp()
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- sc_core::sc_time(sc_core::SC_ZERO_TIME)).to_double())
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>> 32 & 0x00000000FFFFFFFF);
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break;
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[[likely]] default:
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ret_value = CSR[csr];
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break;
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}
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return ret_value;
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}
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/**
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* @brief Set CSR value
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* @param csr CSR number to access
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* @param value new value to register
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*/
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void setCSR(int csr, T value) {
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/* @FIXME: rv32mi-p-ma_fetch tests doesn't allow MISA to be writable,
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* but Volume II: Privileged Architecture v1.10 says MISA is writable (?)
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*/
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if (csr != CSR_MISA) {
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CSR[csr] = value;
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}
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}
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/**
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* Dump register data to console
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*/
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void dump() {
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std::cout << "************************************" << std::endl;
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std::cout << "Registers dump" << std::dec << std::endl;
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std::cout << std::setfill('0') << std::uppercase;
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std::cout << "x0 (zero): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[0];
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std::cout << " x1 (ra): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[1];
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std::cout << " x2 (sp): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[2];
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std::cout << " x3 (gp): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[3] << std::endl;
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std::cout << "x4 (tp): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[4];
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std::cout << " x5 (t0): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[5];
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std::cout << " x6 (t1): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[6];
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std::cout << " x7 (t2): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[7] << std::endl;
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std::cout << "x8 (s0/fp): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[8];
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std::cout << " x9 (s1): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[9];
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std::cout << " x10 (a0): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[10];
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std::cout << " x11 (a1): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[11] << std::endl;
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std::cout << "x12 (a2): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[12];
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std::cout << " x13 (a3): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[13];
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std::cout << " x14 (a4): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[14];
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std::cout << " x15 (a5): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[15] << std::endl;
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std::cout << "x16 (a6): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[16];
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std::cout << " x17 (a7): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[17];
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std::cout << " x18 (s2): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[18];
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std::cout << " x19 (s3): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[19] << std::endl;
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std::cout << "x20 (s4): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[20];
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std::cout << " x21 (s5): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[21];
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std::cout << " x22 (s6): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[22];
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std::cout << " x23 (s7): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[23] << std::endl;
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std::cout << "x24 (s8): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[24];
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std::cout << " x25 (s9): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[25];
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std::cout << " x26 (s10): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[26];
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std::cout << " x27 (s11): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[27] << std::endl;
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std::cout << "x28 (t3): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[28];
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std::cout << " x29 (t4): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[29];
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std::cout << " x30 (t5): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[30];
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std::cout << " x31 (t6): 0x" << std::right << std::setw(8)
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<< std::hex << register_bank[31] << std::endl;
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std::cout << "PC: 0x" << std::setw(8) << std::hex << register_PC << std::dec << std::endl;
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std::cout << "************************************" << std::endl;
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}
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private:
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/**
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* bank of registers (32 regs of 32bits each)
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*/
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std::array<T, 32> register_bank = {{0}};
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/**
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* Program counter (32 bits width)
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*/
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T register_PC;
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/**
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* CSR registers (4096 maximum)
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*/
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std::unordered_map<T, unsigned int> CSR;
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Performance *perf;
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void initCSR();
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/*
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void initCSR() {
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CSR[CSR_MISA] = MISA_MXL | MISA_M_EXTENSION | MISA_C_EXTENSION
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| MISA_A_EXTENSION | MISA_I_BASE;
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CSR[CSR_MSTATUS] = MISA_MXL;
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}
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*/
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};
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}
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#endif
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