
set_property -dict { PACKAGE_PIN P30 IOSTANDARD LVCMOS18 } [get_ports { o_led0 }];

set_property -dict { PACKAGE_PIN M30 IOSTANDARD LVCMOS18 } [get_ports { o_led_blink }];


set_property -dict { PACKAGE_PIN Y26  IOSTANDARD LVCMOS33  PULLUP true } [get_ports i_pcie_rstn]


set_property PACKAGE_PIN J8  [get_ports { i_pcie_refclkp }];
create_clock -name sys_clk -period 10 [get_ports i_pcie_refclkp]


# set_property PACKAGE_PIN F2   [get_ports { o_pcie_txp[0] }];
# #set_property PACKAGE_PIN AA2  [get_ports { o_pcie_txp[1] }];
# #set_property PACKAGE_PIN AC2  [get_ports { o_pcie_txp[2] }];
# #set_property PACKAGE_PIN AE2  [get_ports { o_pcie_txp[3] }];
# #set_property PACKAGE_PIN AG2  [get_ports { o_pcie_txp[4] }];
# #set_property PACKAGE_PIN AH4  [get_ports { o_pcie_txp[5] }];
# #set_property PACKAGE_PIN AJ2  [get_ports { o_pcie_txp[6] }];
# #set_property PACKAGE_PIN AK4  [get_ports { o_pcie_txp[7] }];

# set_property PACKAGE_PIN H6   [get_ports { i_pcie_rxp[0] }];
# #set_property PACKAGE_PIN AA6  [get_ports { i_pcie_rxp[1] }];
# #set_property PACKAGE_PIN AB4  [get_ports { i_pcie_rxp[2] }];
# #set_property PACKAGE_PIN AC6  [get_ports { i_pcie_rxp[3] }];
# #set_property PACKAGE_PIN AD4  [get_ports { i_pcie_rxp[4] }];
# #set_property PACKAGE_PIN AE6  [get_ports { i_pcie_rxp[5] }];
# #set_property PACKAGE_PIN AF4  [get_ports { i_pcie_rxp[6] }];
# #set_property PACKAGE_PIN AG6  [get_ports { i_pcie_rxp[7] }];


set_property PACKAGE_PIN F2   [get_ports { o_pcie_txp[0] }];
set_property PACKAGE_PIN H2   [get_ports { o_pcie_txp[1] }];
set_property PACKAGE_PIN K2   [get_ports { o_pcie_txp[2] }];
set_property PACKAGE_PIN M2   [get_ports { o_pcie_txp[3] }];
set_property PACKAGE_PIN N4   [get_ports { o_pcie_txp[4] }];
set_property PACKAGE_PIN P2   [get_ports { o_pcie_txp[5] }];
set_property PACKAGE_PIN T2   [get_ports { o_pcie_txp[6] }];
set_property PACKAGE_PIN U4   [get_ports { o_pcie_txp[7] }];


set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]





# set_property PACKAGE_PIN J8 [get_ports {PCIe_CLK_clk_p[0]}]
# set_property LOC GTXE2_CHANNEL_X0Y23 [get_cells {Top_i/xdma_0/inst/Top_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[0].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
# set_property PACKAGE_PIN F2 [get_ports {pcie_7x_mgt_txp[0]}]
# set_property LOC GTXE2_CHANNEL_X0Y22 [get_cells {Top_i/xdma_0/inst/Top_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[1].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
# set_property PACKAGE_PIN H2 [get_ports {pcie_7x_mgt_txp[1]}]
# set_property LOC GTXE2_CHANNEL_X0Y21 [get_cells {Top_i/xdma_0/inst/Top_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[2].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
# set_property PACKAGE_PIN K2 [get_ports {pcie_7x_mgt_txp[2]}]
# set_property LOC GTXE2_CHANNEL_X0Y20 [get_cells {Top_i/xdma_0/inst/Top_xdma_0_0_pcie2_to_pcie3_wrapper_i/pcie2_ip_i/inst/inst/gt_top_i/pipe_wrapper_i/pipe_lane[3].gt_wrapper_i/gtx_channel.gtxe2_channel_i}]
# set_property PACKAGE_PIN M2 [get_ports {pcie_7x_mgt_txp[3]}]

# # set_property IOSTANDARD LVCMOS33 [get_ports PCIe_RST_n]
# # set_property PACKAGE_PIN Y26 [get_ports PCIe_RST_n]
# # set_property PULLUP true [get_ports PCIe_RST_n]

# set_property PACKAGE_PIN N30 [get_ports {LED[2]}]
# set_property PACKAGE_PIN M30 [get_ports {LED[1]}]
# set_property PACKAGE_PIN P30 [get_ports {LED[0]}]
# set_property IOSTANDARD LVCMOS18 [get_ports {LED[2]}]
# set_property IOSTANDARD LVCMOS18 [get_ports {LED[1]}]
# set_property IOSTANDARD LVCMOS18 [get_ports {LED[0]}]

# set_property PACKAGE_PIN AA28 [get_ports clk_50]
# set_property IOSTANDARD LVCMOS33 [get_ports clk_50]


# set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
# set_property BITSTREAM.CONFIG.CONFIGRATE 12 [current_design]
# set_property BITSTREAM.CONFIG.USERID 32'h12345678 [current_design]
# set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]

# #set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
# #set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
# #set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
# #connect_debug_port dbg_hub/clk [get_nets clk_50_IBUF_BUFG]


# set_property C_CLK_INPUT_FREQ_HZ 300000000 [get_debug_cores dbg_hub]
# set_property C_ENABLE_CLK_DIVIDER false [get_debug_cores dbg_hub]
# set_property C_USER_SCAN_CHAIN 1 [get_debug_cores dbg_hub]
# connect_debug_port dbg_hub/clk [get_nets clk_50_IBUF_BUFG]

