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            "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
            "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
          },
          "port_maps": {
            "CLK": [ { "physical_name": "s_axi_aclk" } ]
          }
        }
      },
      "memory_maps": {
        "S_AXI": {
          "display_name": "S_AXI_MEM",
          "description": "Memory Map for S_AXI",
          "address_blocks": {
            "Mem0": {
              "base_address": "0",
              "range": "4096",
              "display_name": "Mem0",
              "description": "Register Block",
              "usage": "memory",
              "access": "read-write"
            }
          }
        }
      }
    }
  }
}