Copyright 1986-2022 Xilinx, Inc. All Rights Reserved.
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022
| Date         : Thu May  1 00:22:12 2025
| Host         : colin-9700k running 64-bit Ubuntu 22.04.5 LTS
| Command      : upgrade_ip
| Device       : xc7k480tffg1156-2L
------------------------------------------------------------------------------------

Upgrade Log for IP 'xdma_0'

1. Summary
----------

CAUTION (success, with warnings) in the upgrade of xdma_0 (xilinx.com:ip:xdma:4.1) from (Rev. 3) to (Rev. 20)

After upgrade, an IP may have parameter differences compared to the original customization. Please review the parameters within the IP customization GUI to ensure proper functionality.

2. Upgrade messages
-------------------

Failed to execute command 'namespace eval ::ipgen_xdma_v4_1_utils {::xcoUpgradeLib::upgradeXCI xdma_v4_1 xdma_v4_1 ::ipgen_xdma_v4_1_utils ::xcoUpgradeLib::xciArray}' :
	expected boolean value but got "WARNING: upgrade cannot get value of parameter bro"
WARNING: upgrade cannot get value of parameter broadcom_sbr_wa : there is no parameter called broadcom_sbr_wa in xdma_v4_1

3. Customization warnings
-------------------------

The normal upgrade process failed due to validation failures in the given configuration. Attempting partial upgrade to set as many user parameters as possible. Please check the parameters whose values were not applied.

An attempt to modify the value of disabled parameter 'pf1_msix_cap_table_size' from '000' to '020' has been ignored for IP 'xdma_0'

An attempt to modify the value of disabled parameter 'pf1_msix_cap_table_offset' from '00000000' to '00009000' has been ignored for IP 'xdma_0'

An attempt to modify the value of disabled parameter 'pf1_msix_cap_pba_offset' from '00000000' to '00009FE0' has been ignored for IP 'xdma_0'

Unable to set the value 'X0Y1' on parameter 'Pcie Blk Locn' due to the following failure - 
Value 'X0Y1' is out of the range for parameter 'Pcie Blk Locn(pcie_blk_locn)' for IP 'xdma_0' . Valid values are - X0Y0
. Restoring to an old valid value of 'X0Y0'

An attempt to modify the value of disabled parameter 'PF3_SRIOV_VF_DEVICE_ID' from 'A331' to '0000' has been ignored for IP 'xdma_0'

An attempt to modify the value of disabled parameter 'PF2_SRIOV_VF_DEVICE_ID' from 'A231' to '0000' has been ignored for IP 'xdma_0'

An attempt to modify the value of disabled parameter 'PF1_SRIOV_VF_DEVICE_ID' from 'A131' to '0000' has been ignored for IP 'xdma_0'


4. Debug Commands
-----------------

  The following debug information can be passed to Vivado as Tcl commands,
in order to validate or debug the output of the upgrade flow.
  You may consult any warnings from within this upgrade, and alter or remove
the configuration parameter(s) which caused the warning; then execute the Tcl
commands, and use the IP Customization GUI to verify the IP configuration.

create_ip -vlnv xilinx.com:ip:xdma:4.1 -user_name xdma_0
set_property -dict "\
  CONFIG.BASEADDR {0x00001000} \
  CONFIG.CLK.SYS_CLK.ASSOCIATED_BUSIF {} \
  CONFIG.CLK.SYS_CLK.ASSOCIATED_RESET {} \
  CONFIG.CLK.SYS_CLK.CLK_DOMAIN {} \
  CONFIG.CLK.SYS_CLK.FREQ_HZ {100000000} \
  CONFIG.CLK.SYS_CLK.INSERT_VIP {0} \
  CONFIG.CLK.SYS_CLK.PHASE {0.000} \
  CONFIG.CLK.axi_aclk.ASSOCIATED_BUSIF {M_AXI:S_AXI_B:M_AXI_LITE:S_AXI_LITE:M_AXI_BYPASS:M_AXI_B:S_AXIS_C2H_0:S_AXIS_C2H_1:S_AXIS_C2H_2:S_AXIS_C2H_3:M_AXIS_H2C_0:M_AXIS_H2C_1:M_AXIS_H2C_2:M_AXIS_H2C_3:sc0_ats_m_axis_cq:sc0_ats_m_axis_rc:sc0_ats_s_axis_cc:sc0_ats_s_axis_rq:sc1_ats_m_axis_cq:sc1_ats_m_axis_rc:sc1_ats_s_axis_cc:sc1_ats_s_axis_rq:cxs_tx:cxs_rx} \
  CONFIG.CLK.axi_aclk.ASSOCIATED_RESET {axi_aresetn} \
  CONFIG.CLK.axi_aclk.CLK_DOMAIN {} \
  CONFIG.CLK.axi_aclk.FREQ_HZ {125000000} \
  CONFIG.CLK.axi_aclk.INSERT_VIP {0} \
  CONFIG.CLK.axi_aclk.PHASE {0.000} \
  CONFIG.Component_Name {xdma_0} \
  CONFIG.HIGHADDR {0x00001FFF} \
  CONFIG.INS_LOSS_NYQ {15} \
  CONFIG.MSI_X_OPTIONS {None} \
  CONFIG.M_AXI.ADDR_WIDTH {64} \
  CONFIG.M_AXI.ARUSER_WIDTH {0} \
  CONFIG.M_AXI.AWUSER_WIDTH {0} \
  CONFIG.M_AXI.BUSER_WIDTH {0} \
  CONFIG.M_AXI.CLK_DOMAIN {} \
  CONFIG.M_AXI.DATA_WIDTH {64} \
  CONFIG.M_AXI.FREQ_HZ {100000000} \
  CONFIG.M_AXI.HAS_BRESP {1} \
  CONFIG.M_AXI.HAS_BURST {0} \
  CONFIG.M_AXI.HAS_BURST.VALUE_SRC {CONSTANT} \
  CONFIG.M_AXI.HAS_CACHE {1} \
  CONFIG.M_AXI.HAS_LOCK {1} \
  CONFIG.M_AXI.HAS_PROT {1} \
  CONFIG.M_AXI.HAS_QOS {0} \
  CONFIG.M_AXI.HAS_REGION {0} \
  CONFIG.M_AXI.HAS_RRESP {1} \
  CONFIG.M_AXI.HAS_WSTRB {1} \
  CONFIG.M_AXI.ID_WIDTH {4} \
  CONFIG.M_AXI.INSERT_VIP {0} \
  CONFIG.M_AXI.MAX_BURST_LENGTH {256} \
  CONFIG.M_AXI.NUM_READ_OUTSTANDING {2} \
  CONFIG.M_AXI.NUM_READ_THREADS {1} \
  CONFIG.M_AXI.NUM_WRITE_OUTSTANDING {2} \
  CONFIG.M_AXI.NUM_WRITE_THREADS {1} \
  CONFIG.M_AXI.PHASE {0.000} \
  CONFIG.M_AXI.PROTOCOL {AXI4} \
  CONFIG.M_AXI.READ_WRITE_MODE {READ_WRITE} \
  CONFIG.M_AXI.RUSER_BITS_PER_BYTE {0} \
  CONFIG.M_AXI.RUSER_WIDTH {0} \
  CONFIG.M_AXI.SUPPORTS_NARROW_BURST {0} \
  CONFIG.M_AXI.WUSER_BITS_PER_BYTE {0} \
  CONFIG.M_AXI.WUSER_WIDTH {0} \
  CONFIG.M_AXI_BYPASS.ADDR_WIDTH {64} \
  CONFIG.M_AXI_BYPASS.ARUSER_WIDTH {0} \
  CONFIG.M_AXI_BYPASS.AWUSER_WIDTH {0} \
  CONFIG.M_AXI_BYPASS.BUSER_WIDTH {0} \
  CONFIG.M_AXI_BYPASS.CLK_DOMAIN {} \
  CONFIG.M_AXI_BYPASS.DATA_WIDTH {64} \
  CONFIG.M_AXI_BYPASS.FREQ_HZ {100000000} \
  CONFIG.M_AXI_BYPASS.HAS_BRESP {1} \
  CONFIG.M_AXI_BYPASS.HAS_BURST {1} \
  CONFIG.M_AXI_BYPASS.HAS_CACHE {1} \
  CONFIG.M_AXI_BYPASS.HAS_LOCK {1} \
  CONFIG.M_AXI_BYPASS.HAS_PROT {1} \
  CONFIG.M_AXI_BYPASS.HAS_QOS {0} \
  CONFIG.M_AXI_BYPASS.HAS_REGION {0} \
  CONFIG.M_AXI_BYPASS.HAS_RRESP {1} \
  CONFIG.M_AXI_BYPASS.HAS_WSTRB {1} \
  CONFIG.M_AXI_BYPASS.ID_WIDTH {4} \
  CONFIG.M_AXI_BYPASS.INSERT_VIP {0} \
  CONFIG.M_AXI_BYPASS.MAX_BURST_LENGTH {256} \
  CONFIG.M_AXI_BYPASS.NUM_READ_OUTSTANDING {8} \
  CONFIG.M_AXI_BYPASS.NUM_READ_THREADS {2} \
  CONFIG.M_AXI_BYPASS.NUM_WRITE_OUTSTANDING {8} \
  CONFIG.M_AXI_BYPASS.NUM_WRITE_THREADS {2} \
  CONFIG.M_AXI_BYPASS.PHASE {0.000} \
  CONFIG.M_AXI_BYPASS.PROTOCOL {AXI4} \
  CONFIG.M_AXI_BYPASS.READ_WRITE_MODE {READ_WRITE} \
  CONFIG.M_AXI_BYPASS.RUSER_BITS_PER_BYTE {0} \
  CONFIG.M_AXI_BYPASS.RUSER_WIDTH {0} \
  CONFIG.M_AXI_BYPASS.SUPPORTS_NARROW_BURST {0} \
  CONFIG.M_AXI_BYPASS.WUSER_BITS_PER_BYTE {0} \
  CONFIG.M_AXI_BYPASS.WUSER_WIDTH {0} \
  CONFIG.PCIE_BOARD_INTERFACE {Custom} \
  CONFIG.PF0_DEVICE_ID_mqdma {9021} \
  CONFIG.PF0_MSIX_CAP_PBA_BIR_mqdma {BAR_0} \
  CONFIG.PF0_MSIX_CAP_PBA_OFFSET_mqdma {00000000} \
  CONFIG.PF0_MSIX_CAP_TABLE_BIR_mqdma {BAR_0} \
  CONFIG.PF0_MSIX_CAP_TABLE_OFFSET_mqdma {00000000} \
  CONFIG.PF0_MSIX_CAP_TABLE_SIZE_mqdma {000} \
  CONFIG.PF0_REVISION_ID_mqdma {00} \
  CONFIG.PF0_SRIOV_CAP_INITIAL_VF {0} \
  CONFIG.PF0_SRIOV_FIRST_VF_OFFSET {0} \
  CONFIG.PF0_SRIOV_FUNC_DEP_LINK {0000} \
  CONFIG.PF0_SRIOV_SUPPORTED_PAGE_SIZE {00000553} \
  CONFIG.PF0_SRIOV_VF_DEVICE_ID {0000} \
  CONFIG.PF0_SUBSYSTEM_ID_mqdma {0007} \
  CONFIG.PF0_SUBSYSTEM_VENDOR_ID_mqdma {10EE} \
  CONFIG.PF1_DEVICE_ID_mqdma {0007} \
  CONFIG.PF1_INTERRUPT_PIN {NONE} \
  CONFIG.PF1_MSIX_CAP_PBA_BIR_mqdma {BAR_0} \
  CONFIG.PF1_MSIX_CAP_PBA_OFFSET_mqdma {00000000} \
  CONFIG.PF1_MSIX_CAP_TABLE_BIR_mqdma {BAR_0} \
  CONFIG.PF1_MSIX_CAP_TABLE_OFFSET_mqdma {00000000} \
  CONFIG.PF1_MSIX_CAP_TABLE_SIZE_mqdma {000} \
  CONFIG.PF1_MSI_CAP_MULTIMSGCAP {1_vector} \
  CONFIG.PF1_REVISION_ID {00} \
  CONFIG.PF1_REVISION_ID_mqdma {00} \
  CONFIG.PF1_SRIOV_CAP_INITIAL_VF {0} \
  CONFIG.PF1_SRIOV_CAP_VER {1} \
  CONFIG.PF1_SRIOV_FIRST_VF_OFFSET {0} \
  CONFIG.PF1_SRIOV_FUNC_DEP_LINK {0001} \
  CONFIG.PF1_SRIOV_SUPPORTED_PAGE_SIZE {00000553} \
  CONFIG.PF1_SRIOV_VF_DEVICE_ID {0000} \
  CONFIG.PF1_SUBSYSTEM_ID {0007} \
  CONFIG.PF1_SUBSYSTEM_ID_mqdma {0007} \
  CONFIG.PF1_SUBSYSTEM_VENDOR_ID {10EE} \
  CONFIG.PF1_SUBSYSTEM_VENDOR_ID_mqdma {10EE} \
  CONFIG.PF1_Use_Class_Code_Lookup_Assistant {false} \
  CONFIG.PF2_DEVICE_ID_mqdma {9021} \
  CONFIG.PF2_INTERRUPT_PIN {NONE} \
  CONFIG.PF2_MSIX_CAP_PBA_BIR_mqdma {BAR_0} \
  CONFIG.PF2_MSIX_CAP_PBA_OFFSET_mqdma {00000000} \
  CONFIG.PF2_MSIX_CAP_TABLE_BIR_mqdma {BAR_0} \
  CONFIG.PF2_MSIX_CAP_TABLE_OFFSET_mqdma {00000000} \
  CONFIG.PF2_MSIX_CAP_TABLE_SIZE_mqdma {000} \
  CONFIG.PF2_MSI_CAP_MULTIMSGCAP {1_vector} \
  CONFIG.PF2_REVISION_ID {00} \
  CONFIG.PF2_REVISION_ID_mqdma {00} \
  CONFIG.PF2_SRIOV_CAP_INITIAL_VF {0} \
  CONFIG.PF2_SRIOV_CAP_VER {1} \
  CONFIG.PF2_SRIOV_FIRST_VF_OFFSET {0} \
  CONFIG.PF2_SRIOV_FUNC_DEP_LINK {0002} \
  CONFIG.PF2_SRIOV_SUPPORTED_PAGE_SIZE {00000553} \
  CONFIG.PF2_SRIOV_VF_DEVICE_ID {0000} \
  CONFIG.PF2_SUBSYSTEM_ID {0007} \
  CONFIG.PF2_SUBSYSTEM_ID_mqdma {0007} \
  CONFIG.PF2_SUBSYSTEM_VENDOR_ID {10EE} \
  CONFIG.PF2_SUBSYSTEM_VENDOR_ID_mqdma {10EE} \
  CONFIG.PF2_Use_Class_Code_Lookup_Assistant {false} \
  CONFIG.PF3_DEVICE_ID_mqdma {9021} \
  CONFIG.PF3_INTERRUPT_PIN {NONE} \
  CONFIG.PF3_MSIX_CAP_PBA_BIR_mqdma {BAR_0} \
  CONFIG.PF3_MSIX_CAP_PBA_OFFSET_mqdma {00000000} \
  CONFIG.PF3_MSIX_CAP_TABLE_BIR_mqdma {BAR_0} \
  CONFIG.PF3_MSIX_CAP_TABLE_OFFSET_mqdma {00000000} \
  CONFIG.PF3_MSIX_CAP_TABLE_SIZE_mqdma {000} \
  CONFIG.PF3_MSI_CAP_MULTIMSGCAP {1_vector} \
  CONFIG.PF3_REVISION_ID {00} \
  CONFIG.PF3_REVISION_ID_mqdma {00} \
  CONFIG.PF3_SRIOV_CAP_INITIAL_VF {0} \
  CONFIG.PF3_SRIOV_CAP_VER {1} \
  CONFIG.PF3_SRIOV_FIRST_VF_OFFSET {0} \
  CONFIG.PF3_SRIOV_FUNC_DEP_LINK {0003} \
  CONFIG.PF3_SRIOV_SUPPORTED_PAGE_SIZE {00000553} \
  CONFIG.PF3_SRIOV_VF_DEVICE_ID {0000} \
  CONFIG.PF3_SUBSYSTEM_ID {0007} \
  CONFIG.PF3_SUBSYSTEM_ID_mqdma {0007} \
  CONFIG.PF3_SUBSYSTEM_VENDOR_ID {10EE} \
  CONFIG.PF3_SUBSYSTEM_VENDOR_ID_mqdma {10EE} \
  CONFIG.PF3_Use_Class_Code_Lookup_Assistant {false} \
  CONFIG.PHY_LP_TXPRESET {4} \
  CONFIG.RST.axi_aresetn.INSERT_VIP {0} \
  CONFIG.RST.axi_aresetn.POLARITY {ACTIVE_LOW} \
  CONFIG.RST.sys_rst_n.BOARD.ASSOCIATED_PARAM {SYS_RST_N_BOARD_INTERFACE} \
  CONFIG.RST.sys_rst_n.INSERT_VIP {0} \
  CONFIG.RST.sys_rst_n.POLARITY {ACTIVE_LOW} \
  CONFIG.RST.sys_rst_n.TYPE {PCIE_PERST} \
  CONFIG.RST.user_reset.INSERT_VIP {0} \
  CONFIG.RST.user_reset.POLARITY {ACTIVE_HIGH} \
  CONFIG.RX_PPM_OFFSET {0} \
  CONFIG.RX_SSC_PPM {0} \
  CONFIG.SRIOV_CAP_ENABLE {false} \
  CONFIG.SRIOV_FIRST_VF_OFFSET {1} \
  CONFIG.SYS_RST_N_BOARD_INTERFACE {Custom} \
  CONFIG.Shared_Logic {1} \
  CONFIG.Shared_Logic_Both {false} \
  CONFIG.Shared_Logic_Both_7xG2 {false} \
  CONFIG.Shared_Logic_Clk {false} \
  CONFIG.Shared_Logic_Clk_7xG2 {false} \
  CONFIG.Shared_Logic_Gtc {false} \
  CONFIG.Shared_Logic_Gtc_7xG2 {false} \
  CONFIG.acs_ext_cap_enable {false} \
  CONFIG.aspm_support {No_ASPM} \
  CONFIG.axi_aclk_loopback {false} \
  CONFIG.axi_addr_width {64} \
  CONFIG.axi_bypass_64bit_en {false} \
  CONFIG.axi_bypass_prefetchable {false} \
  CONFIG.axi_data_width {64_bit} \
  CONFIG.axi_id_width {4} \
  CONFIG.axi_vip_in_exdes {false} \
  CONFIG.axibar2pciebar_0 {0x0000000000000000} \
  CONFIG.axibar2pciebar_1 {0x0000000000000000} \
  CONFIG.axibar2pciebar_2 {0x0000000000000000} \
  CONFIG.axibar2pciebar_3 {0x0000000000000000} \
  CONFIG.axibar2pciebar_4 {0x0000000000000000} \
  CONFIG.axibar2pciebar_5 {0x0000000000000000} \
  CONFIG.axibar_0 {0x0000000000000000} \
  CONFIG.axibar_1 {0x0000000000000000} \
  CONFIG.axibar_2 {0x0000000000000000} \
  CONFIG.axibar_3 {0x0000000000000000} \
  CONFIG.axibar_4 {0x0000000000000000} \
  CONFIG.axibar_5 {0x0000000000000000} \
  CONFIG.axibar_highaddr_0 {0x0000000000000000} \
  CONFIG.axibar_highaddr_1 {0x0000000000000000} \
  CONFIG.axibar_highaddr_2 {0x0000000000000000} \
  CONFIG.axibar_highaddr_3 {0x0000000000000000} \
  CONFIG.axibar_highaddr_4 {0x0000000000000000} \
  CONFIG.axibar_highaddr_5 {0x0000000000000000} \
  CONFIG.axibar_num {1} \
  CONFIG.axil_master_64bit_en {false} \
  CONFIG.axil_master_prefetchable {false} \
  CONFIG.axilite_master_en {false} \
  CONFIG.axilite_master_scale {Megabytes} \
  CONFIG.axilite_master_size {1} \
  CONFIG.axis_pipe_line_stage {0} \
  CONFIG.axist_bypass_en {true} \
  CONFIG.axist_bypass_scale {Megabytes} \
  CONFIG.axist_bypass_size {1} \
  CONFIG.axisten_freq {62.5} \
  CONFIG.axisten_if_enable_msg_route {27FFF} \
  CONFIG.axsize_byte_access_en {false} \
  CONFIG.bar0_indicator {1} \
  CONFIG.bar1_indicator {0} \
  CONFIG.bar2_indicator {0} \
  CONFIG.bar3_indicator {0} \
  CONFIG.bar4_indicator {0} \
  CONFIG.bar5_indicator {0} \
  CONFIG.bar_indicator {BAR_0} \
  CONFIG.barlite2 {7} \
  CONFIG.bridge_registers_offset_enable {false} \
  CONFIG.c_ats_enable {false} \
  CONFIG.c_ats_switch_unique_bdf {1} \
  CONFIG.c_m_axi_num_read {8} \
  CONFIG.c_m_axi_num_readq {2} \
  CONFIG.c_m_axi_num_write {8} \
  CONFIG.c_pri_enable {false} \
  CONFIG.c_s_axi_num_read {8} \
  CONFIG.c_s_axi_num_write {8} \
  CONFIG.c_s_axi_supports_narrow_burst {false} \
  CONFIG.c_smmu_en {0} \
  CONFIG.cfg_ext_if {false} \
  CONFIG.cfg_mgmt_if {false} \
  CONFIG.comp_timeout {50ms} \
  CONFIG.copy_pf0 {true} \
  CONFIG.copy_sriov_pf0 {true} \
  CONFIG.coreclk_freq {500} \
  CONFIG.ctrl_skip_mask {true} \
  CONFIG.dedicate_perst {false} \
  CONFIG.device_port_type {PCI_Express_Endpoint_device} \
  CONFIG.disable_bram_pipeline {false} \
  CONFIG.disable_eq_synchronizer {false} \
  CONFIG.disable_gt_loc {false} \
  CONFIG.dma_reset_source_sel {User_Reset} \
  CONFIG.drp_clk_sel {Internal} \
  CONFIG.dsc_bypass_rd {0000} \
  CONFIG.dsc_bypass_rd_out {0000} \
  CONFIG.dsc_bypass_wr {0000} \
  CONFIG.dsc_bypass_wr_out {0000} \
  CONFIG.ecc_en {false} \
  CONFIG.en_axi_master_if {true} \
  CONFIG.en_axi_mm_mqdma {true} \
  CONFIG.en_axi_slave_if {true} \
  CONFIG.en_axi_st_mqdma {false} \
  CONFIG.en_bridge {false} \
  CONFIG.en_coreclk_es1 {false} \
  CONFIG.en_dbg_descramble {false} \
  CONFIG.en_debug_ports {false} \
  CONFIG.en_dma_and_bridge {false} \
  CONFIG.en_ext_ch_gt_drp {false} \
  CONFIG.en_gt_selection {false} \
  CONFIG.en_l23_entry {false} \
  CONFIG.en_mqdma {false} \
  CONFIG.en_pcie_drp {false} \
  CONFIG.en_transceiver_status_ports {false} \
  CONFIG.enable_ats_switch {FALSE} \
  CONFIG.enable_auto_rxeq {False} \
  CONFIG.enable_ccix {FALSE} \
  CONFIG.enable_code {0000} \
  CONFIG.enable_dvsec {FALSE} \
  CONFIG.enable_gen4 {false} \
  CONFIG.enable_ibert {false} \
  CONFIG.enable_jtag_dbg {false} \
  CONFIG.enable_lane_reversal {false} \
  CONFIG.enable_mark_debug {false} \
  CONFIG.enable_more_clk {false} \
  CONFIG.enable_multi_pcie {false} \
  CONFIG.enable_pcie_debug {False} \
  CONFIG.enable_resource_reduction {false} \
  CONFIG.enable_slave_read_64os {false} \
  CONFIG.ext_startup_primitive {false} \
  CONFIG.ext_sys_clk_bufg {false} \
  CONFIG.ext_xvc_vsec_enable {false} \
  CONFIG.free_run_freq {100_MHz} \
  CONFIG.functional_mode {DMA} \
  CONFIG.gen4_eieos_0s7 {true} \
  CONFIG.gen_pipe_debug {false} \
  CONFIG.gtcom_in_core_usp {2} \
  CONFIG.gtwiz_in_core_us {1} \
  CONFIG.gtwiz_in_core_usp {1} \
  CONFIG.include_baroffset_reg {true} \
  CONFIG.ins_loss_profile {Add-in_Card} \
  CONFIG.intx_rx_pin_en {true} \
  CONFIG.legacy_cfg_ext_if {false} \
  CONFIG.local_test {false} \
  CONFIG.master_cal_only {false} \
  CONFIG.mcap_enablement {None} \
  CONFIG.mcap_fpga_bitstream_version {00000000} \
  CONFIG.mode_selection {Basic} \
  CONFIG.mpsoc_pl_rp_enable {false} \
  CONFIG.msi_rx_pin_en {FALSE} \
  CONFIG.msix_rx_decode_en {FALSE} \
  CONFIG.msix_rx_pin_en {TRUE} \
  CONFIG.msix_type {HARD} \
  CONFIG.mult_pf_des {false} \
  CONFIG.num_queues {1} \
  CONFIG.old_bridge_timeout {false} \
  CONFIG.parity_settings {None} \
  CONFIG.pcie_blk_locn {X0Y1} \
  CONFIG.pcie_extended_tag {false} \
  CONFIG.pcie_id_if {false} \
  CONFIG.pcie_mgt.BOARD.ASSOCIATED_PARAM {PCIE_BOARD_INTERFACE} \
  CONFIG.pciebar2axibar_0 {0x0000000000000000} \
  CONFIG.pciebar2axibar_1 {0x0000000000000000} \
  CONFIG.pciebar2axibar_2 {0x0000000000000000} \
  CONFIG.pciebar2axibar_3 {0x0000000000000000} \
  CONFIG.pciebar2axibar_4 {0x0000000000000000} \
  CONFIG.pciebar2axibar_5 {0x0000000000000000} \
  CONFIG.pciebar2axibar_6 {0x0000000000000000} \
  CONFIG.pciebar2axibar_axil_master {0x00000000} \
  CONFIG.pciebar2axibar_axist_bypass {0x0000000000000000} \
  CONFIG.pciebar2axibar_xdma {0x0000000000000000} \
  CONFIG.performance {false} \
  CONFIG.pf0_Use_Class_Code_Lookup_Assistant {false} \
  CONFIG.pf0_Use_Class_Code_Lookup_Assistant_mqdma {false} \
  CONFIG.pf0_aer_cap_ecrc_gen_and_check_capable {false} \
  CONFIG.pf0_ari_enabled {false} \
  CONFIG.pf0_ats_enabled {false} \
  CONFIG.pf0_bar0_64bit {false} \
  CONFIG.pf0_bar0_64bit_mqdma {false} \
  CONFIG.pf0_bar0_enabled {true} \
  CONFIG.pf0_bar0_enabled_mqdma {true} \
  CONFIG.pf0_bar0_index {0} \
  CONFIG.pf0_bar0_prefetchable {false} \
  CONFIG.pf0_bar0_prefetchable_mqdma {false} \
  CONFIG.pf0_bar0_scale {Kilobytes} \
  CONFIG.pf0_bar0_scale_mqdma {Kilobytes} \
  CONFIG.pf0_bar0_size {128} \
  CONFIG.pf0_bar0_size_mqdma {128} \
  CONFIG.pf0_bar0_type {Memory} \
  CONFIG.pf0_bar0_type_mqdma {DMA} \
  CONFIG.pf0_bar1_64bit {false} \
  CONFIG.pf0_bar1_64bit_mqdma {false} \
  CONFIG.pf0_bar1_enabled {false} \
  CONFIG.pf0_bar1_enabled_mqdma {false} \
  CONFIG.pf0_bar1_index {7} \
  CONFIG.pf0_bar1_prefetchable {false} \
  CONFIG.pf0_bar1_prefetchable_mqdma {false} \
  CONFIG.pf0_bar1_scale {Kilobytes} \
  CONFIG.pf0_bar1_scale_mqdma {Kilobytes} \
  CONFIG.pf0_bar1_size {4} \
  CONFIG.pf0_bar1_size_mqdma {128} \
  CONFIG.pf0_bar1_type {Memory} \
  CONFIG.pf0_bar1_type_mqdma {N/A} \
  CONFIG.pf0_bar2_64bit {false} \
  CONFIG.pf0_bar2_64bit_mqdma {false} \
  CONFIG.pf0_bar2_enabled {false} \
  CONFIG.pf0_bar2_enabled_mqdma {false} \
  CONFIG.pf0_bar2_index {7} \
  CONFIG.pf0_bar2_prefetchable {false} \
  CONFIG.pf0_bar2_prefetchable_mqdma {false} \
  CONFIG.pf0_bar2_scale {Kilobytes} \
  CONFIG.pf0_bar2_scale_mqdma {Kilobytes} \
  CONFIG.pf0_bar2_size {4} \
  CONFIG.pf0_bar2_size_mqdma {128} \
  CONFIG.pf0_bar2_type {Memory} \
  CONFIG.pf0_bar2_type_mqdma {N/A} \
  CONFIG.pf0_bar3_64bit {false} \
  CONFIG.pf0_bar3_64bit_mqdma {false} \
  CONFIG.pf0_bar3_enabled {false} \
  CONFIG.pf0_bar3_enabled_mqdma {false} \
  CONFIG.pf0_bar3_index {7} \
  CONFIG.pf0_bar3_prefetchable {false} \
  CONFIG.pf0_bar3_prefetchable_mqdma {false} \
  CONFIG.pf0_bar3_scale {Kilobytes} \
  CONFIG.pf0_bar3_scale_mqdma {Kilobytes} \
  CONFIG.pf0_bar3_size {4} \
  CONFIG.pf0_bar3_size_mqdma {128} \
  CONFIG.pf0_bar3_type {Memory} \
  CONFIG.pf0_bar3_type_mqdma {N/A} \
  CONFIG.pf0_bar4_64bit {false} \
  CONFIG.pf0_bar4_64bit_mqdma {false} \
  CONFIG.pf0_bar4_enabled {false} \
  CONFIG.pf0_bar4_enabled_mqdma {false} \
  CONFIG.pf0_bar4_index {7} \
  CONFIG.pf0_bar4_prefetchable {false} \
  CONFIG.pf0_bar4_prefetchable_mqdma {false} \
  CONFIG.pf0_bar4_scale {Kilobytes} \
  CONFIG.pf0_bar4_scale_mqdma {Kilobytes} \
  CONFIG.pf0_bar4_size {4} \
  CONFIG.pf0_bar4_size_mqdma {128} \
  CONFIG.pf0_bar4_type {Memory} \
  CONFIG.pf0_bar4_type_mqdma {N/A} \
  CONFIG.pf0_bar5_64bit {false} \
  CONFIG.pf0_bar5_enabled {false} \
  CONFIG.pf0_bar5_enabled_mqdma {false} \
  CONFIG.pf0_bar5_index {7} \
  CONFIG.pf0_bar5_prefetchable {false} \
  CONFIG.pf0_bar5_prefetchable_mqdma {false} \
  CONFIG.pf0_bar5_scale {Kilobytes} \
  CONFIG.pf0_bar5_scale_mqdma {Kilobytes} \
  CONFIG.pf0_bar5_size {4} \
  CONFIG.pf0_bar5_size_mqdma {128} \
  CONFIG.pf0_bar5_type {Memory} \
  CONFIG.pf0_bar5_type_mqdma {N/A} \
  CONFIG.pf0_base_class_menu {Simple_communication_controllers} \
  CONFIG.pf0_base_class_menu_mqdma {Memory_controller} \
  CONFIG.pf0_class_code {058000} \
  CONFIG.pf0_class_code_base {05} \
  CONFIG.pf0_class_code_base_mqdma {05} \
  CONFIG.pf0_class_code_interface {00} \
  CONFIG.pf0_class_code_interface_mqdma {00} \
  CONFIG.pf0_class_code_mqdma {058000} \
  CONFIG.pf0_class_code_sub {80} \
  CONFIG.pf0_class_code_sub_mqdma {80} \
  CONFIG.pf0_device_id {7021} \
  CONFIG.pf0_expansion_rom_enabled {false} \
  CONFIG.pf0_expansion_rom_scale {Kilobytes} \
  CONFIG.pf0_expansion_rom_size {4} \
  CONFIG.pf0_expansion_rom_type {N/A} \
  CONFIG.pf0_interrupt_pin {NONE} \
  CONFIG.pf0_link_status_slot_clock_config {true} \
  CONFIG.pf0_msi_cap_multimsgcap {1_vector} \
  CONFIG.pf0_msi_enabled {false} \
  CONFIG.pf0_msix_cap_pba_bir {BAR_0} \
  CONFIG.pf0_msix_cap_pba_offset {00008FE0} \
  CONFIG.pf0_msix_cap_table_bir {BAR_0} \
  CONFIG.pf0_msix_cap_table_offset {00008000} \
  CONFIG.pf0_msix_cap_table_size {01F} \
  CONFIG.pf0_msix_enabled {true} \
  CONFIG.pf0_msix_enabled_mqdma {false} \
  CONFIG.pf0_msix_impl_locn {Internal} \
  CONFIG.pf0_pri_enabled {false} \
  CONFIG.pf0_rbar_cap_bar0 {0xffffffffffff} \
  CONFIG.pf0_rbar_cap_bar1 {0x000000000000} \
  CONFIG.pf0_rbar_cap_bar2 {0x000000000000} \
  CONFIG.pf0_rbar_cap_bar3 {0x000000000000} \
  CONFIG.pf0_rbar_cap_bar4 {0x000000000000} \
  CONFIG.pf0_rbar_cap_bar5 {0x000000000000} \
  CONFIG.pf0_rbar_num {1} \
  CONFIG.pf0_revision_id {00} \
  CONFIG.pf0_sriov_bar0_64bit {false} \
  CONFIG.pf0_sriov_bar0_enabled {true} \
  CONFIG.pf0_sriov_bar0_prefetchable {false} \
  CONFIG.pf0_sriov_bar0_scale {Kilobytes} \
  CONFIG.pf0_sriov_bar0_size {2} \
  CONFIG.pf0_sriov_bar0_type {DMA} \
  CONFIG.pf0_sriov_bar1_64bit {false} \
  CONFIG.pf0_sriov_bar1_enabled {false} \
  CONFIG.pf0_sriov_bar1_prefetchable {false} \
  CONFIG.pf0_sriov_bar1_scale {Kilobytes} \
  CONFIG.pf0_sriov_bar1_size {2} \
  CONFIG.pf0_sriov_bar1_type {N/A} \
  CONFIG.pf0_sriov_bar2_64bit {false} \
  CONFIG.pf0_sriov_bar2_enabled {false} \
  CONFIG.pf0_sriov_bar2_prefetchable {false} \
  CONFIG.pf0_sriov_bar2_scale {Kilobytes} \
  CONFIG.pf0_sriov_bar2_size {2} \
  CONFIG.pf0_sriov_bar2_type {N/A} \
  CONFIG.pf0_sriov_bar3_64bit {false} \
  CONFIG.pf0_sriov_bar3_enabled {false} \
  CONFIG.pf0_sriov_bar3_prefetchable {false} \
  CONFIG.pf0_sriov_bar3_scale {Kilobytes} \
  CONFIG.pf0_sriov_bar3_size {2} \
  CONFIG.pf0_sriov_bar3_type {N/A} \
  CONFIG.pf0_sriov_bar4_64bit {false} \
  CONFIG.pf0_sriov_bar4_enabled {false} \
  CONFIG.pf0_sriov_bar4_prefetchable {false} \
  CONFIG.pf0_sriov_bar4_scale {Kilobytes} \
  CONFIG.pf0_sriov_bar4_size {2} \
  CONFIG.pf0_sriov_bar4_type {N/A} \
  CONFIG.pf0_sriov_bar5_64bit {false} \
  CONFIG.pf0_sriov_bar5_enabled {false} \
  CONFIG.pf0_sriov_bar5_prefetchable {false} \
  CONFIG.pf0_sriov_bar5_scale {Kilobytes} \
  CONFIG.pf0_sriov_bar5_size {2} \
  CONFIG.pf0_sriov_bar5_type {N/A} \
  CONFIG.pf0_sriov_cap_ver {1} \
  CONFIG.pf0_sub_class_interface_menu {Generic_XT_compatible_serial_controller} \
  CONFIG.pf0_sub_class_interface_menu_mqdma {Other_memory_controller} \
  CONFIG.pf0_subsystem_id {0007} \
  CONFIG.pf0_subsystem_vendor_id {10EE} \
  CONFIG.pf0_vendor_id_mqdma {10EE} \
  CONFIG.pf1_Use_Class_Code_Lookup_Assistant_mqdma {false} \
  CONFIG.pf1_bar0_64bit {false} \
  CONFIG.pf1_bar0_64bit_mqdma {false} \
  CONFIG.pf1_bar0_enabled {true} \
  CONFIG.pf1_bar0_enabled_mqdma {true} \
  CONFIG.pf1_bar0_index {0} \
  CONFIG.pf1_bar0_prefetchable {false} \
  CONFIG.pf1_bar0_prefetchable_mqdma {false} \
  CONFIG.pf1_bar0_scale {Kilobytes} \
  CONFIG.pf1_bar0_scale_mqdma {Kilobytes} \
  CONFIG.pf1_bar0_size {128} \
  CONFIG.pf1_bar0_size_mqdma {128} \
  CONFIG.pf1_bar0_type {Memory} \
  CONFIG.pf1_bar0_type_mqdma {DMA} \
  CONFIG.pf1_bar1_64bit {false} \
  CONFIG.pf1_bar1_64bit_mqdma {false} \
  CONFIG.pf1_bar1_enabled {false} \
  CONFIG.pf1_bar1_enabled_mqdma {false} \
  CONFIG.pf1_bar1_index {7} \
  CONFIG.pf1_bar1_prefetchable {false} \
  CONFIG.pf1_bar1_prefetchable_mqdma {false} \
  CONFIG.pf1_bar1_scale {Kilobytes} \
  CONFIG.pf1_bar1_scale_mqdma {Kilobytes} \
  CONFIG.pf1_bar1_size {128} \
  CONFIG.pf1_bar1_size_mqdma {128} \
  CONFIG.pf1_bar1_type {Memory} \
  CONFIG.pf1_bar1_type_mqdma {N/A} \
  CONFIG.pf1_bar2_64bit {false} \
  CONFIG.pf1_bar2_64bit_mqdma {false} \
  CONFIG.pf1_bar2_enabled {false} \
  CONFIG.pf1_bar2_enabled_mqdma {false} \
  CONFIG.pf1_bar2_index {7} \
  CONFIG.pf1_bar2_prefetchable {false} \
  CONFIG.pf1_bar2_prefetchable_mqdma {false} \
  CONFIG.pf1_bar2_scale {Kilobytes} \
  CONFIG.pf1_bar2_scale_mqdma {Kilobytes} \
  CONFIG.pf1_bar2_size {128} \
  CONFIG.pf1_bar2_size_mqdma {128} \
  CONFIG.pf1_bar2_type {Memory} \
  CONFIG.pf1_bar2_type_mqdma {N/A} \
  CONFIG.pf1_bar3_64bit {false} \
  CONFIG.pf1_bar3_64bit_mqdma {false} \
  CONFIG.pf1_bar3_enabled {false} \
  CONFIG.pf1_bar3_enabled_mqdma {false} \
  CONFIG.pf1_bar3_index {7} \
  CONFIG.pf1_bar3_prefetchable {false} \
  CONFIG.pf1_bar3_prefetchable_mqdma {false} \
  CONFIG.pf1_bar3_scale {Kilobytes} \
  CONFIG.pf1_bar3_scale_mqdma {Kilobytes} \
  CONFIG.pf1_bar3_size {128} \
  CONFIG.pf1_bar3_size_mqdma {128} \
  CONFIG.pf1_bar3_type {Memory} \
  CONFIG.pf1_bar3_type_mqdma {N/A} \
  CONFIG.pf1_bar4_64bit {false} \
  CONFIG.pf1_bar4_64bit_mqdma {false} \
  CONFIG.pf1_bar4_enabled {false} \
  CONFIG.pf1_bar4_enabled_mqdma {false} \
  CONFIG.pf1_bar4_index {7} \
  CONFIG.pf1_bar4_prefetchable {false} \
  CONFIG.pf1_bar4_prefetchable_mqdma {false} \
  CONFIG.pf1_bar4_scale {Kilobytes} \
  CONFIG.pf1_bar4_scale_mqdma {Kilobytes} \
  CONFIG.pf1_bar4_size {128} \
  CONFIG.pf1_bar4_size_mqdma {128} \
  CONFIG.pf1_bar4_type {Memory} \
  CONFIG.pf1_bar4_type_mqdma {N/A} \
  CONFIG.pf1_bar5_enabled {false} \
  CONFIG.pf1_bar5_enabled_mqdma {false} \
  CONFIG.pf1_bar5_index {7} \
  CONFIG.pf1_bar5_prefetchable {false} \
  CONFIG.pf1_bar5_prefetchable_mqdma {false} \
  CONFIG.pf1_bar5_scale {Kilobytes} \
  CONFIG.pf1_bar5_scale_mqdma {Kilobytes} \
  CONFIG.pf1_bar5_size {128} \
  CONFIG.pf1_bar5_size_mqdma {128} \
  CONFIG.pf1_bar5_type {Memory} \
  CONFIG.pf1_bar5_type_mqdma {N/A} \
  CONFIG.pf1_base_class_menu {Simple_communication_controllers} \
  CONFIG.pf1_base_class_menu_mqdma {Memory_controller} \
  CONFIG.pf1_class_code {070001} \
  CONFIG.pf1_class_code_base {07} \
  CONFIG.pf1_class_code_base_mqdma {05} \
  CONFIG.pf1_class_code_interface {01} \
  CONFIG.pf1_class_code_interface_mqdma {00} \
  CONFIG.pf1_class_code_mqdma {058000} \
  CONFIG.pf1_class_code_sub {00} \
  CONFIG.pf1_class_code_sub_mqdma {80} \
  CONFIG.pf1_device_id {1041} \
  CONFIG.pf1_expansion_rom_enabled {false} \
  CONFIG.pf1_expansion_rom_scale {Kilobytes} \
  CONFIG.pf1_expansion_rom_size {4} \
  CONFIG.pf1_expansion_rom_type {N/A} \
  CONFIG.pf1_msi_enabled {false} \
  CONFIG.pf1_msix_cap_pba_bir {BAR_0} \
  CONFIG.pf1_msix_cap_pba_offset {00009FE0} \
  CONFIG.pf1_msix_cap_table_bir {BAR_0} \
  CONFIG.pf1_msix_cap_table_offset {00009000} \
  CONFIG.pf1_msix_cap_table_size {020} \
  CONFIG.pf1_msix_enabled {false} \
  CONFIG.pf1_msix_enabled_mqdma {false} \
  CONFIG.pf1_pciebar2axibar_0 {0x0000000000000000} \
  CONFIG.pf1_pciebar2axibar_1 {0x0000000000000000} \
  CONFIG.pf1_pciebar2axibar_2 {0x0000000000000000} \
  CONFIG.pf1_pciebar2axibar_3 {0x0000000000000000} \
  CONFIG.pf1_pciebar2axibar_4 {0x0000000000000000} \
  CONFIG.pf1_pciebar2axibar_5 {0x0000000000000000} \
  CONFIG.pf1_pciebar2axibar_6 {0x0000000000000000} \
  CONFIG.pf1_rbar_cap_bar0 {0xffffffffffff} \
  CONFIG.pf1_rbar_cap_bar1 {0x000000000000} \
  CONFIG.pf1_rbar_cap_bar2 {0x000000000000} \
  CONFIG.pf1_rbar_cap_bar3 {0x000000000000} \
  CONFIG.pf1_rbar_cap_bar4 {0x000000000000} \
  CONFIG.pf1_rbar_cap_bar5 {0x000000000000} \
  CONFIG.pf1_rbar_num {1} \
  CONFIG.pf1_sriov_bar0_64bit {false} \
  CONFIG.pf1_sriov_bar0_enabled {true} \
  CONFIG.pf1_sriov_bar0_prefetchable {false} \
  CONFIG.pf1_sriov_bar0_scale {Kilobytes} \
  CONFIG.pf1_sriov_bar0_size {2} \
  CONFIG.pf1_sriov_bar0_type {DMA} \
  CONFIG.pf1_sriov_bar1_64bit {false} \
  CONFIG.pf1_sriov_bar1_enabled {false} \
  CONFIG.pf1_sriov_bar1_prefetchable {false} \
  CONFIG.pf1_sriov_bar1_scale {Kilobytes} \
  CONFIG.pf1_sriov_bar1_size {2} \
  CONFIG.pf1_sriov_bar1_type {N/A} \
  CONFIG.pf1_sriov_bar2_64bit {false} \
  CONFIG.pf1_sriov_bar2_enabled {false} \
  CONFIG.pf1_sriov_bar2_prefetchable {false} \
  CONFIG.pf1_sriov_bar2_scale {Kilobytes} \
  CONFIG.pf1_sriov_bar2_size {2} \
  CONFIG.pf1_sriov_bar2_type {N/A} \
  CONFIG.pf1_sriov_bar3_64bit {false} \
  CONFIG.pf1_sriov_bar3_enabled {false} \
  CONFIG.pf1_sriov_bar3_prefetchable {false} \
  CONFIG.pf1_sriov_bar3_scale {Kilobytes} \
  CONFIG.pf1_sriov_bar3_size {2} \
  CONFIG.pf1_sriov_bar3_type {N/A} \
  CONFIG.pf1_sriov_bar4_64bit {false} \
  CONFIG.pf1_sriov_bar4_enabled {false} \
  CONFIG.pf1_sriov_bar4_prefetchable {false} \
  CONFIG.pf1_sriov_bar4_scale {Kilobytes} \
  CONFIG.pf1_sriov_bar4_size {2} \
  CONFIG.pf1_sriov_bar4_type {N/A} \
  CONFIG.pf1_sriov_bar5_64bit {false} \
  CONFIG.pf1_sriov_bar5_enabled {false} \
  CONFIG.pf1_sriov_bar5_prefetchable {false} \
  CONFIG.pf1_sriov_bar5_scale {Kilobytes} \
  CONFIG.pf1_sriov_bar5_size {2} \
  CONFIG.pf1_sriov_bar5_type {N/A} \
  CONFIG.pf1_sub_class_interface_menu {16450_compatible_serial_controller} \
  CONFIG.pf1_sub_class_interface_menu_mqdma {Other_memory_controller} \
  CONFIG.pf1_vendor_id {10EE} \
  CONFIG.pf1_vendor_id_mqdma {10EE} \
  CONFIG.pf2_Use_Class_Code_Lookup_Assistant_mqdma {false} \
  CONFIG.pf2_bar0_64bit {false} \
  CONFIG.pf2_bar0_64bit_mqdma {false} \
  CONFIG.pf2_bar0_enabled {true} \
  CONFIG.pf2_bar0_enabled_mqdma {true} \
  CONFIG.pf2_bar0_index {0} \
  CONFIG.pf2_bar0_prefetchable {false} \
  CONFIG.pf2_bar0_prefetchable_mqdma {false} \
  CONFIG.pf2_bar0_scale {Kilobytes} \
  CONFIG.pf2_bar0_scale_mqdma {Kilobytes} \
  CONFIG.pf2_bar0_size {128} \
  CONFIG.pf2_bar0_size_mqdma {128} \
  CONFIG.pf2_bar0_type {Memory} \
  CONFIG.pf2_bar0_type_mqdma {DMA} \
  CONFIG.pf2_bar1_64bit {false} \
  CONFIG.pf2_bar1_64bit_mqdma {false} \
  CONFIG.pf2_bar1_enabled {true} \
  CONFIG.pf2_bar1_enabled_mqdma {false} \
  CONFIG.pf2_bar1_index {7} \
  CONFIG.pf2_bar1_prefetchable {false} \
  CONFIG.pf2_bar1_prefetchable_mqdma {false} \
  CONFIG.pf2_bar1_scale {Kilobytes} \
  CONFIG.pf2_bar1_scale_mqdma {Kilobytes} \
  CONFIG.pf2_bar1_size {128} \
  CONFIG.pf2_bar1_size_mqdma {128} \
  CONFIG.pf2_bar1_type {Memory} \
  CONFIG.pf2_bar1_type_mqdma {N/A} \
  CONFIG.pf2_bar2_64bit {false} \
  CONFIG.pf2_bar2_64bit_mqdma {false} \
  CONFIG.pf2_bar2_enabled {true} \
  CONFIG.pf2_bar2_enabled_mqdma {false} \
  CONFIG.pf2_bar2_index {7} \
  CONFIG.pf2_bar2_prefetchable {false} \
  CONFIG.pf2_bar2_prefetchable_mqdma {false} \
  CONFIG.pf2_bar2_scale {Kilobytes} \
  CONFIG.pf2_bar2_scale_mqdma {Kilobytes} \
  CONFIG.pf2_bar2_size {128} \
  CONFIG.pf2_bar2_size_mqdma {128} \
  CONFIG.pf2_bar2_type {Memory} \
  CONFIG.pf2_bar2_type_mqdma {N/A} \
  CONFIG.pf2_bar3_64bit {false} \
  CONFIG.pf2_bar3_64bit_mqdma {false} \
  CONFIG.pf2_bar3_enabled {true} \
  CONFIG.pf2_bar3_enabled_mqdma {false} \
  CONFIG.pf2_bar3_index {7} \
  CONFIG.pf2_bar3_prefetchable {false} \
  CONFIG.pf2_bar3_prefetchable_mqdma {false} \
  CONFIG.pf2_bar3_scale {Kilobytes} \
  CONFIG.pf2_bar3_scale_mqdma {Kilobytes} \
  CONFIG.pf2_bar3_size {128} \
  CONFIG.pf2_bar3_size_mqdma {128} \
  CONFIG.pf2_bar3_type {Memory} \
  CONFIG.pf2_bar3_type_mqdma {N/A} \
  CONFIG.pf2_bar4_64bit {false} \
  CONFIG.pf2_bar4_64bit_mqdma {false} \
  CONFIG.pf2_bar4_enabled {true} \
  CONFIG.pf2_bar4_enabled_mqdma {false} \
  CONFIG.pf2_bar4_index {7} \
  CONFIG.pf2_bar4_prefetchable {false} \
  CONFIG.pf2_bar4_prefetchable_mqdma {false} \
  CONFIG.pf2_bar4_scale {Kilobytes} \
  CONFIG.pf2_bar4_scale_mqdma {Kilobytes} \
  CONFIG.pf2_bar4_size {128} \
  CONFIG.pf2_bar4_size_mqdma {128} \
  CONFIG.pf2_bar4_type {Memory} \
  CONFIG.pf2_bar4_type_mqdma {N/A} \
  CONFIG.pf2_bar5_enabled {true} \
  CONFIG.pf2_bar5_enabled_mqdma {false} \
  CONFIG.pf2_bar5_index {7} \
  CONFIG.pf2_bar5_prefetchable {false} \
  CONFIG.pf2_bar5_prefetchable_mqdma {false} \
  CONFIG.pf2_bar5_scale {Kilobytes} \
  CONFIG.pf2_bar5_scale_mqdma {Kilobytes} \
  CONFIG.pf2_bar5_size {128} \
  CONFIG.pf2_bar5_size_mqdma {128} \
  CONFIG.pf2_bar5_type {Memory} \
  CONFIG.pf2_bar5_type_mqdma {N/A} \
  CONFIG.pf2_base_class_menu {Memory_controller} \
  CONFIG.pf2_base_class_menu_mqdma {Memory_controller} \
  CONFIG.pf2_class_code {058000} \
  CONFIG.pf2_class_code_base {05} \
  CONFIG.pf2_class_code_base_mqdma {05} \
  CONFIG.pf2_class_code_interface {00} \
  CONFIG.pf2_class_code_interface_mqdma {00} \
  CONFIG.pf2_class_code_mqdma {058000} \
  CONFIG.pf2_class_code_sub {80} \
  CONFIG.pf2_class_code_sub_mqdma {80} \
  CONFIG.pf2_device_id {1040} \
  CONFIG.pf2_expansion_rom_enabled {false} \
  CONFIG.pf2_expansion_rom_scale {Kilobytes} \
  CONFIG.pf2_expansion_rom_size {4} \
  CONFIG.pf2_expansion_rom_type {N/A} \
  CONFIG.pf2_msi_enabled {false} \
  CONFIG.pf2_msix_enabled_mqdma {false} \
  CONFIG.pf2_pciebar2axibar_0 {0x0000000000000000} \
  CONFIG.pf2_pciebar2axibar_1 {0x0000000000000000} \
  CONFIG.pf2_pciebar2axibar_2 {0x0000000000000000} \
  CONFIG.pf2_pciebar2axibar_3 {0x0000000000000000} \
  CONFIG.pf2_pciebar2axibar_4 {0x0000000000000000} \
  CONFIG.pf2_pciebar2axibar_5 {0x0000000000000000} \
  CONFIG.pf2_rbar_cap_bar0 {0xffffffffffff} \
  CONFIG.pf2_rbar_cap_bar1 {0x000000000000} \
  CONFIG.pf2_rbar_cap_bar2 {0x000000000000} \
  CONFIG.pf2_rbar_cap_bar3 {0x000000000000} \
  CONFIG.pf2_rbar_cap_bar4 {0x000000000000} \
  CONFIG.pf2_rbar_cap_bar5 {0x000000000000} \
  CONFIG.pf2_rbar_num {1} \
  CONFIG.pf2_sriov_bar0_64bit {false} \
  CONFIG.pf2_sriov_bar0_enabled {true} \
  CONFIG.pf2_sriov_bar0_prefetchable {false} \
  CONFIG.pf2_sriov_bar0_scale {Kilobytes} \
  CONFIG.pf2_sriov_bar0_size {2} \
  CONFIG.pf2_sriov_bar0_type {DMA} \
  CONFIG.pf2_sriov_bar1_64bit {false} \
  CONFIG.pf2_sriov_bar1_enabled {false} \
  CONFIG.pf2_sriov_bar1_prefetchable {false} \
  CONFIG.pf2_sriov_bar1_scale {Kilobytes} \
  CONFIG.pf2_sriov_bar1_size {2} \
  CONFIG.pf2_sriov_bar1_type {N/A} \
  CONFIG.pf2_sriov_bar2_64bit {false} \
  CONFIG.pf2_sriov_bar2_enabled {false} \
  CONFIG.pf2_sriov_bar2_prefetchable {false} \
  CONFIG.pf2_sriov_bar2_scale {Kilobytes} \
  CONFIG.pf2_sriov_bar2_size {2} \
  CONFIG.pf2_sriov_bar2_type {N/A} \
  CONFIG.pf2_sriov_bar3_64bit {false} \
  CONFIG.pf2_sriov_bar3_enabled {false} \
  CONFIG.pf2_sriov_bar3_prefetchable {false} \
  CONFIG.pf2_sriov_bar3_scale {Kilobytes} \
  CONFIG.pf2_sriov_bar3_size {2} \
  CONFIG.pf2_sriov_bar3_type {N/A} \
  CONFIG.pf2_sriov_bar4_64bit {false} \
  CONFIG.pf2_sriov_bar4_enabled {false} \
  CONFIG.pf2_sriov_bar4_prefetchable {false} \
  CONFIG.pf2_sriov_bar4_scale {Kilobytes} \
  CONFIG.pf2_sriov_bar4_size {2} \
  CONFIG.pf2_sriov_bar4_type {N/A} \
  CONFIG.pf2_sriov_bar5_64bit {false} \
  CONFIG.pf2_sriov_bar5_enabled {false} \
  CONFIG.pf2_sriov_bar5_prefetchable {false} \
  CONFIG.pf2_sriov_bar5_scale {Kilobytes} \
  CONFIG.pf2_sriov_bar5_size {2} \
  CONFIG.pf2_sriov_bar5_type {N/A} \
  CONFIG.pf2_sub_class_interface_menu {Other_memory_controller} \
  CONFIG.pf2_sub_class_interface_menu_mqdma {Other_memory_controller} \
  CONFIG.pf2_vendor_id_mqdma {10EE} \
  CONFIG.pf3_Use_Class_Code_Lookup_Assistant_mqdma {false} \
  CONFIG.pf3_bar0_64bit {false} \
  CONFIG.pf3_bar0_64bit_mqdma {false} \
  CONFIG.pf3_bar0_enabled {true} \
  CONFIG.pf3_bar0_enabled_mqdma {true} \
  CONFIG.pf3_bar0_index {0} \
  CONFIG.pf3_bar0_prefetchable {false} \
  CONFIG.pf3_bar0_prefetchable_mqdma {false} \
  CONFIG.pf3_bar0_scale {Kilobytes} \
  CONFIG.pf3_bar0_scale_mqdma {Kilobytes} \
  CONFIG.pf3_bar0_size {128} \
  CONFIG.pf3_bar0_size_mqdma {128} \
  CONFIG.pf3_bar0_type {Memory} \
  CONFIG.pf3_bar0_type_mqdma {DMA} \
  CONFIG.pf3_bar1_64bit {false} \
  CONFIG.pf3_bar1_64bit_mqdma {false} \
  CONFIG.pf3_bar1_enabled {true} \
  CONFIG.pf3_bar1_enabled_mqdma {false} \
  CONFIG.pf3_bar1_index {7} \
  CONFIG.pf3_bar1_prefetchable {false} \
  CONFIG.pf3_bar1_prefetchable_mqdma {false} \
  CONFIG.pf3_bar1_scale {Kilobytes} \
  CONFIG.pf3_bar1_scale_mqdma {Kilobytes} \
  CONFIG.pf3_bar1_size {128} \
  CONFIG.pf3_bar1_size_mqdma {128} \
  CONFIG.pf3_bar1_type {Memory} \
  CONFIG.pf3_bar1_type_mqdma {N/A} \
  CONFIG.pf3_bar2_64bit {false} \
  CONFIG.pf3_bar2_64bit_mqdma {false} \
  CONFIG.pf3_bar2_enabled {true} \
  CONFIG.pf3_bar2_enabled_mqdma {false} \
  CONFIG.pf3_bar2_index {7} \
  CONFIG.pf3_bar2_prefetchable {false} \
  CONFIG.pf3_bar2_prefetchable_mqdma {false} \
  CONFIG.pf3_bar2_scale {Kilobytes} \
  CONFIG.pf3_bar2_scale_mqdma {Kilobytes} \
  CONFIG.pf3_bar2_size {128} \
  CONFIG.pf3_bar2_size_mqdma {128} \
  CONFIG.pf3_bar2_type {Memory} \
  CONFIG.pf3_bar2_type_mqdma {N/A} \
  CONFIG.pf3_bar3_64bit {false} \
  CONFIG.pf3_bar3_64bit_mqdma {false} \
  CONFIG.pf3_bar3_enabled {true} \
  CONFIG.pf3_bar3_enabled_mqdma {false} \
  CONFIG.pf3_bar3_index {7} \
  CONFIG.pf3_bar3_prefetchable {false} \
  CONFIG.pf3_bar3_prefetchable_mqdma {false} \
  CONFIG.pf3_bar3_scale {Kilobytes} \
  CONFIG.pf3_bar3_scale_mqdma {Kilobytes} \
  CONFIG.pf3_bar3_size {128} \
  CONFIG.pf3_bar3_size_mqdma {128} \
  CONFIG.pf3_bar3_type {Memory} \
  CONFIG.pf3_bar3_type_mqdma {N/A} \
  CONFIG.pf3_bar4_64bit {false} \
  CONFIG.pf3_bar4_64bit_mqdma {false} \
  CONFIG.pf3_bar4_enabled {true} \
  CONFIG.pf3_bar4_enabled_mqdma {false} \
  CONFIG.pf3_bar4_index {7} \
  CONFIG.pf3_bar4_prefetchable {false} \
  CONFIG.pf3_bar4_prefetchable_mqdma {false} \
  CONFIG.pf3_bar4_scale {Kilobytes} \
  CONFIG.pf3_bar4_scale_mqdma {Kilobytes} \
  CONFIG.pf3_bar4_size {128} \
  CONFIG.pf3_bar4_size_mqdma {128} \
  CONFIG.pf3_bar4_type {Memory} \
  CONFIG.pf3_bar4_type_mqdma {N/A} \
  CONFIG.pf3_bar5_enabled {true} \
  CONFIG.pf3_bar5_enabled_mqdma {false} \
  CONFIG.pf3_bar5_index {7} \
  CONFIG.pf3_bar5_prefetchable {false} \
  CONFIG.pf3_bar5_prefetchable_mqdma {false} \
  CONFIG.pf3_bar5_scale {Kilobytes} \
  CONFIG.pf3_bar5_scale_mqdma {Kilobytes} \
  CONFIG.pf3_bar5_size {128} \
  CONFIG.pf3_bar5_size_mqdma {128} \
  CONFIG.pf3_bar5_type {Memory} \
  CONFIG.pf3_bar5_type_mqdma {N/A} \
  CONFIG.pf3_base_class_menu {Memory_controller} \
  CONFIG.pf3_base_class_menu_mqdma {Memory_controller} \
  CONFIG.pf3_class_code {058000} \
  CONFIG.pf3_class_code_base {05} \
  CONFIG.pf3_class_code_base_mqdma {05} \
  CONFIG.pf3_class_code_interface {00} \
  CONFIG.pf3_class_code_interface_mqdma {00} \
  CONFIG.pf3_class_code_mqdma {058000} \
  CONFIG.pf3_class_code_sub {80} \
  CONFIG.pf3_class_code_sub_mqdma {80} \
  CONFIG.pf3_device_id {1039} \
  CONFIG.pf3_expansion_rom_enabled {false} \
  CONFIG.pf3_expansion_rom_scale {Kilobytes} \
  CONFIG.pf3_expansion_rom_size {4} \
  CONFIG.pf3_expansion_rom_type {N/A} \
  CONFIG.pf3_msi_enabled {false} \
  CONFIG.pf3_msix_enabled_mqdma {false} \
  CONFIG.pf3_pciebar2axibar_0 {0x0000000000000000} \
  CONFIG.pf3_pciebar2axibar_1 {0x0000000000000000} \
  CONFIG.pf3_pciebar2axibar_2 {0x0000000000000000} \
  CONFIG.pf3_pciebar2axibar_3 {0x0000000000000000} \
  CONFIG.pf3_pciebar2axibar_4 {0x0000000000000000} \
  CONFIG.pf3_pciebar2axibar_5 {0x0000000000000000} \
  CONFIG.pf3_rbar_cap_bar0 {0xffffffffffff} \
  CONFIG.pf3_rbar_cap_bar1 {0x000000000000} \
  CONFIG.pf3_rbar_cap_bar2 {0x000000000000} \
  CONFIG.pf3_rbar_cap_bar3 {0x000000000000} \
  CONFIG.pf3_rbar_cap_bar4 {0x000000000000} \
  CONFIG.pf3_rbar_cap_bar5 {0x000000000000} \
  CONFIG.pf3_rbar_num {1} \
  CONFIG.pf3_sriov_bar0_64bit {false} \
  CONFIG.pf3_sriov_bar0_enabled {true} \
  CONFIG.pf3_sriov_bar0_prefetchable {false} \
  CONFIG.pf3_sriov_bar0_scale {Kilobytes} \
  CONFIG.pf3_sriov_bar0_size {2} \
  CONFIG.pf3_sriov_bar0_type {DMA} \
  CONFIG.pf3_sriov_bar1_64bit {false} \
  CONFIG.pf3_sriov_bar1_enabled {false} \
  CONFIG.pf3_sriov_bar1_prefetchable {false} \
  CONFIG.pf3_sriov_bar1_scale {Kilobytes} \
  CONFIG.pf3_sriov_bar1_size {2} \
  CONFIG.pf3_sriov_bar1_type {N/A} \
  CONFIG.pf3_sriov_bar2_64bit {false} \
  CONFIG.pf3_sriov_bar2_enabled {false} \
  CONFIG.pf3_sriov_bar2_prefetchable {false} \
  CONFIG.pf3_sriov_bar2_scale {Kilobytes} \
  CONFIG.pf3_sriov_bar2_size {2} \
  CONFIG.pf3_sriov_bar2_type {N/A} \
  CONFIG.pf3_sriov_bar3_64bit {false} \
  CONFIG.pf3_sriov_bar3_enabled {false} \
  CONFIG.pf3_sriov_bar3_prefetchable {false} \
  CONFIG.pf3_sriov_bar3_scale {Kilobytes} \
  CONFIG.pf3_sriov_bar3_size {2} \
  CONFIG.pf3_sriov_bar3_type {N/A} \
  CONFIG.pf3_sriov_bar4_64bit {false} \
  CONFIG.pf3_sriov_bar4_enabled {false} \
  CONFIG.pf3_sriov_bar4_prefetchable {false} \
  CONFIG.pf3_sriov_bar4_scale {Kilobytes} \
  CONFIG.pf3_sriov_bar4_size {2} \
  CONFIG.pf3_sriov_bar4_type {N/A} \
  CONFIG.pf3_sriov_bar5_64bit {false} \
  CONFIG.pf3_sriov_bar5_enabled {false} \
  CONFIG.pf3_sriov_bar5_prefetchable {false} \
  CONFIG.pf3_sriov_bar5_scale {Kilobytes} \
  CONFIG.pf3_sriov_bar5_size {2} \
  CONFIG.pf3_sriov_bar5_type {N/A} \
  CONFIG.pf3_sub_class_interface_menu {Other_memory_controller} \
  CONFIG.pf3_sub_class_interface_menu_mqdma {Other_memory_controller} \
  CONFIG.pf3_vendor_id_mqdma {10EE} \
  CONFIG.pf_swap {false} \
  CONFIG.pipe_line_stage {2} \
  CONFIG.pipe_sim {false} \
  CONFIG.pl_link_cap_max_link_speed {5.0_GT/s} \
  CONFIG.pl_link_cap_max_link_width {X1} \
  CONFIG.plltype {QPLL1} \
  CONFIG.post_synth_sim_en {false} \
  CONFIG.rbar_enable {false} \
  CONFIG.ref_clk_freq {100_MHz} \
  CONFIG.runbit_fix {false} \
  CONFIG.rx_detect {Default} \
  CONFIG.s_axi_id_width {4} \
  CONFIG.select_quad {GTH_Quad_128} \
  CONFIG.set_finite_credit {false} \
  CONFIG.silicon_rev {Pre-Production} \
  CONFIG.soft_reset_en {false} \
  CONFIG.split_dma {false} \
  CONFIG.split_dma_single_pf {false} \
  CONFIG.sys_reset_polarity {ACTIVE_LOW} \
  CONFIG.timeout0_sel {14} \
  CONFIG.timeout1_sel {15} \
  CONFIG.timeout_mult {3} \
  CONFIG.tl_credits_cd {15} \
  CONFIG.tl_credits_ch {15} \
  CONFIG.tl_pf_enable_reg {1} \
  CONFIG.two_bypass_bar {false} \
  CONFIG.type1_membase_memlimit_enable {Disabled} \
  CONFIG.type1_prefetchable_membase_memlimit {Disabled} \
  CONFIG.use_standard_interfaces {false} \
  CONFIG.usplus_es1_seqnum_bypass {false} \
  CONFIG.usr_irq_exdes {false} \
  CONFIG.vcu118_board {false} \
  CONFIG.vcu1525_ddr_ex {false} \
  CONFIG.vendor_id {10EE} \
  CONFIG.vu9p_board {false} \
  CONFIG.vu9p_tul_ex {false} \
  CONFIG.xdma_axi_intf_mm {AXI_Memory_Mapped} \
  CONFIG.xdma_axilite_slave {false} \
  CONFIG.xdma_dsc_bypass {false} \
  CONFIG.xdma_en {true} \
  CONFIG.xdma_non_incremental_exdes {false} \
  CONFIG.xdma_num_usr_irq {16} \
  CONFIG.xdma_pcie_64bit_en {false} \
  CONFIG.xdma_pcie_prefetchable {false} \
  CONFIG.xdma_rnum_chnl {1} \
  CONFIG.xdma_rnum_rids {32} \
  CONFIG.xdma_scale {Kilobytes} \
  CONFIG.xdma_size {64} \
  CONFIG.xdma_st_infinite_desc_exdes {false} \
  CONFIG.xdma_sts_ports {false} \
  CONFIG.xdma_wnum_chnl {1} \
  CONFIG.xdma_wnum_rids {16} \
  CONFIG.xlnx_ref_board {None} " [get_ips xdma_0]


