

# Project configuration -------------------------------------------------------

create_project -force xdma480t
set_property SOURCE_MGMT_MODE None [current_project]
set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1]
set_property PART xc7k480tffg1156-2L [current_project]

# Files inclusion

# add_file ../sources/Top_wrapper.v



# set_property GENERATE_SYNTH_CHECKPOINT true [get_files ../sources/ip/Top_auto_cc_0/Top_auto_cc_0.xci]
generate_target all [get_files ../sources/ip/Top_auto_cc_0/Top_auto_cc_0.xci]

# add_file ../sources/Top.bd

# generate_target all [get_files ../sources/Top.bd]


# read_ip ../sources/ip/Top_auto_cc_0/Top_auto_cc_0.xci
# read_ip ../sources/ip/Top_auto_ds_1/Top_auto_ds_1.xci
# read_ip ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci
# read_ip ../sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci
# read_ip ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci
# read_ip ../sources/ip/Top_auto_cc_1/Top_auto_cc_1.xci
# read_ip ../sources/ip/Top_auto_ds_2/Top_auto_ds_2.xci
# read_ip ../sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci
# read_ip ../sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci
# read_ip ../sources/ip/Top_auto_cc_2/Top_auto_cc_2.xci
# read_ip ../sources/ip/Top_auto_pc_0/Top_auto_pc_0.xci
# read_ip ../sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci
# read_ip ../sources/ip/Top_xbar_0/Top_xbar_0.xci
# read_ip ../sources/ip/Top_auto_cc_3/Top_auto_cc_3.xci
# read_ip ../sources/ip/Top_auto_pc_1/Top_auto_pc_1.xci
# read_ip ../sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci
# read_ip ../sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci
# read_ip ../sources/ip/Top_auto_ds_0/Top_auto_ds_0.xci
# read_ip ../sources/ip/Top_auto_us_0/Top_auto_us_0.xci
# read_ip ../sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci
# read_ip ../sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci



# generate_target all  

# Constraints inclusion

add_file -fileset constrs_1 ../normal.xdc
# set_property TARGET_CONSTRS_FILE /home/colin/develop/abstractaccelerator/fpga/xc7z010/timing.xdc [current_fileset -constrset]

# Top-level specification
set_property TOP Top_wrapper [current_fileset]

# Verilog Includes
# set_property INCLUDE_DIRS { /home/colin/develop/abstractaccelerator/fpga/xc7z010 } [current_fileset]

# Verilog Parameters / VHDL Generics
set_property GENERIC { FREQ=100000000 SECS=1 } -objects [get_filesets sources_1]


close_project

# Design flow -----------------------------------------------------------------

open_project xdma480t

# Synthesis

# PRESYNTH
# set_property DESIGN_MODE GateLvl [current_fileset]
reset_run synth_1
launch_runs synth_1
wait_on_run synth_1
#report_property [get_runs synth_1]
if { [get_property STATUS [get_runs synth_1]] ne "synth_design Complete!" } { exit 1 }

# Place and Route

reset_run impl_1
launch_runs impl_1
wait_on_run impl_1
#report_property [get_runs impl_1]
if { [get_property STATUS [get_runs impl_1]] ne "route_design Complete!" } { exit 1 }

# Bitstream generation

open_run impl_1
write_bitstream -force xdma480t
write_debug_probes -force -quiet xdma480t.ltx

close_project

