267 lines
14 KiB
Plaintext
267 lines
14 KiB
Plaintext
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<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2022.2 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. -->
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<Project Version="7" Minor="61" Path="/home/colin/develop/netfpga_pcie_x1_xdma_bram/pcie_xdma_test.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="8306b796781a4dfeb4e157eab322d15c"/>
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<Option Name="Part" Val="xc7k480tffg1156-2L"/>
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<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
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<Option Name="CompiledLibDirXSim" Val=""/>
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<Option Name="CompiledLibDirModelSim" Val="$PCACHEDIR/compile_simlib/modelsim"/>
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<Option Name="CompiledLibDirQuesta" Val="$PCACHEDIR/compile_simlib/questa"/>
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<Option Name="CompiledLibDirXcelium" Val="$PCACHEDIR/compile_simlib/xcelium"/>
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<Option Name="CompiledLibDirVCS" Val="$PCACHEDIR/compile_simlib/vcs"/>
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<Option Name="CompiledLibDirRiviera" Val="$PCACHEDIR/compile_simlib/riviera"/>
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<Option Name="CompiledLibDirActivehdl" Val="$PCACHEDIR/compile_simlib/activehdl"/>
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<Option Name="SimulatorInstallDirModelSim" Val=""/>
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<Option Name="SimulatorInstallDirQuesta" Val=""/>
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<Option Name="SimulatorInstallDirXcelium" Val=""/>
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<Option Name="SimulatorInstallDirVCS" Val=""/>
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<Option Name="SimulatorInstallDirRiviera" Val=""/>
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<Option Name="SimulatorInstallDirActiveHdl" Val=""/>
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<Option Name="SimulatorGccInstallDirModelSim" Val=""/>
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<Option Name="SimulatorGccInstallDirQuesta" Val=""/>
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<Option Name="SimulatorGccInstallDirXcelium" Val=""/>
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<Option Name="SimulatorGccInstallDirVCS" Val=""/>
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<Option Name="SimulatorGccInstallDirRiviera" Val=""/>
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<Option Name="SimulatorGccInstallDirActiveHdl" Val=""/>
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<Option Name="SimulatorVersionXsim" Val="2022.2"/>
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<Option Name="SimulatorVersionModelSim" Val="2022.2"/>
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<Option Name="SimulatorVersionQuesta" Val="2022.2"/>
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<Option Name="SimulatorVersionXcelium" Val="21.09.009"/>
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<Option Name="SimulatorVersionVCS" Val="S-2021.09"/>
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<Option Name="SimulatorVersionRiviera" Val="2022.04"/>
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<Option Name="SimulatorVersionActiveHdl" Val="13.0"/>
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<Option Name="SimulatorGccVersionXsim" Val="6.2.0"/>
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<Option Name="SimulatorGccVersionModelSim" Val="7.4.0"/>
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<Option Name="SimulatorGccVersionQuesta" Val="7.4.0"/>
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<Option Name="SimulatorGccVersionXcelium" Val="9.3.0"/>
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<Option Name="SimulatorGccVersionVCS" Val="9.2.0"/>
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<Option Name="SimulatorGccVersionRiviera" Val="9.3.0"/>
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<Option Name="SimulatorGccVersionActiveHdl" Val="9.3.0"/>
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<Option Name="TargetLanguage" Val="VHDL"/>
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<Option Name="BoardPart" Val=""/>
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<Option Name="ActiveSimSet" Val="sim_1"/>
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<Option Name="DefaultLib" Val="xil_defaultlib"/>
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<Option Name="ProjectType" Val="Default"/>
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<Option Name="IPOutputRepo" Val="$PCACHEDIR/ip"/>
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<Option Name="IPDefaultOutputPath" Val="$PGENDIR/sources_1"/>
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<Option Name="IPCachePermission" Val="read"/>
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<Option Name="IPCachePermission" Val="write"/>
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<Option Name="EnableCoreContainer" Val="FALSE"/>
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<Option Name="EnableResourceEstimation" Val="FALSE"/>
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<Option Name="SimCompileState" Val="TRUE"/>
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<Option Name="CreateRefXciForCoreContainers" Val="FALSE"/>
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<Option Name="IPUserFilesDir" Val="$PIPUSERFILESDIR"/>
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<Option Name="IPStaticSourceDir" Val="$PIPUSERFILESDIR/ipstatic"/>
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<Option Name="EnableBDX" Val="FALSE"/>
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<Option Name="WTXSimLaunchSim" Val="0"/>
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<Option Name="WTModelSimLaunchSim" Val="0"/>
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<Option Name="WTQuestaLaunchSim" Val="0"/>
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<Option Name="WTIesLaunchSim" Val="0"/>
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<Option Name="WTVcsLaunchSim" Val="0"/>
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<Option Name="WTRivieraLaunchSim" Val="0"/>
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<Option Name="WTActivehdlLaunchSim" Val="0"/>
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<Option Name="WTXSimExportSim" Val="4"/>
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<Option Name="WTModelSimExportSim" Val="4"/>
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<Option Name="WTQuestaExportSim" Val="4"/>
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<Option Name="WTIesExportSim" Val="4"/>
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<Option Name="WTVcsExportSim" Val="4"/>
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<Option Name="WTRivieraExportSim" Val="4"/>
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<Option Name="WTActivehdlExportSim" Val="4"/>
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<Option Name="GenerateIPUpgradeLog" Val="TRUE"/>
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<Option Name="XSimRadix" Val="hex"/>
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<Option Name="XSimTimeUnit" Val="ns"/>
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<Option Name="XSimArrayDisplayLimit" Val="1024"/>
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<Option Name="XSimTraceLimit" Val="65536"/>
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<Option Name="SimTypes" Val="rtl"/>
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<Option Name="MEMEnableMemoryMapGeneration" Val="TRUE"/>
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<Option Name="DcpsUptoDate" Val="TRUE"/>
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<Option Name="ClassicSocBoot" Val="FALSE"/>
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<Option Name="LocalIPRepoLeafDirName" Val="ip_repo"/>
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</Configuration>
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<FileSets Version="1" Minor="31">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1" RelGenDir="$PGENDIR/sources_1">
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<Filter Type="Srcs"/>
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<File Path="$PPRDIR/RTL/axi_bram.sv">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/RTL/fpga_top.sv">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="fpga_top"/>
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<Option Name="dataflowViewerSettings" Val="min_width=16"/>
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</Config>
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</FileSet>
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1" RelGenDir="$PGENDIR/constrs_1">
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<Filter Type="Constrs"/>
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<File Path="$PPRDIR/fpga_top.xdc">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="ConstrsType" Val="XDC"/>
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</Config>
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</FileSet>
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<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1" RelGenDir="$PGENDIR/sim_1">
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<Filter Type="Srcs"/>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="fpga_top"/>
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<Option Name="TopLib" Val="xil_defaultlib"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="TransportPathDelay" Val="0"/>
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<Option Name="TransportIntDelay" Val="0"/>
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<Option Name="SelectedSimModel" Val="rtl"/>
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<Option Name="PamDesignTestbench" Val=""/>
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<Option Name="PamDutBypassFile" Val="xil_dut_bypass"/>
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<Option Name="PamSignalDriverFile" Val="xil_bypass_driver"/>
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<Option Name="PamPseudoTop" Val="pseudo_tb"/>
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<Option Name="SrcSet" Val="sources_1"/>
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</Config>
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</FileSet>
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<FileSet Name="utils_1" Type="Utils" RelSrcDir="$PSRCDIR/utils_1" RelGenDir="$PGENDIR/utils_1">
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<Filter Type="Utils"/>
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<Config>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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<FileSet Name="xdma_0" Type="BlockSrcs" RelSrcDir="$PSRCDIR/xdma_0" RelGenDir="$PGENDIR/xdma_0">
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<File Path="$PPRDIR/IP/xdma_0/xdma_0.xci">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/IP/xdma_0/xdma_0.xci"/>
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<Attr Name="ImportTime" Val="1562482864"/>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="TopModule" Val="xdma_0"/>
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<Option Name="dataflowViewerSettings" Val="min_width=16"/>
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<Option Name="UseBlackboxStub" Val="1"/>
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</Config>
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</FileSet>
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</FileSets>
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<Simulators>
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<Simulator Name="XSim">
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<Option Name="Description" Val="Vivado Simulator"/>
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<Option Name="CompiledLib" Val="0"/>
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</Simulator>
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<Simulator Name="ModelSim">
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<Option Name="Description" Val="ModelSim Simulator"/>
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</Simulator>
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<Simulator Name="Questa">
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<Option Name="Description" Val="Questa Advanced Simulator"/>
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</Simulator>
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<Simulator Name="Xcelium">
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<Option Name="Description" Val="Xcelium Parallel Simulator"/>
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</Simulator>
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<Simulator Name="VCS">
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<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
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</Simulator>
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<Simulator Name="Riviera">
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<Option Name="Description" Val="Riviera-PRO Simulator"/>
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</Simulator>
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</Simulators>
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<Runs Version="1" Minor="19">
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<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7k480tffg1156-2L" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/synth_1">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2017"/>
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<Step Id="synth_design"/>
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</Strategy>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2017"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="xdma_0_synth_1" Type="Ft3:Synth" SrcSet="xdma_0" Part="xc7k480tffg1156-2L" ConstrsSet="xdma_0" Description="Vivado Synthesis Defaults" AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" IncludeInArchive="true" IsChild="false" AutoIncrementalDir="$PSRCDIR/utils_1/imports/xdma_0_synth_1" AutoRQSDir="$PSRCDIR/utils_1/imports/xdma_0_synth_1">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2022"/>
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<Step Id="synth_design"/>
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</Strategy>
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<ReportStrategy Name="Vivado Synthesis Default Reports" Flow="Vivado Synthesis 2022"/>
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||
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7k480tffg1156-2L" ConstrsSet="constrs_1" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" State="current" SynthRun="synth_1" IncludeInArchive="true" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/impl_1">
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<Strategy Version="1" Minor="2">
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2017"/>
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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<Step Id="write_bitstream"/>
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</Strategy>
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<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2017"/>
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<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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<RQSFiles/>
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</Run>
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<Run Id="xdma_0_impl_1" Type="Ft2:EntireDesign" Part="xc7k480tffg1156-2L" ConstrsSet="xdma_0" Description="Default settings for Implementation." AutoIncrementalCheckpoint="false" WriteIncrSynthDcp="false" SynthRun="xdma_0_synth_1" IncludeInArchive="false" IsChild="false" GenFullBitstream="true" AutoIncrementalDir="$PSRCDIR/utils_1/imports/xdma_0_impl_1" AutoRQSDir="$PSRCDIR/utils_1/imports/xdma_0_impl_1">
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<Strategy Version="1" Minor="2">
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||
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<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2022"/>
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||
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<Step Id="init_design"/>
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<Step Id="opt_design"/>
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<Step Id="power_opt_design"/>
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<Step Id="place_design"/>
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<Step Id="post_place_power_opt_design"/>
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<Step Id="phys_opt_design"/>
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<Step Id="route_design"/>
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<Step Id="post_route_phys_opt_design"/>
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||
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<Step Id="write_bitstream"/>
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||
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|
</Strategy>
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||
|
|
<ReportStrategy Name="Vivado Implementation Default Reports" Flow="Vivado Implementation 2022"/>
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||
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|
<Report Name="ROUTE_DESIGN.REPORT_METHODOLOGY" Enabled="1"/>
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||
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<RQSFiles/>
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||
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</Run>
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||
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</Runs>
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||
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<Board/>
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||
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<DashboardSummary Version="1" Minor="0">
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||
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<Dashboards>
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||
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<Dashboard Name="default_dashboard">
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||
|
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<Gadgets>
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||
|
|
<Gadget Name="drc_1" Type="drc" Version="1" Row="2" Column="0">
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||
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_drc_0 "/>
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||
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</Gadget>
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||
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<Gadget Name="methodology_1" Type="methodology" Version="1" Row="2" Column="1">
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||
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_methodology_0 "/>
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||
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</Gadget>
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||
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<Gadget Name="power_1" Type="power" Version="1" Row="1" Column="0">
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||
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_power_0 "/>
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||
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</Gadget>
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||
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<Gadget Name="timing_1" Type="timing" Version="1" Row="0" Column="1">
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||
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_route_report_timing_summary_0 "/>
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</Gadget>
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||
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<Gadget Name="utilization_1" Type="utilization" Version="1" Row="0" Column="0">
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||
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<GadgetParam Name="REPORTS" Type="string_list" Value="synth_1#synth_1_synth_report_utilization_0 "/>
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||
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<GadgetParam Name="RUN.STEP" Type="string" Value="synth_design"/>
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||
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<GadgetParam Name="RUN.TYPE" Type="string" Value="synthesis"/>
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</Gadget>
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||
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<Gadget Name="utilization_2" Type="utilization" Version="1" Row="1" Column="1">
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||
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<GadgetParam Name="REPORTS" Type="string_list" Value="impl_1#impl_1_place_report_utilization_0 "/>
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</Gadget>
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</Gadgets>
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||
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</Dashboard>
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||
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<CurrentDashboard>default_dashboard</CurrentDashboard>
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</Dashboards>
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</DashboardSummary>
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||
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</Project>
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