65 lines
1.6 KiB
Tcl
65 lines
1.6 KiB
Tcl
|
|
||
|
|
|
||
|
|
# Project configuration -------------------------------------------------------
|
||
|
|
|
||
|
|
create_project -force xdma480t
|
||
|
|
set_property SOURCE_MGMT_MODE None [current_project]
|
||
|
|
set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1]
|
||
|
|
set_property PART xc7k480tffg1156-2L [current_project]
|
||
|
|
|
||
|
|
# Files inclusion
|
||
|
|
|
||
|
|
add_file ../RTL/axi_bram.sv
|
||
|
|
|
||
|
|
add_file ../RTL/fpga_top.sv
|
||
|
|
|
||
|
|
add_file ../IP/xdma_0/xdma_0.xci
|
||
|
|
|
||
|
|
# Constraints inclusion
|
||
|
|
|
||
|
|
add_file -fileset constrs_1 ../fpga_top.xdc
|
||
|
|
# set_property TARGET_CONSTRS_FILE /home/colin/develop/abstractaccelerator/fpga/xc7z010/timing.xdc [current_fileset -constrset]
|
||
|
|
|
||
|
|
# Top-level specification
|
||
|
|
set_property TOP fpga_top [current_fileset]
|
||
|
|
|
||
|
|
# Verilog Includes
|
||
|
|
# set_property INCLUDE_DIRS { /home/colin/develop/abstractaccelerator/fpga/xc7z010 } [current_fileset]
|
||
|
|
|
||
|
|
# Verilog Parameters / VHDL Generics
|
||
|
|
set_property GENERIC { FREQ=100000000 SECS=1 } -objects [get_filesets sources_1]
|
||
|
|
|
||
|
|
|
||
|
|
close_project
|
||
|
|
|
||
|
|
# Design flow -----------------------------------------------------------------
|
||
|
|
|
||
|
|
open_project xdma480t
|
||
|
|
|
||
|
|
# Synthesis
|
||
|
|
|
||
|
|
# PRESYNTH
|
||
|
|
# set_property DESIGN_MODE GateLvl [current_fileset]
|
||
|
|
reset_run synth_1
|
||
|
|
launch_runs synth_1
|
||
|
|
wait_on_run synth_1
|
||
|
|
#report_property [get_runs synth_1]
|
||
|
|
if { [get_property STATUS [get_runs synth_1]] ne "synth_design Complete!" } { exit 1 }
|
||
|
|
|
||
|
|
# Place and Route
|
||
|
|
|
||
|
|
reset_run impl_1
|
||
|
|
launch_runs impl_1
|
||
|
|
wait_on_run impl_1
|
||
|
|
#report_property [get_runs impl_1]
|
||
|
|
if { [get_property STATUS [get_runs impl_1]] ne "route_design Complete!" } { exit 1 }
|
||
|
|
|
||
|
|
# Bitstream generation
|
||
|
|
|
||
|
|
open_run impl_1
|
||
|
|
write_bitstream -force xdma480t
|
||
|
|
write_debug_probes -force -quiet xdma480t.ltx
|
||
|
|
|
||
|
|
close_project
|
||
|
|
|