97 lines
3.1 KiB
Tcl
97 lines
3.1 KiB
Tcl
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# Project configuration -------------------------------------------------------
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create_project -force xdma480t
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set_property SOURCE_MGMT_MODE None [current_project]
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set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1]
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set_property PART xc7k480tffg1156-2L [current_project]
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# Files inclusion
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# add_file ../sources/Top_wrapper.v
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# set_property GENERATE_SYNTH_CHECKPOINT true [get_files ../sources/ip/Top_auto_cc_0/Top_auto_cc_0.xci]
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generate_target all [get_files ../sources/ip/Top_auto_cc_0/Top_auto_cc_0.xci]
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# add_file ../sources/Top.bd
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# generate_target all [get_files ../sources/Top.bd]
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# read_ip ../sources/ip/Top_auto_cc_0/Top_auto_cc_0.xci
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# read_ip ../sources/ip/Top_auto_ds_1/Top_auto_ds_1.xci
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# read_ip ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci
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# read_ip ../sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci
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# read_ip ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci
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# read_ip ../sources/ip/Top_auto_cc_1/Top_auto_cc_1.xci
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# read_ip ../sources/ip/Top_auto_ds_2/Top_auto_ds_2.xci
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# read_ip ../sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci
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# read_ip ../sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci
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# read_ip ../sources/ip/Top_auto_cc_2/Top_auto_cc_2.xci
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# read_ip ../sources/ip/Top_auto_pc_0/Top_auto_pc_0.xci
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# read_ip ../sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci
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# read_ip ../sources/ip/Top_xbar_0/Top_xbar_0.xci
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# read_ip ../sources/ip/Top_auto_cc_3/Top_auto_cc_3.xci
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# read_ip ../sources/ip/Top_auto_pc_1/Top_auto_pc_1.xci
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# read_ip ../sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci
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# read_ip ../sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci
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# read_ip ../sources/ip/Top_auto_ds_0/Top_auto_ds_0.xci
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# read_ip ../sources/ip/Top_auto_us_0/Top_auto_us_0.xci
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# read_ip ../sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci
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# read_ip ../sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci
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# generate_target all
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# Constraints inclusion
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add_file -fileset constrs_1 ../normal.xdc
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# set_property TARGET_CONSTRS_FILE /home/colin/develop/abstractaccelerator/fpga/xc7z010/timing.xdc [current_fileset -constrset]
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# Top-level specification
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set_property TOP Top_wrapper [current_fileset]
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# Verilog Includes
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# set_property INCLUDE_DIRS { /home/colin/develop/abstractaccelerator/fpga/xc7z010 } [current_fileset]
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# Verilog Parameters / VHDL Generics
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set_property GENERIC { FREQ=100000000 SECS=1 } -objects [get_filesets sources_1]
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close_project
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# Design flow -----------------------------------------------------------------
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open_project xdma480t
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# Synthesis
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# PRESYNTH
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# set_property DESIGN_MODE GateLvl [current_fileset]
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reset_run synth_1
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launch_runs synth_1
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wait_on_run synth_1
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#report_property [get_runs synth_1]
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if { [get_property STATUS [get_runs synth_1]] ne "synth_design Complete!" } { exit 1 }
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# Place and Route
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reset_run impl_1
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launch_runs impl_1
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wait_on_run impl_1
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#report_property [get_runs impl_1]
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if { [get_property STATUS [get_runs impl_1]] ne "route_design Complete!" } { exit 1 }
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# Bitstream generation
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open_run impl_1
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write_bitstream -force xdma480t
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write_debug_probes -force -quiet xdma480t.ltx
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close_project
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