xc7k480t/nitefury_pcie_xdma_ddr/project/normal.xdc

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2025-05-10 13:29:27 +08:00
set_property -dict { PACKAGE_PIN P30 IOSTANDARD LVCMOS18 } [get_ports { user_lnk_up_0 }];
# set_property -dict { PACKAGE_PIN M30 IOSTANDARD LVCMOS18 } [get_ports { o_led_blink }];
set_property -dict { PACKAGE_PIN Y26 IOSTANDARD LVCMOS33 PULLUP true } [get_ports {pci_reset}]
# set_property PACKAGE_PIN J8 [get_ports { SYS_CLK_0_clk_p }];
set_property PACKAGE_PIN J8 [get_ports { pcie_clkin_clk_p }];
create_clock -name sys_clk -period 10 [get_ports pcie_clkin_clk_p]
set_property PACKAGE_PIN F2 [get_ports { pcie_mgt_0_txp[0] }];
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullup [current_design]