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Update nitefury_pcie_xdma_ddr.

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Colin 2025-05-10 23:24:56 +08:00
parent 330d8de4f7
commit 2f30b86ab0
26 changed files with 469 additions and 79 deletions
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2
nitefury_pcie_xdma_ddr/project/Makefile
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@ -1,4 +1,6 @@
o:
cd build && vivado -mode batch -notrace -quiet -source ../o.tcl
impl:
cd build && vivado -mode batch -notrace -quiet -source ../test.tcl

25
nitefury_pcie_xdma_ddr/project/o.tcl Normal file
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@ -0,0 +1,25 @@
# 创建Vivado工程（非图形界面模式）
create_project my_project ./my_project -part xc7k480tffg1156-2L -force
# # 生成IP核（以AXI UART Lite为例）
# create_ip -name axi_uartlite -vendor xilinx.com -library ip -version 2.0 -module_name uart_inst
# # 配置IP参数
# set_property -dict [list \
# CONFIG.C_BAUDRATE {115200} \
# CONFIG.C_S_AXI_ACLK_FREQ_HZ {100000000} \
# CONFIG.C_DATA_BITS {8} \
# CONFIG.C_USE_PARITY {0} \
# ] [get_ips uart_inst]
# add_file ../uart_inst.xci
add_file ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci
# 生成IP输出文件（RTL、约束、网表等）
generate_target -force all [get_ips Top_axi_bram_ctrl_0_0]
synth_ip [get_ips Top_axi_bram_ctrl_0_0]
# write_ip_tcl -help
# write_ip_tcl -force -verbose [get_ips uart_inst] ./uart_inst.tcl

4
nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_0/Top_auto_cc_0.xci
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@ -5,7 +5,7 @@
"cell_name": "axi_interconnect_0/m00_couplers/auto_cc",
"component_reference": "xilinx.com:ip:axi_clock_converter:2.1",
"ip_revision": "26",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_0",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_0",
"parameters": {
"component_parameters": {
"PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
@ -61,7 +61,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "26" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_0" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_0" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

8
nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_1/Top_auto_cc_1.xci
View File

@ -5,7 +5,7 @@
"cell_name": "axi_interconnect_0/m01_couplers/auto_cc",
"component_reference": "xilinx.com:ip:axi_clock_converter:2.1",
"ip_revision": "26",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_1",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_1",
"parameters": {
"component_parameters": {
"PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
@ -46,14 +46,14 @@
"ARCHITECTURE": [ { "value": "kintex7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7k480t" } ],
"DEVICE": [ { "value": "xc7k480ti" } ],
"PACKAGE": [ { "value": "ffg1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
@ -61,7 +61,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "26" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_1" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_1" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

8
nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_2/Top_auto_cc_2.xci
View File

@ -5,7 +5,7 @@
"cell_name": "axi_interconnect_0/m02_couplers/auto_cc",
"component_reference": "xilinx.com:ip:axi_clock_converter:2.1",
"ip_revision": "26",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_2",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_2",
"parameters": {
"component_parameters": {
"PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
@ -46,14 +46,14 @@
"ARCHITECTURE": [ { "value": "kintex7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7k480t" } ],
"DEVICE": [ { "value": "xc7k480ti" } ],
"PACKAGE": [ { "value": "ffg1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
@ -61,7 +61,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "26" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_2" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_2" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

8
nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_3/Top_auto_cc_3.xci
View File

@ -5,7 +5,7 @@
"cell_name": "axi_interconnect_0/m03_couplers/auto_cc",
"component_reference": "xilinx.com:ip:axi_clock_converter:2.1",
"ip_revision": "26",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_3",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_3",
"parameters": {
"component_parameters": {
"PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
@ -46,14 +46,14 @@
"ARCHITECTURE": [ { "value": "kintex7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7k480t" } ],
"DEVICE": [ { "value": "xc7k480ti" } ],
"PACKAGE": [ { "value": "ffg1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
@ -61,7 +61,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "26" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_3" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_3" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

6
nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_0/Top_auto_ds_0.xci
View File

@ -5,7 +5,7 @@
"cell_name": "axi_interconnect_0/m00_couplers/auto_ds",
"component_reference": "xilinx.com:ip:axi_dwidth_converter:2.1",
"ip_revision": "27",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_ds_0",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_ds_0",
"parameters": {
"component_parameters": {
"PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
@ -44,7 +44,7 @@
"ARCHITECTURE": [ { "value": "kintex7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7k480t" } ],
"DEVICE": [ { "value": "xc7k480ti" } ],
"PACKAGE": [ { "value": "ffg1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
@ -59,7 +59,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "27" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_ds_0" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_ds_0" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

8
nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_1/Top_auto_ds_1.xci
View File

@ -5,7 +5,7 @@
"cell_name": "axi_interconnect_0/m02_couplers/auto_ds",
"component_reference": "xilinx.com:ip:axi_dwidth_converter:2.1",
"ip_revision": "27",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_ds_1",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_ds_1",
"parameters": {
"component_parameters": {
"PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
@ -44,14 +44,14 @@
"ARCHITECTURE": [ { "value": "kintex7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7k480t" } ],
"DEVICE": [ { "value": "xc7k480ti" } ],
"PACKAGE": [ { "value": "ffg1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
@ -59,7 +59,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "27" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_ds_1" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_ds_1" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

8
nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_2/Top_auto_ds_2.xci
View File

@ -5,7 +5,7 @@
"cell_name": "axi_interconnect_0/m04_couplers/auto_ds",
"component_reference": "xilinx.com:ip:axi_dwidth_converter:2.1",
"ip_revision": "27",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_ds_2",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_ds_2",
"parameters": {
"component_parameters": {
"PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
@ -44,14 +44,14 @@
"ARCHITECTURE": [ { "value": "kintex7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7k480t" } ],
"DEVICE": [ { "value": "xc7k480ti" } ],
"PACKAGE": [ { "value": "ffg1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
@ -59,7 +59,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "27" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_ds_2" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_ds_2" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

8
nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_pc_0/Top_auto_pc_0.xci
View File

@ -5,7 +5,7 @@
"cell_name": "axi_interconnect_0/m00_couplers/auto_pc",
"component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "27",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_pc_0",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_pc_0",
"parameters": {
"component_parameters": {
"SI_PROTOCOL": [ { "value": "AXI4", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
@ -44,14 +44,14 @@
"ARCHITECTURE": [ { "value": "kintex7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7k480t" } ],
"DEVICE": [ { "value": "xc7k480ti" } ],
"PACKAGE": [ { "value": "ffg1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
@ -59,7 +59,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "27" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_pc_0" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_pc_0" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

8
nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_pc_1/Top_auto_pc_1.xci
View File

@ -5,7 +5,7 @@
"cell_name": "axi_interconnect_0/m02_couplers/auto_pc",
"component_reference": "xilinx.com:ip:axi_protocol_converter:2.1",
"ip_revision": "27",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_pc_1",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_pc_1",
"parameters": {
"component_parameters": {
"SI_PROTOCOL": [ { "value": "AXI4", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
@ -44,14 +44,14 @@
"ARCHITECTURE": [ { "value": "kintex7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7k480t" } ],
"DEVICE": [ { "value": "xc7k480ti" } ],
"PACKAGE": [ { "value": "ffg1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
@ -59,7 +59,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "27" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_pc_1" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_pc_1" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

6
nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_us_0/Top_auto_us_0.xci
View File

@ -5,7 +5,7 @@
"cell_name": "axi_interconnect_0/s00_couplers/auto_us",
"component_reference": "xilinx.com:ip:axi_dwidth_converter:2.1",
"ip_revision": "27",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_us_0",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_us_0",
"parameters": {
"component_parameters": {
"PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ],
@ -44,7 +44,7 @@
"ARCHITECTURE": [ { "value": "kintex7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7k480t" } ],
"DEVICE": [ { "value": "xc7k480ti" } ],
"PACKAGE": [ { "value": "ffg1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
@ -59,7 +59,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "27" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_us_0" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_us_0" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

8
nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci
View File

@ -5,7 +5,7 @@
"cell_name": "axi_bram_ctrl_0",
"component_reference": "xilinx.com:ip:axi_bram_ctrl:4.1",
"ip_revision": "7",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_axi_bram_ctrl_0_0",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_axi_bram_ctrl_0_0",
"parameters": {
"component_parameters": {
"DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ],
@ -47,14 +47,14 @@
"ARCHITECTURE": [ { "value": "kintex7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7k480t" } ],
"DEVICE": [ { "value": "xc7k480ti" } ],
"PACKAGE": [ { "value": "ffg1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
@ -62,7 +62,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "7" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_axi_bram_ctrl_0_0" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_axi_bram_ctrl_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

6
nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci
View File

@ -5,7 +5,7 @@
"cell_name": "axi_interconnect_0",
"component_reference": "xilinx.com:ip:axi_interconnect:2.1",
"ip_revision": "28",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_axi_interconnect_0_0",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_axi_interconnect_0_0",
"parameters": {
"component_parameters": {
"NUM_SI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@ -328,7 +328,7 @@
"ARCHITECTURE": [ { "value": "kintex7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7k480t" } ],
"DEVICE": [ { "value": "xc7k480ti" } ],
"PACKAGE": [ { "value": "ffg1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
@ -343,7 +343,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator_AppCore" } ],
"IPREVISION": [ { "value": "28" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_axi_interconnect_0_0" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_axi_interconnect_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

10
nitefury_pcie_xdma_ddr/project/sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci
View File

@ -5,7 +5,7 @@
"cell_name": "blk_mem_gen_0",
"component_reference": "xilinx.com:ip:blk_mem_gen:8.4",
"ip_revision": "5",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_blk_mem_gen_0_0",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_blk_mem_gen_0_0",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "Top_blk_mem_gen_0_0", "resolve_type": "user", "usage": "all" } ],
@ -156,20 +156,20 @@
"C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_COUNT_36K_BRAM": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ],
"C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ],
"C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 5.3746 mW", "resolve_type": "generated", "usage": "all" } ]
"C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 5.10587 mW", "resolve_type": "generated", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "kintex7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7k480t" } ],
"DEVICE": [ { "value": "xc7k480ti" } ],
"PACKAGE": [ { "value": "ffg1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
@ -177,7 +177,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "5" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_blk_mem_gen_0_0" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_blk_mem_gen_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

8
nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci
View File

@ -5,7 +5,7 @@
"cell_name": "mig_7series_1",
"component_reference": "xilinx.com:ip:mig_7series:4.2",
"ip_revision": "1",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_mig_7series_1_0",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_mig_7series_1_0",
"parameters": {
"component_parameters": {
"XML_INPUT_FILE": [ { "value": "mig_b.prj", "value_src": "user", "resolve_type": "user", "usage": "all" } ],
@ -1167,14 +1167,14 @@
"ARCHITECTURE": [ { "value": "kintex7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7k480t" } ],
"DEVICE": [ { "value": "xc7k480ti" } ],
"PACKAGE": [ { "value": "ffg1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
@ -1182,7 +1182,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "1" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_mig_7series_1_0" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_mig_7series_1_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

2
nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/mig_a.prj
View File

@ -19,7 +19,7 @@
<XADC_En>Enabled</XADC_En>
<TargetFPGA>xc7k480t-ffg1156/-2L</TargetFPGA>
<TargetFPGA>xc7k480ti-ffg1156/-2L</TargetFPGA>
<Version>4.2</Version>

2
nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/mig_b.prj
View File

@ -19,7 +19,7 @@
<XADC_En>Enabled</XADC_En>
<TargetFPGA>xc7k480t-ffg1156/-2L</TargetFPGA>
<TargetFPGA>xc7k480ti-ffg1156/-2L</TargetFPGA>
<Version>4.2</Version>

6
nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci
View File

@ -5,7 +5,7 @@
"cell_name": "util_ds_buf_0",
"component_reference": "xilinx.com:ip:util_ds_buf:2.2",
"ip_revision": "29",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_util_ds_buf_0_0",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_util_ds_buf_0_0",
"parameters": {
"component_parameters": {
"C_SIZE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ],
@ -33,7 +33,7 @@
"ARCHITECTURE": [ { "value": "kintex7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7k480t" } ],
"DEVICE": [ { "value": "xc7k480ti" } ],
"PACKAGE": [ { "value": "ffg1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
@ -48,7 +48,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "29" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_util_ds_buf_0_0" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_util_ds_buf_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

8
nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci
View File

@ -5,7 +5,7 @@
"cell_name": "util_vector_logic_1",
"component_reference": "xilinx.com:ip:util_vector_logic:2.0",
"ip_revision": "2",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_util_vector_logic_1_3",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_util_vector_logic_1_3",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "Top_util_vector_logic_1_3", "resolve_type": "user", "usage": "all" } ],
@ -21,14 +21,14 @@
"ARCHITECTURE": [ { "value": "kintex7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7k480t" } ],
"DEVICE": [ { "value": "xc7k480ti" } ],
"PACKAGE": [ { "value": "ffg1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
@ -36,7 +36,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "2" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_util_vector_logic_1_3" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_util_vector_logic_1_3" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

8
nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci
View File

@ -5,7 +5,7 @@
"cell_name": "util_vector_logic_2",
"component_reference": "xilinx.com:ip:util_vector_logic:2.0",
"ip_revision": "2",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_util_vector_logic_1_4",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_util_vector_logic_1_4",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "Top_util_vector_logic_1_4", "resolve_type": "user", "usage": "all" } ],
@ -21,14 +21,14 @@
"ARCHITECTURE": [ { "value": "kintex7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7k480t" } ],
"DEVICE": [ { "value": "xc7k480ti" } ],
"PACKAGE": [ { "value": "ffg1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
@ -36,7 +36,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "2" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_util_vector_logic_1_4" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_util_vector_logic_1_4" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

8
nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci
View File

@ -5,7 +5,7 @@
"cell_name": "axi_interconnect_0/xbar",
"component_reference": "xilinx.com:ip:axi_crossbar:2.1",
"ip_revision": "28",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xbar_0",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xbar_0",
"parameters": {
"component_parameters": {
"ADDR_RANGES": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ],
@ -1244,14 +1244,14 @@
"ARCHITECTURE": [ { "value": "kintex7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7k480t" } ],
"DEVICE": [ { "value": "xc7k480ti" } ],
"PACKAGE": [ { "value": "ffg1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
@ -1259,7 +1259,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "28" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xbar_0" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xbar_0" } ],
"SELECTEDSIMMODEL": [ { "value": "rtl" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

6
nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci
View File

@ -5,7 +5,7 @@
"cell_name": "xdma_1",
"component_reference": "xilinx.com:ip:xdma:4.1",
"ip_revision": "20",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xdma_1_0",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xdma_1_0",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "Top_xdma_1_0", "resolve_type": "user", "usage": "all" } ],
@ -1279,7 +1279,7 @@
"ARCHITECTURE": [ { "value": "kintex7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7k480t" } ],
"DEVICE": [ { "value": "xc7k480ti" } ],
"PACKAGE": [ { "value": "ffg1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
@ -1294,7 +1294,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "20" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xdma_1_0" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xdma_1_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

6
nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci
View File

@ -5,7 +5,7 @@
"cell_name": "xlconstant_0",
"component_reference": "xilinx.com:ip:xlconstant:1.1",
"ip_revision": "7",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xlconstant_0_0",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xlconstant_0_0",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "Top_xlconstant_0_0", "resolve_type": "user", "usage": "all" } ],
@ -20,7 +20,7 @@
"ARCHITECTURE": [ { "value": "kintex7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7k480t" } ],
"DEVICE": [ { "value": "xc7k480ti" } ],
"PACKAGE": [ { "value": "ffg1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
@ -35,7 +35,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "7" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xlconstant_0_0" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xlconstant_0_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

8
nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci
View File

@ -5,7 +5,7 @@
"cell_name": "xlconstant_2",
"component_reference": "xilinx.com:ip:xlconstant:1.1",
"ip_revision": "7",
"gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xlconstant_2_0",
"gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xlconstant_2_0",
"parameters": {
"component_parameters": {
"Component_Name": [ { "value": "Top_xlconstant_2_0", "resolve_type": "user", "usage": "all" } ],
@ -20,14 +20,14 @@
"ARCHITECTURE": [ { "value": "kintex7" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7k480t" } ],
"DEVICE": [ { "value": "xc7k480ti" } ],
"PACKAGE": [ { "value": "ffg1156" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-2L" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "E" } ],
"TEMPERATURE_GRADE": [ { "value": "I" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
@ -35,7 +35,7 @@
"IPCONTEXT": [ { "value": "IP_Integrator" } ],
"IPREVISION": [ { "value": "7" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xlconstant_2_0" } ],
"OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xlconstant_2_0" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "../../ipshared" } ],
"SWVERSION": [ { "value": "2022.2" } ],

363
nitefury_pcie_xdma_ddr/project/uart_inst.xci Normal file
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@ -0,0 +1,363 @@
{
"schema": "xilinx.com:schema:json_instance:1.0",
"ip_inst": {
"xci_name": "uart_inst",
"component_reference": "xilinx.com:ip:axi_uartlite:2.0",
"ip_revision": "31",
"gen_directory": "build/my_project/my_project.gen/sources_1/ip/uart_inst",
"parameters": {
"component_parameters": {
"C_DATA_BITS": [ { "value": "8", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_BAUDRATE": [ { "value": "115200", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_S_AXI_ACLK_FREQ_HZ": [ { "value": "100000000", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_S_AXI_ACLK_FREQ_HZ_d": [ { "value": "100", "resolve_type": "user", "format": "float", "usage": "all" } ],
"Component_Name": [ { "value": "uart_inst", "resolve_type": "user", "usage": "all" } ],
"PARITY": [ { "value": "No_Parity", "resolve_type": "user", "usage": "all" } ],
"C_USE_PARITY": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ],
"C_ODD_PARITY": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ],
"USE_BOARD_FLOW": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ],
"UARTLITE_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ]
},
"model_parameters": {
"C_FAMILY": [ { "value": "zynq", "resolve_type": "generated", "usage": "all" } ],
"C_S_AXI_ACLK_FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_S_AXI_ADDR_WIDTH": [ { "value": "4", "format": "long", "usage": "all" } ],
"C_S_AXI_DATA_WIDTH": [ { "value": "32", "format": "long", "usage": "all" } ],
"C_BAUDRATE": [ { "value": "115200", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_DATA_BITS": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_USE_PARITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ],
"C_ODD_PARITY": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ]
},
"project_parameters": {
"ARCHITECTURE": [ { "value": "zynq" } ],
"BASE_BOARD_PART": [ { "value": "" } ],
"BOARD_CONNECTIONS": [ { "value": "" } ],
"DEVICE": [ { "value": "xc7z020" } ],
"PACKAGE": [ { "value": "clg400" } ],
"PREFHDL": [ { "value": "VERILOG" } ],
"SILICON_REVISION": [ { "value": "" } ],
"SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ],
"SPEEDGRADE": [ { "value": "-1" } ],
"STATIC_POWER": [ { "value": "" } ],
"TEMPERATURE_GRADE": [ { "value": "" } ],
"USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ],
"USE_RDI_GENERATION": [ { "value": "TRUE" } ]
},
"runtime_parameters": {
"IPCONTEXT": [ { "value": "IP_Flow" } ],
"IPREVISION": [ { "value": "31" } ],
"MANAGED": [ { "value": "TRUE" } ],
"OUTPUTDIR": [ { "value": "build/my_project/my_project.gen/sources_1/ip/uart_inst" } ],
"SELECTEDSIMMODEL": [ { "value": "" } ],
"SHAREDDIR": [ { "value": "." } ],
"SWVERSION": [ { "value": "2022.2" } ],
"SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ]
}
},
"boundary": {
"ports": {
"s_axi_aclk": [ { "direction": "in", "driver_value": "0" } ],
"s_axi_aresetn": [ { "direction": "in", "driver_value": "1" } ],
"interrupt": [ { "direction": "out" } ],
"s_axi_awaddr": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
"s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ],
"s_axi_awready": [ { "direction": "out" } ],
"s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ],
"s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
"s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ],
"s_axi_wready": [ { "direction": "out" } ],
"s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
"s_axi_bvalid": [ { "direction": "out" } ],
"s_axi_bready": [ { "direction": "in", "driver_value": "0" } ],
"s_axi_araddr": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ],
"s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ],
"s_axi_arready": [ { "direction": "out" } ],
"s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ],
"s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ],
"s_axi_rvalid": [ { "direction": "out" } ],
"s_axi_rready": [ { "direction": "in", "driver_value": "0" } ],
"rx": [ { "direction": "in", "driver_value": "0" } ],
"tx": [ { "direction": "out" } ]
},
"interfaces": {
"S_AXI": {
"vlnv": "xilinx.com:interface:aximm:1.0",
"abstraction_type": "xilinx.com:interface:aximm_rtl:1.0",
"mode": "slave",
"parameters": {
"DATA_WIDTH": [ { "value": "32", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PROTOCOL": [ { "value": "AXI4LITE", "value_src": "constant", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ID_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ADDR_WIDTH": [ { "value": "4", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BURST": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_LOCK": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_PROT": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_CACHE": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_QOS": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_REGION": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_WSTRB": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_BRESP": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"HAS_RRESP": [ { "value": "1", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"SUPPORTS_NARROW_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_OUTSTANDING": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_OUTSTANDING": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"MAX_BURST_LENGTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_READ_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"NUM_WRITE_THREADS": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"ARADDR": [ { "physical_name": "s_axi_araddr" } ],
"ARREADY": [ { "physical_name": "s_axi_arready" } ],
"ARVALID": [ { "physical_name": "s_axi_arvalid" } ],
"AWADDR": [ { "physical_name": "s_axi_awaddr" } ],
"AWREADY": [ { "physical_name": "s_axi_awready" } ],
"AWVALID": [ { "physical_name": "s_axi_awvalid" } ],
"BREADY": [ { "physical_name": "s_axi_bready" } ],
"BRESP": [ { "physical_name": "s_axi_bresp" } ],
"BVALID": [ { "physical_name": "s_axi_bvalid" } ],
"RDATA": [ { "physical_name": "s_axi_rdata" } ],
"RREADY": [ { "physical_name": "s_axi_rready" } ],
"RRESP": [ { "physical_name": "s_axi_rresp" } ],
"RVALID": [ { "physical_name": "s_axi_rvalid" } ],
"WDATA": [ { "physical_name": "s_axi_wdata" } ],
"WREADY": [ { "physical_name": "s_axi_wready" } ],
"WSTRB": [ { "physical_name": "s_axi_wstrb" } ],
"WVALID": [ { "physical_name": "s_axi_wvalid" } ]
}
},
"ACLK": {
"vlnv": "xilinx.com:signal:clock:1.0",
"abstraction_type": "xilinx.com:signal:clock_rtl:1.0",
"mode": "slave",
"parameters": {
"ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_src": "constant", "usage": "all" } ],
"ASSOCIATED_RESET": [ { "value": "s_axi_aresetn", "value_src": "constant", "usage": "all" } ],
"FREQ_HZ": [ { "value": "100000000", "resolve_type": "user", "format": "long", "usage": "all" } ],
"FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ],
"PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ],
"CLK_DOMAIN": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"CLK": [ { "physical_name": "s_axi_aclk" } ]
}
},
"ARESETN": {
"vlnv": "xilinx.com:signal:reset:1.0",
"abstraction_type": "xilinx.com:signal:reset_rtl:1.0",
"mode": "slave",
"parameters": {
"POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "usage": "all" } ],
"INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"RST": [ { "physical_name": "s_axi_aresetn" } ]
}
},
"INTERRUPT": {
"vlnv": "xilinx.com:signal:interrupt:1.0",
"abstraction_type": "xilinx.com:signal:interrupt_rtl:1.0",
"mode": "master",
"parameters": {
"SENSITIVITY": [ { "value": "EDGE_RISING", "value_src": "constant", "usage": "all" } ],
"PortWidth": [ { "value": "1", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ]
},
"port_maps": {
"INTERRUPT": [ { "physical_name": "interrupt" } ]
}
},
"UART": {
"vlnv": "xilinx.com:interface:uart:1.0",
"abstraction_type": "xilinx.com:interface:uart_rtl:1.0",
"mode": "master",
"parameters": {
"BOARD.ASSOCIATED_PARAM": [ { "value": "UARTLITE_BOARD_INTERFACE", "value_src": "constant", "usage": "all" } ]
},
"port_maps": {
"RxD": [ { "physical_name": "rx" } ],
"TxD": [ { "physical_name": "tx" } ]
}
}
},
"memory_maps": {
"S_AXI": {
"display_name": "S_AXI_MEM",
"description": "Memory Map for S_AXI",
"address_blocks": {
"Reg": {
"base_address": "0",
"range": "4096",
"display_name": "Reg",
"description": "Register Block",
"usage": "register",
"access": "read-write",
"registers": {
"RX_FIFO": {
"address_offset": "0x0",
"size": 32,
"display_name": "RX FIFO",
"description": "Receive data FIFO",
"is_volatile": true,
"access": "read-only",
"reset_value": "0x0",
"fields": {
"RX_DATA": {
"bit_offset": 0,
"bit_width": 8,
"display_name": "Receive Data",
"description": "UART Receive Data\n",
"is_volatile": true,
"access": "read-only"
}
}
},
"TX_FIFO": {
"address_offset": "0x4",
"size": 32,
"display_name": "TX FIFO",
"description": "Transmit data FIFO",
"is_volatile": true,
"access": "write-only",
"reset_value": "0x0",
"fields": {
"TX_DATA": {
"bit_offset": 0,
"bit_width": 8,
"display_name": "Transmit Data",
"description": "UART Transmit Data\n",
"is_volatile": true,
"access": "write-only"
}
}
},
"CTRL_REG": {
"address_offset": "0xC",
"size": 32,
"display_name": "Control Register",
"description": "UART Lite control register",
"is_volatile": true,
"access": "write-only",
"reset_value": "0x0",
"fields": {
"RST_TXFIFO": {
"bit_offset": 0,
"bit_width": 1,
"display_name": "Reset Tx FIFO",
"description": "Reset/clear the transmit FIFO\nWriting a 1 to this bit position clears the transmit FIFO\n 0 - Do nothing\n 1 - Clear the transmit FIFO\n",
"is_volatile": true,
"access": "write-only"
},
"RST_RXFIFO": {
"bit_offset": 1,
"bit_width": 1,
"display_name": "Reset Rx FIFO",
"description": "Reset/clear the receive FIFO\nWriting a 1 to this bit position clears the receive FIFO\n 0 - Do nothing\n 1 - Clear the receive FIFO\n",
"is_volatile": true,
"access": "write-only"
},
"Enable_Intr": {
"bit_offset": 4,
"bit_width": 1,
"display_name": "Enable interrupt",
"description": "Enable interrupt for the AXI UART Lite\n 0 - Disable interrupt signal\n 1 - Enable interrupt signal\n",
"is_volatile": true,
"access": "write-only"
}
}
},
"STAT_REG": {
"address_offset": "0x8",
"size": 32,
"display_name": "Status Register",
"description": "UART Lite status register",
"is_volatile": true,
"access": "read-only",
"reset_value": "0x0",
"fields": {
"RX_FIFO_Valid_Data": {
"bit_offset": 0,
"bit_width": 1,
"display_name": "RX FIFO Valid Data",
"description": "Indicates if the receive FIFO has data.\n 0 - Receive FIFO is empty\n 1 - Receive FIFO has data\n",
"is_volatile": true,
"access": "read-only"
},
"RX_FIFO_Full": {
"bit_offset": 1,
"bit_width": 1,
"display_name": "RX FIFO Full",
"description": "Indicates if the receive FIFO is full.\n 0 - Receive FIFO is not full\n 1 - Receive FIFO is full\n",
"is_volatile": true,
"access": "read-only"
},
"TX_FIFO_Empty": {
"bit_offset": 2,
"bit_width": 1,
"display_name": "TX FIFO Empty",
"description": "Indicates if the transmit FIFO is empty.\n 0 - Transmit FIFO is not empty\n 1 - Transmit FIFO is empty\n",
"is_volatile": true,
"access": "read-only"
},
"TX_FIFO_Full": {
"bit_offset": 3,
"bit_width": 1,
"display_name": "TX FIFO Full",
"description": "Indicates if the transmit FIFO is full.\n 0 - Transmit FIFO is not full\n 1 - Transmit FIFO is full\n",
"is_volatile": true,
"access": "read-only"
},
"Intr_Enabled": {
"bit_offset": 4,
"bit_width": 1,
"display_name": "Interrupt Enabled",
"description": "Indicates that interrupts is enabled.\n 0 - Interrupt is disabled\n 1 - Interrupt is enabled\n",
"is_volatile": true,
"access": "read-only"
},
"Overrun_Error": {
"bit_offset": 5,
"bit_width": 1,
"display_name": "Overrun Error",
"description": "Indicates that a overrun error has occurred after the last time the status register was read. Overrun is when a new character has been received but the receive FIFO is full. The received character is ignored and not written into the receive FIFO. This bit is cleared when the status register is read. 0 - No overrun error has occurred 1 - Overrun error has occurred\n",
"is_volatile": true,
"access": "read-only"
},
"Frame_Error": {
"bit_offset": 6,
"bit_width": 1,
"display_name": "Frame Error",
"description": "Indicates that a frame error has occurred after the last time the status register was read. Frame error is defined as detection of a stop bit with the value 0. The receive character is ignored and not written to the receive FIFO. This bit is cleared when the status register is read. 0 - No frame error has occurred 1 - Frame error has occurred\n",
"is_volatile": true,
"access": "read-only"
},
"Parity_Error": {
"bit_offset": 7,
"bit_width": 1,
"display_name": "Parity Error",
"description": "Indicates that a parity error has occurred after the last time the status register was read. If the UART is configured without any parity handling, this bit is always 0. The received character is written into the receive FIFO. This bit is cleared when the status register is read. 0 - No parity error has occurred 1 - Parity error has occurred\n",
"is_volatile": true,
"access": "read-only"
}
}
}
}
}
}
}
}
}
}
}