From 55677acfded8bd6003fbd6157f7c185d6904709f Mon Sep 17 00:00:00 2001 From: Colin <> Date: Thu, 15 May 2025 00:35:46 +0800 Subject: [PATCH] Update nitefury_pcie_xdma_ddr address map and dma test. pass all. --- nitefury_pcie_xdma_ddr/dma_test.py | 12 +++++++----- .../project/sources/ip/Top_xbar_0/Top_xbar_0.xci | 4 ++-- nitefury_pcie_xdma_ddr/project/xdma_ddr.tcl | 6 +++--- 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/nitefury_pcie_xdma_ddr/dma_test.py b/nitefury_pcie_xdma_ddr/dma_test.py index 70920a7..6c5c7f6 100644 --- a/nitefury_pcie_xdma_ddr/dma_test.py +++ b/nitefury_pcie_xdma_ddr/dma_test.py @@ -3,10 +3,10 @@ import os import time ############################################## -def main(): +def Test(size=4096,addr=0): # Generate some data - TRANSFER_SIZE = 0x40000000 + TRANSFER_SIZE = size tx_data = bytearray(os.urandom(TRANSFER_SIZE)) # Open files @@ -15,7 +15,7 @@ def main(): # Send data to FPGA start = time.time() - os.pwrite(fd_h2c, tx_data, 0x80000000); + os.pwrite(fd_h2c, tx_data, addr); end = time.time() duration = end-start; @@ -25,7 +25,7 @@ def main(): # Receive data from FPGA start = time.time() - rx_data = os.pread(fd_c2h, TRANSFER_SIZE, 0x80000000); + rx_data = os.pread(fd_c2h, TRANSFER_SIZE, addr); end = time.time() duration = end-start; @@ -47,6 +47,8 @@ def main(): ############################################## if __name__ == '__main__': - main() + Test(8192,0x100000000) + Test(0x40000000,0x000000000) + Test(0x40000000,0x080000000) diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci index 3558fe0..7ad0df3 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci @@ -711,7 +711,7 @@ "M00_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M00_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M00_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "M01_A00_BASE_ADDR": [ { "value": "0x0000000100000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A00_BASE_ADDR": [ { "value": "0x0000000080000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M01_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M01_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M01_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], @@ -727,7 +727,7 @@ "M01_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M01_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M01_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "M02_A00_BASE_ADDR": [ { "value": "0x00000000C0000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A00_BASE_ADDR": [ { "value": "0x0000000100000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M02_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M02_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M02_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], diff --git a/nitefury_pcie_xdma_ddr/project/xdma_ddr.tcl b/nitefury_pcie_xdma_ddr/project/xdma_ddr.tcl index 4650293..3314c8d 100644 --- a/nitefury_pcie_xdma_ddr/project/xdma_ddr.tcl +++ b/nitefury_pcie_xdma_ddr/project/xdma_ddr.tcl @@ -4,7 +4,7 @@ set_property SOURCE_MGMT_MODE None [current_project] set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1] set_property PART xc7k480tffg1156-2L [current_project] -set_param general.maxThreads 16 +set_param general.maxThreads 4 # create_ip -name axi_interconnect -vendor xilinx.com -library ip -version 1.7 -module_name axi_interconnect_0 @@ -83,7 +83,7 @@ open_project xdma_ddr ##### PRESYNTH # set_property DESIGN_MODE GateLvl [current_fileset] reset_run synth_1 -launch_runs synth_1 -jobs 16 +launch_runs synth_1 -jobs 4 wait_on_run synth_1 #report_property [get_runs synth_1] if { [get_property STATUS [get_runs synth_1]] ne "synth_design Complete!" } { exit 1 } @@ -91,7 +91,7 @@ if { [get_property STATUS [get_runs synth_1]] ne "synth_design Complete!" } { ex ##### Place and Route reset_run impl_1 -launch_runs impl_1 -jobs 16 +launch_runs impl_1 -jobs 4 wait_on_run impl_1 #report_property [get_runs impl_1] # if { [get_property STATUS [get_runs impl_1]] ne "route_design Complete!" } { exit 1 }