diff --git a/nitefury_pcie_xdma_ddr/project/sources/Top.v b/nitefury_pcie_xdma_ddr/project/sources/Top.v index 1a777e1..38dc17a 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/Top.v +++ b/nitefury_pcie_xdma_ddr/project/sources/Top.v @@ -1,15 +1,15 @@ //Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022 -//Date : Mon May 12 00:32:06 2025 -//Host : deve running 64-bit Ubuntu 22.04.5 LTS +//Date : Wed May 14 00:03:48 2025 +//Host : colin-9700k running 64-bit Ubuntu 22.04.5 LTS //Command : generate_target Top.bd //Design : Top //Purpose : IP block netlist //-------------------------------------------------------------------------------- `timescale 1 ps / 1 ps -(* HW_HANDOFF = "Top.hwdef" *) (* core_generation_info = "Top,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Top,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=27,numReposBlks=20,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) +(* CORE_GENERATION_INFO = "Top,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Top,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=19,numReposBlks=14,numNonXlnxBlks=0,numHierBlks=5,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "Top.hwdef" *) module Top (C0_DDR3_0_addr, C0_DDR3_0_ba, @@ -51,52 +51,54 @@ module Top pcie_mgt_0_txn, pcie_mgt_0_txp, user_lnk_up_0); - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 ADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME C0_DDR3_0, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) output [14:0]C0_DDR3_0_addr; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 BA" *) output [2:0]C0_DDR3_0_ba; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CAS_N" *) output C0_DDR3_0_cas_n; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CK_N" *) output [0:0]C0_DDR3_0_ck_n; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CK_P" *) output [0:0]C0_DDR3_0_ck_p; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CKE" *) output [0:0]C0_DDR3_0_cke; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CS_N" *) output [0:0]C0_DDR3_0_cs_n; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 DQ" *) inout [71:0]C0_DDR3_0_dq; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 DQS_N" *) inout [8:0]C0_DDR3_0_dqs_n; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 DQS_P" *) inout [8:0]C0_DDR3_0_dqs_p; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 ODT" *) output [0:0]C0_DDR3_0_odt; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 RAS_N" *) output C0_DDR3_0_ras_n; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 RESET_N" *) output C0_DDR3_0_reset_n; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 WE_N" *) output C0_DDR3_0_we_n; - (* x_interface_info = "xilinx.com:interface:diff_clock:1.0 C0_SYS_CLK_0 CLK_N" *) (* x_interface_parameter = "XIL_INTERFACENAME C0_SYS_CLK_0, CAN_DEBUG false, FREQ_HZ 100000000" *) input C0_SYS_CLK_0_clk_n; - (* x_interface_info = "xilinx.com:interface:diff_clock:1.0 C0_SYS_CLK_0 CLK_P" *) input C0_SYS_CLK_0_clk_p; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 ADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME C1_DDR3_0, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) output [14:0]C1_DDR3_0_addr; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 BA" *) output [2:0]C1_DDR3_0_ba; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CAS_N" *) output C1_DDR3_0_cas_n; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CK_N" *) output [0:0]C1_DDR3_0_ck_n; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CK_P" *) output [0:0]C1_DDR3_0_ck_p; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CKE" *) output [0:0]C1_DDR3_0_cke; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CS_N" *) output [0:0]C1_DDR3_0_cs_n; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 DQ" *) inout [71:0]C1_DDR3_0_dq; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 DQS_N" *) inout [8:0]C1_DDR3_0_dqs_n; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 DQS_P" *) inout [8:0]C1_DDR3_0_dqs_p; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 ODT" *) output [0:0]C1_DDR3_0_odt; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 RAS_N" *) output C1_DDR3_0_ras_n; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 RESET_N" *) output C1_DDR3_0_reset_n; - (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 WE_N" *) output C1_DDR3_0_we_n; - (* x_interface_info = "xilinx.com:interface:diff_clock:1.0 C1_SYS_CLK_0 CLK_N" *) (* x_interface_parameter = "XIL_INTERFACENAME C1_SYS_CLK_0, CAN_DEBUG false, FREQ_HZ 100000000" *) input C1_SYS_CLK_0_clk_n; - (* x_interface_info = "xilinx.com:interface:diff_clock:1.0 C1_SYS_CLK_0 CLK_P" *) input C1_SYS_CLK_0_clk_p; - (* x_interface_info = "xilinx.com:signal:reset:1.0 RST.PCI_RESET RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RST.PCI_RESET, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input pci_reset; - (* x_interface_info = "xilinx.com:interface:diff_clock:1.0 pcie_clkin CLK_N" *) (* x_interface_parameter = "XIL_INTERFACENAME pcie_clkin, CAN_DEBUG false, FREQ_HZ 100000000" *) input [0:0]pcie_clkin_clk_n; - (* x_interface_info = "xilinx.com:interface:diff_clock:1.0 pcie_clkin CLK_P" *) input [0:0]pcie_clkin_clk_p; - (* x_interface_info = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 rxn" *) input [0:0]pcie_mgt_0_rxn; - (* x_interface_info = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 rxp" *) input [0:0]pcie_mgt_0_rxp; - (* x_interface_info = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 txn" *) output [0:0]pcie_mgt_0_txn; - (* x_interface_info = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 txp" *) output [0:0]pcie_mgt_0_txp; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME C0_DDR3_0, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) output [14:0]C0_DDR3_0_addr; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 BA" *) output [2:0]C0_DDR3_0_ba; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CAS_N" *) output C0_DDR3_0_cas_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CK_N" *) output [0:0]C0_DDR3_0_ck_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CK_P" *) output [0:0]C0_DDR3_0_ck_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CKE" *) output [0:0]C0_DDR3_0_cke; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CS_N" *) output [0:0]C0_DDR3_0_cs_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 DQ" *) inout [71:0]C0_DDR3_0_dq; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 DQS_N" *) inout [8:0]C0_DDR3_0_dqs_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 DQS_P" *) inout [8:0]C0_DDR3_0_dqs_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 ODT" *) output [0:0]C0_DDR3_0_odt; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 RAS_N" *) output C0_DDR3_0_ras_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 RESET_N" *) output C0_DDR3_0_reset_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 WE_N" *) output C0_DDR3_0_we_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 C0_SYS_CLK_0 CLK_N" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME C0_SYS_CLK_0, CAN_DEBUG false, FREQ_HZ 100000000" *) input C0_SYS_CLK_0_clk_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 C0_SYS_CLK_0 CLK_P" *) input C0_SYS_CLK_0_clk_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME C1_DDR3_0, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) output [14:0]C1_DDR3_0_addr; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 BA" *) output [2:0]C1_DDR3_0_ba; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CAS_N" *) output C1_DDR3_0_cas_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CK_N" *) output [0:0]C1_DDR3_0_ck_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CK_P" *) output [0:0]C1_DDR3_0_ck_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CKE" *) output [0:0]C1_DDR3_0_cke; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CS_N" *) output [0:0]C1_DDR3_0_cs_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 DQ" *) inout [71:0]C1_DDR3_0_dq; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 DQS_N" *) inout [8:0]C1_DDR3_0_dqs_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 DQS_P" *) inout [8:0]C1_DDR3_0_dqs_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 ODT" *) output [0:0]C1_DDR3_0_odt; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 RAS_N" *) output C1_DDR3_0_ras_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 RESET_N" *) output C1_DDR3_0_reset_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 WE_N" *) output C1_DDR3_0_we_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 C1_SYS_CLK_0 CLK_N" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME C1_SYS_CLK_0, CAN_DEBUG false, FREQ_HZ 100000000" *) input C1_SYS_CLK_0_clk_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 C1_SYS_CLK_0 CLK_P" *) input C1_SYS_CLK_0_clk_p; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.PCI_RESET RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.PCI_RESET, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input pci_reset; + (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 pcie_clkin CLK_N" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME pcie_clkin, CAN_DEBUG false, FREQ_HZ 100000000" *) input [0:0]pcie_clkin_clk_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 pcie_clkin CLK_P" *) input [0:0]pcie_clkin_clk_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 rxn" *) input [0:0]pcie_mgt_0_rxn; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 rxp" *) input [0:0]pcie_mgt_0_rxp; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 txn" *) output [0:0]pcie_mgt_0_txn; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 txp" *) output [0:0]pcie_mgt_0_txp; output user_lnk_up_0; wire C0_SYS_CLK_0_1_CLK_N; wire C0_SYS_CLK_0_1_CLK_P; wire C1_SYS_CLK_0_1_CLK_N; wire C1_SYS_CLK_0_1_CLK_P; - wire [7:0]M00_ARESETN_2; + wire M01_ACLK_1; + wire S00_ACLK_1; + wire S00_ARESETN_1; wire [63:0]S00_AXI_1_ARADDR; wire [1:0]S00_AXI_1_ARBURST; wire [3:0]S00_AXI_1_ARCACHE; @@ -104,7 +106,7 @@ module Top wire [7:0]S00_AXI_1_ARLEN; wire S00_AXI_1_ARLOCK; wire [2:0]S00_AXI_1_ARPROT; - wire S00_AXI_1_ARREADY; + wire [0:0]S00_AXI_1_ARREADY; wire [2:0]S00_AXI_1_ARSIZE; wire S00_AXI_1_ARVALID; wire [63:0]S00_AXI_1_AWADDR; @@ -114,50 +116,72 @@ module Top wire [7:0]S00_AXI_1_AWLEN; wire S00_AXI_1_AWLOCK; wire [2:0]S00_AXI_1_AWPROT; - wire S00_AXI_1_AWREADY; + wire [0:0]S00_AXI_1_AWREADY; wire [2:0]S00_AXI_1_AWSIZE; wire S00_AXI_1_AWVALID; wire [3:0]S00_AXI_1_BID; wire S00_AXI_1_BREADY; wire [1:0]S00_AXI_1_BRESP; - wire S00_AXI_1_BVALID; + wire [0:0]S00_AXI_1_BVALID; wire [63:0]S00_AXI_1_RDATA; wire [3:0]S00_AXI_1_RID; - wire S00_AXI_1_RLAST; + wire [0:0]S00_AXI_1_RLAST; wire S00_AXI_1_RREADY; wire [1:0]S00_AXI_1_RRESP; - wire S00_AXI_1_RVALID; + wire [0:0]S00_AXI_1_RVALID; wire [63:0]S00_AXI_1_WDATA; wire S00_AXI_1_WLAST; - wire S00_AXI_1_WREADY; + wire [0:0]S00_AXI_1_WREADY; wire [7:0]S00_AXI_1_WSTRB; wire S00_AXI_1_WVALID; wire [12:0]axi_bram_ctrl_0_BRAM_PORTA_ADDR; wire axi_bram_ctrl_0_BRAM_PORTA_CLK; - wire [31:0]axi_bram_ctrl_0_BRAM_PORTA_DIN; - wire [31:0]axi_bram_ctrl_0_BRAM_PORTA_DOUT; + wire [63:0]axi_bram_ctrl_0_BRAM_PORTA_DIN; + wire [63:0]axi_bram_ctrl_0_BRAM_PORTA_DOUT; wire axi_bram_ctrl_0_BRAM_PORTA_EN; wire axi_bram_ctrl_0_BRAM_PORTA_RST; - wire [3:0]axi_bram_ctrl_0_BRAM_PORTA_WE; - wire [31:0]axi_interconnect_0_M00_AXI_ARADDR; + wire [7:0]axi_bram_ctrl_0_BRAM_PORTA_WE; + wire [30:0]axi_interconnect_0_M00_AXI_ARADDR; + wire [1:0]axi_interconnect_0_M00_AXI_ARBURST; + wire [3:0]axi_interconnect_0_M00_AXI_ARCACHE; + wire [3:0]axi_interconnect_0_M00_AXI_ARID; + wire [7:0]axi_interconnect_0_M00_AXI_ARLEN; + wire axi_interconnect_0_M00_AXI_ARLOCK; + wire [2:0]axi_interconnect_0_M00_AXI_ARPROT; + wire [3:0]axi_interconnect_0_M00_AXI_ARQOS; wire axi_interconnect_0_M00_AXI_ARREADY; + wire [2:0]axi_interconnect_0_M00_AXI_ARSIZE; wire axi_interconnect_0_M00_AXI_ARVALID; - wire [31:0]axi_interconnect_0_M00_AXI_AWADDR; + wire [30:0]axi_interconnect_0_M00_AXI_AWADDR; + wire [1:0]axi_interconnect_0_M00_AXI_AWBURST; + wire [3:0]axi_interconnect_0_M00_AXI_AWCACHE; + wire [3:0]axi_interconnect_0_M00_AXI_AWID; + wire [7:0]axi_interconnect_0_M00_AXI_AWLEN; + wire axi_interconnect_0_M00_AXI_AWLOCK; + wire [2:0]axi_interconnect_0_M00_AXI_AWPROT; + wire [3:0]axi_interconnect_0_M00_AXI_AWQOS; wire axi_interconnect_0_M00_AXI_AWREADY; + wire [2:0]axi_interconnect_0_M00_AXI_AWSIZE; wire axi_interconnect_0_M00_AXI_AWVALID; + wire [3:0]axi_interconnect_0_M00_AXI_BID; wire axi_interconnect_0_M00_AXI_BREADY; wire [1:0]axi_interconnect_0_M00_AXI_BRESP; wire axi_interconnect_0_M00_AXI_BVALID; - wire [31:0]axi_interconnect_0_M00_AXI_RDATA; + wire [63:0]axi_interconnect_0_M00_AXI_RDATA; + wire [3:0]axi_interconnect_0_M00_AXI_RID; + wire axi_interconnect_0_M00_AXI_RLAST; wire axi_interconnect_0_M00_AXI_RREADY; wire [1:0]axi_interconnect_0_M00_AXI_RRESP; wire axi_interconnect_0_M00_AXI_RVALID; - wire [31:0]axi_interconnect_0_M00_AXI_WDATA; + wire [63:0]axi_interconnect_0_M00_AXI_WDATA; + wire axi_interconnect_0_M00_AXI_WLAST; wire axi_interconnect_0_M00_AXI_WREADY; + wire [7:0]axi_interconnect_0_M00_AXI_WSTRB; wire axi_interconnect_0_M00_AXI_WVALID; wire [30:0]axi_interconnect_0_M01_AXI_ARADDR; wire [1:0]axi_interconnect_0_M01_AXI_ARBURST; wire [3:0]axi_interconnect_0_M01_AXI_ARCACHE; + wire [3:0]axi_interconnect_0_M01_AXI_ARID; wire [7:0]axi_interconnect_0_M01_AXI_ARLEN; wire axi_interconnect_0_M01_AXI_ARLOCK; wire [2:0]axi_interconnect_0_M01_AXI_ARPROT; @@ -168,6 +192,7 @@ module Top wire [30:0]axi_interconnect_0_M01_AXI_AWADDR; wire [1:0]axi_interconnect_0_M01_AXI_AWBURST; wire [3:0]axi_interconnect_0_M01_AXI_AWCACHE; + wire [3:0]axi_interconnect_0_M01_AXI_AWID; wire [7:0]axi_interconnect_0_M01_AXI_AWLEN; wire axi_interconnect_0_M01_AXI_AWLOCK; wire [2:0]axi_interconnect_0_M01_AXI_AWPROT; @@ -175,99 +200,88 @@ module Top wire axi_interconnect_0_M01_AXI_AWREADY; wire [2:0]axi_interconnect_0_M01_AXI_AWSIZE; wire axi_interconnect_0_M01_AXI_AWVALID; + wire [3:0]axi_interconnect_0_M01_AXI_BID; wire axi_interconnect_0_M01_AXI_BREADY; wire [1:0]axi_interconnect_0_M01_AXI_BRESP; wire axi_interconnect_0_M01_AXI_BVALID; - wire [511:0]axi_interconnect_0_M01_AXI_RDATA; + wire [63:0]axi_interconnect_0_M01_AXI_RDATA; + wire [3:0]axi_interconnect_0_M01_AXI_RID; wire axi_interconnect_0_M01_AXI_RLAST; wire axi_interconnect_0_M01_AXI_RREADY; wire [1:0]axi_interconnect_0_M01_AXI_RRESP; wire axi_interconnect_0_M01_AXI_RVALID; - wire [511:0]axi_interconnect_0_M01_AXI_WDATA; + wire [63:0]axi_interconnect_0_M01_AXI_WDATA; wire axi_interconnect_0_M01_AXI_WLAST; wire axi_interconnect_0_M01_AXI_WREADY; - wire [63:0]axi_interconnect_0_M01_AXI_WSTRB; + wire [7:0]axi_interconnect_0_M01_AXI_WSTRB; wire axi_interconnect_0_M01_AXI_WVALID; - wire [31:0]axi_interconnect_0_M02_AXI_ARADDR; + wire [63:0]axi_interconnect_0_M02_AXI_ARADDR; + wire [1:0]axi_interconnect_0_M02_AXI_ARBURST; + wire [3:0]axi_interconnect_0_M02_AXI_ARCACHE; + wire [3:0]axi_interconnect_0_M02_AXI_ARID; + wire [7:0]axi_interconnect_0_M02_AXI_ARLEN; + wire axi_interconnect_0_M02_AXI_ARLOCK; + wire [2:0]axi_interconnect_0_M02_AXI_ARPROT; wire axi_interconnect_0_M02_AXI_ARREADY; + wire [2:0]axi_interconnect_0_M02_AXI_ARSIZE; wire axi_interconnect_0_M02_AXI_ARVALID; - wire [31:0]axi_interconnect_0_M02_AXI_AWADDR; + wire [63:0]axi_interconnect_0_M02_AXI_AWADDR; + wire [1:0]axi_interconnect_0_M02_AXI_AWBURST; + wire [3:0]axi_interconnect_0_M02_AXI_AWCACHE; + wire [3:0]axi_interconnect_0_M02_AXI_AWID; + wire [7:0]axi_interconnect_0_M02_AXI_AWLEN; + wire axi_interconnect_0_M02_AXI_AWLOCK; + wire [2:0]axi_interconnect_0_M02_AXI_AWPROT; wire axi_interconnect_0_M02_AXI_AWREADY; + wire [2:0]axi_interconnect_0_M02_AXI_AWSIZE; wire axi_interconnect_0_M02_AXI_AWVALID; + wire [3:0]axi_interconnect_0_M02_AXI_BID; wire axi_interconnect_0_M02_AXI_BREADY; wire [1:0]axi_interconnect_0_M02_AXI_BRESP; wire axi_interconnect_0_M02_AXI_BVALID; - wire [31:0]axi_interconnect_0_M02_AXI_RDATA; + wire [63:0]axi_interconnect_0_M02_AXI_RDATA; + wire [3:0]axi_interconnect_0_M02_AXI_RID; + wire axi_interconnect_0_M02_AXI_RLAST; wire axi_interconnect_0_M02_AXI_RREADY; wire [1:0]axi_interconnect_0_M02_AXI_RRESP; wire axi_interconnect_0_M02_AXI_RVALID; - wire [31:0]axi_interconnect_0_M02_AXI_WDATA; + wire [63:0]axi_interconnect_0_M02_AXI_WDATA; + wire axi_interconnect_0_M02_AXI_WLAST; wire axi_interconnect_0_M02_AXI_WREADY; + wire [7:0]axi_interconnect_0_M02_AXI_WSTRB; wire axi_interconnect_0_M02_AXI_WVALID; - wire [30:0]axi_interconnect_0_M03_AXI_ARADDR; - wire [1:0]axi_interconnect_0_M03_AXI_ARBURST; - wire [3:0]axi_interconnect_0_M03_AXI_ARCACHE; - wire [7:0]axi_interconnect_0_M03_AXI_ARLEN; - wire axi_interconnect_0_M03_AXI_ARLOCK; - wire [2:0]axi_interconnect_0_M03_AXI_ARPROT; - wire [3:0]axi_interconnect_0_M03_AXI_ARQOS; - wire axi_interconnect_0_M03_AXI_ARREADY; - wire [2:0]axi_interconnect_0_M03_AXI_ARSIZE; - wire axi_interconnect_0_M03_AXI_ARVALID; - wire [30:0]axi_interconnect_0_M03_AXI_AWADDR; - wire [1:0]axi_interconnect_0_M03_AXI_AWBURST; - wire [3:0]axi_interconnect_0_M03_AXI_AWCACHE; - wire [7:0]axi_interconnect_0_M03_AXI_AWLEN; - wire axi_interconnect_0_M03_AXI_AWLOCK; - wire [2:0]axi_interconnect_0_M03_AXI_AWPROT; - wire [3:0]axi_interconnect_0_M03_AXI_AWQOS; - wire axi_interconnect_0_M03_AXI_AWREADY; - wire [2:0]axi_interconnect_0_M03_AXI_AWSIZE; - wire axi_interconnect_0_M03_AXI_AWVALID; - wire axi_interconnect_0_M03_AXI_BREADY; - wire [1:0]axi_interconnect_0_M03_AXI_BRESP; - wire axi_interconnect_0_M03_AXI_BVALID; - wire [511:0]axi_interconnect_0_M03_AXI_RDATA; - wire axi_interconnect_0_M03_AXI_RLAST; - wire axi_interconnect_0_M03_AXI_RREADY; - wire [1:0]axi_interconnect_0_M03_AXI_RRESP; - wire axi_interconnect_0_M03_AXI_RVALID; - wire [511:0]axi_interconnect_0_M03_AXI_WDATA; - wire axi_interconnect_0_M03_AXI_WLAST; - wire axi_interconnect_0_M03_AXI_WREADY; - wire [63:0]axi_interconnect_0_M03_AXI_WSTRB; - wire axi_interconnect_0_M03_AXI_WVALID; - wire [12:0]axi_interconnect_0_M04_AXI_ARADDR; - wire [1:0]axi_interconnect_0_M04_AXI_ARBURST; - wire [3:0]axi_interconnect_0_M04_AXI_ARCACHE; - wire [7:0]axi_interconnect_0_M04_AXI_ARLEN; - wire axi_interconnect_0_M04_AXI_ARLOCK; - wire [2:0]axi_interconnect_0_M04_AXI_ARPROT; - wire axi_interconnect_0_M04_AXI_ARREADY; - wire [2:0]axi_interconnect_0_M04_AXI_ARSIZE; - wire axi_interconnect_0_M04_AXI_ARVALID; - wire [12:0]axi_interconnect_0_M04_AXI_AWADDR; - wire [1:0]axi_interconnect_0_M04_AXI_AWBURST; - wire [3:0]axi_interconnect_0_M04_AXI_AWCACHE; - wire [7:0]axi_interconnect_0_M04_AXI_AWLEN; - wire axi_interconnect_0_M04_AXI_AWLOCK; - wire [2:0]axi_interconnect_0_M04_AXI_AWPROT; - wire axi_interconnect_0_M04_AXI_AWREADY; - wire [2:0]axi_interconnect_0_M04_AXI_AWSIZE; - wire axi_interconnect_0_M04_AXI_AWVALID; - wire axi_interconnect_0_M04_AXI_BREADY; - wire [1:0]axi_interconnect_0_M04_AXI_BRESP; - wire axi_interconnect_0_M04_AXI_BVALID; - wire [31:0]axi_interconnect_0_M04_AXI_RDATA; - wire axi_interconnect_0_M04_AXI_RLAST; - wire axi_interconnect_0_M04_AXI_RREADY; - wire [1:0]axi_interconnect_0_M04_AXI_RRESP; - wire axi_interconnect_0_M04_AXI_RVALID; - wire [31:0]axi_interconnect_0_M04_AXI_WDATA; - wire axi_interconnect_0_M04_AXI_WLAST; - wire axi_interconnect_0_M04_AXI_WREADY; - wire [3:0]axi_interconnect_0_M04_AXI_WSTRB; - wire axi_interconnect_0_M04_AXI_WVALID; + wire [63:0]jtag_axi_0_M_AXI_ARADDR; + wire jtag_axi_0_M_AXI_ARREADY; + wire jtag_axi_0_M_AXI_ARVALID; + wire [63:0]jtag_axi_0_M_AXI_AWADDR; + wire jtag_axi_0_M_AXI_AWREADY; + wire jtag_axi_0_M_AXI_AWVALID; + wire jtag_axi_0_M_AXI_BREADY; + wire [1:0]jtag_axi_0_M_AXI_BRESP; + wire jtag_axi_0_M_AXI_BVALID; + wire [31:0]jtag_axi_0_M_AXI_RDATA; + wire jtag_axi_0_M_AXI_RREADY; + wire [1:0]jtag_axi_0_M_AXI_RRESP; + wire jtag_axi_0_M_AXI_RVALID; + wire [31:0]jtag_axi_0_M_AXI_WDATA; + wire jtag_axi_0_M_AXI_WREADY; + wire jtag_axi_0_M_AXI_WVALID; + wire [63:0]jtag_axi_1_M_AXI_ARADDR; + wire jtag_axi_1_M_AXI_ARREADY; + wire jtag_axi_1_M_AXI_ARVALID; + wire [63:0]jtag_axi_1_M_AXI_AWADDR; + wire jtag_axi_1_M_AXI_AWREADY; + wire jtag_axi_1_M_AXI_AWVALID; + wire jtag_axi_1_M_AXI_BREADY; + wire [1:0]jtag_axi_1_M_AXI_BRESP; + wire jtag_axi_1_M_AXI_BVALID; + wire [31:0]jtag_axi_1_M_AXI_RDATA; + wire jtag_axi_1_M_AXI_RREADY; + wire [1:0]jtag_axi_1_M_AXI_RRESP; + wire jtag_axi_1_M_AXI_RVALID; + wire [31:0]jtag_axi_1_M_AXI_WDATA; + wire jtag_axi_1_M_AXI_WREADY; + wire jtag_axi_1_M_AXI_WVALID; wire [14:0]mig_7series_1_C0_DDR3_ADDR; wire [2:0]mig_7series_1_C0_DDR3_BA; wire mig_7series_1_C0_DDR3_CAS_N; @@ -296,17 +310,15 @@ module Top wire mig_7series_1_C1_DDR3_RAS_N; wire mig_7series_1_C1_DDR3_RESET_N; wire mig_7series_1_C1_DDR3_WE_N; + wire mig_7series_1_c0_ui_clk; wire mig_7series_1_c0_ui_clk_sync_rst; - wire mig_7series_1_c1_ui_clk; wire mig_7series_1_c1_ui_clk_sync_rst; - wire mig_7series_1_ui_clk; wire pci_reset_1; wire [0:0]pcie_clkin_1_CLK_N; wire [0:0]pcie_clkin_1_CLK_P; wire [0:0]util_ds_buf_0_IBUF_OUT; - wire [7:0]util_vector_logic_2_Res; - wire xdma_1_axi_aclk; - wire xdma_1_axi_aresetn; + wire [7:0]util_vector_logic_0_Res; + wire [7:0]util_vector_logic_1_Res; wire [0:0]xdma_1_pcie_mgt_rxn; wire [0:0]xdma_1_pcie_mgt_rxp; wire [0:0]xdma_1_pcie_mgt_txn; @@ -357,65 +369,91 @@ module Top .bram_rst_a(axi_bram_ctrl_0_BRAM_PORTA_RST), .bram_we_a(axi_bram_ctrl_0_BRAM_PORTA_WE), .bram_wrdata_a(axi_bram_ctrl_0_BRAM_PORTA_DIN), - .s_axi_aclk(xdma_1_axi_aclk), - .s_axi_araddr(axi_interconnect_0_M04_AXI_ARADDR), - .s_axi_arburst(axi_interconnect_0_M04_AXI_ARBURST), - .s_axi_arcache(axi_interconnect_0_M04_AXI_ARCACHE), - .s_axi_aresetn(xdma_1_axi_aresetn), - .s_axi_arlen(axi_interconnect_0_M04_AXI_ARLEN), - .s_axi_arlock(axi_interconnect_0_M04_AXI_ARLOCK), - .s_axi_arprot(axi_interconnect_0_M04_AXI_ARPROT), - .s_axi_arready(axi_interconnect_0_M04_AXI_ARREADY), - .s_axi_arsize(axi_interconnect_0_M04_AXI_ARSIZE), - .s_axi_arvalid(axi_interconnect_0_M04_AXI_ARVALID), - .s_axi_awaddr(axi_interconnect_0_M04_AXI_AWADDR), - .s_axi_awburst(axi_interconnect_0_M04_AXI_AWBURST), - .s_axi_awcache(axi_interconnect_0_M04_AXI_AWCACHE), - .s_axi_awlen(axi_interconnect_0_M04_AXI_AWLEN), - .s_axi_awlock(axi_interconnect_0_M04_AXI_AWLOCK), - .s_axi_awprot(axi_interconnect_0_M04_AXI_AWPROT), - .s_axi_awready(axi_interconnect_0_M04_AXI_AWREADY), - .s_axi_awsize(axi_interconnect_0_M04_AXI_AWSIZE), - .s_axi_awvalid(axi_interconnect_0_M04_AXI_AWVALID), - .s_axi_bready(axi_interconnect_0_M04_AXI_BREADY), - .s_axi_bresp(axi_interconnect_0_M04_AXI_BRESP), - .s_axi_bvalid(axi_interconnect_0_M04_AXI_BVALID), - .s_axi_rdata(axi_interconnect_0_M04_AXI_RDATA), - .s_axi_rlast(axi_interconnect_0_M04_AXI_RLAST), - .s_axi_rready(axi_interconnect_0_M04_AXI_RREADY), - .s_axi_rresp(axi_interconnect_0_M04_AXI_RRESP), - .s_axi_rvalid(axi_interconnect_0_M04_AXI_RVALID), - .s_axi_wdata(axi_interconnect_0_M04_AXI_WDATA), - .s_axi_wlast(axi_interconnect_0_M04_AXI_WLAST), - .s_axi_wready(axi_interconnect_0_M04_AXI_WREADY), - .s_axi_wstrb(axi_interconnect_0_M04_AXI_WSTRB), - .s_axi_wvalid(axi_interconnect_0_M04_AXI_WVALID)); + .s_axi_aclk(S00_ACLK_1), + .s_axi_araddr(axi_interconnect_0_M02_AXI_ARADDR[12:0]), + .s_axi_arburst(axi_interconnect_0_M02_AXI_ARBURST), + .s_axi_arcache(axi_interconnect_0_M02_AXI_ARCACHE), + .s_axi_aresetn(S00_ARESETN_1), + .s_axi_arid(axi_interconnect_0_M02_AXI_ARID), + .s_axi_arlen(axi_interconnect_0_M02_AXI_ARLEN), + .s_axi_arlock(axi_interconnect_0_M02_AXI_ARLOCK), + .s_axi_arprot(axi_interconnect_0_M02_AXI_ARPROT), + .s_axi_arready(axi_interconnect_0_M02_AXI_ARREADY), + .s_axi_arsize(axi_interconnect_0_M02_AXI_ARSIZE), + .s_axi_arvalid(axi_interconnect_0_M02_AXI_ARVALID), + .s_axi_awaddr(axi_interconnect_0_M02_AXI_AWADDR[12:0]), + .s_axi_awburst(axi_interconnect_0_M02_AXI_AWBURST), + .s_axi_awcache(axi_interconnect_0_M02_AXI_AWCACHE), + .s_axi_awid(axi_interconnect_0_M02_AXI_AWID), + .s_axi_awlen(axi_interconnect_0_M02_AXI_AWLEN), + .s_axi_awlock(axi_interconnect_0_M02_AXI_AWLOCK), + .s_axi_awprot(axi_interconnect_0_M02_AXI_AWPROT), + .s_axi_awready(axi_interconnect_0_M02_AXI_AWREADY), + .s_axi_awsize(axi_interconnect_0_M02_AXI_AWSIZE), + .s_axi_awvalid(axi_interconnect_0_M02_AXI_AWVALID), + .s_axi_bid(axi_interconnect_0_M02_AXI_BID), + .s_axi_bready(axi_interconnect_0_M02_AXI_BREADY), + .s_axi_bresp(axi_interconnect_0_M02_AXI_BRESP), + .s_axi_bvalid(axi_interconnect_0_M02_AXI_BVALID), + .s_axi_rdata(axi_interconnect_0_M02_AXI_RDATA), + .s_axi_rid(axi_interconnect_0_M02_AXI_RID), + .s_axi_rlast(axi_interconnect_0_M02_AXI_RLAST), + .s_axi_rready(axi_interconnect_0_M02_AXI_RREADY), + .s_axi_rresp(axi_interconnect_0_M02_AXI_RRESP), + .s_axi_rvalid(axi_interconnect_0_M02_AXI_RVALID), + .s_axi_wdata(axi_interconnect_0_M02_AXI_WDATA), + .s_axi_wlast(axi_interconnect_0_M02_AXI_WLAST), + .s_axi_wready(axi_interconnect_0_M02_AXI_WREADY), + .s_axi_wstrb(axi_interconnect_0_M02_AXI_WSTRB), + .s_axi_wvalid(axi_interconnect_0_M02_AXI_WVALID)); Top_axi_interconnect_0_0 axi_interconnect_0 - (.ACLK(xdma_1_axi_aclk), - .ARESETN(xdma_1_axi_aresetn), - .M00_ACLK(mig_7series_1_ui_clk), - .M00_ARESETN(M00_ARESETN_2), + (.ACLK(S00_ACLK_1), + .ARESETN(S00_ARESETN_1), + .M00_ACLK(mig_7series_1_c0_ui_clk), + .M00_ARESETN(util_vector_logic_0_Res), .M00_AXI_araddr(axi_interconnect_0_M00_AXI_ARADDR), + .M00_AXI_arburst(axi_interconnect_0_M00_AXI_ARBURST), + .M00_AXI_arcache(axi_interconnect_0_M00_AXI_ARCACHE), + .M00_AXI_arid(axi_interconnect_0_M00_AXI_ARID), + .M00_AXI_arlen(axi_interconnect_0_M00_AXI_ARLEN), + .M00_AXI_arlock(axi_interconnect_0_M00_AXI_ARLOCK), + .M00_AXI_arprot(axi_interconnect_0_M00_AXI_ARPROT), + .M00_AXI_arqos(axi_interconnect_0_M00_AXI_ARQOS), .M00_AXI_arready(axi_interconnect_0_M00_AXI_ARREADY), + .M00_AXI_arsize(axi_interconnect_0_M00_AXI_ARSIZE), .M00_AXI_arvalid(axi_interconnect_0_M00_AXI_ARVALID), .M00_AXI_awaddr(axi_interconnect_0_M00_AXI_AWADDR), + .M00_AXI_awburst(axi_interconnect_0_M00_AXI_AWBURST), + .M00_AXI_awcache(axi_interconnect_0_M00_AXI_AWCACHE), + .M00_AXI_awid(axi_interconnect_0_M00_AXI_AWID), + .M00_AXI_awlen(axi_interconnect_0_M00_AXI_AWLEN), + .M00_AXI_awlock(axi_interconnect_0_M00_AXI_AWLOCK), + .M00_AXI_awprot(axi_interconnect_0_M00_AXI_AWPROT), + .M00_AXI_awqos(axi_interconnect_0_M00_AXI_AWQOS), .M00_AXI_awready(axi_interconnect_0_M00_AXI_AWREADY), + .M00_AXI_awsize(axi_interconnect_0_M00_AXI_AWSIZE), .M00_AXI_awvalid(axi_interconnect_0_M00_AXI_AWVALID), + .M00_AXI_bid(axi_interconnect_0_M00_AXI_BID), .M00_AXI_bready(axi_interconnect_0_M00_AXI_BREADY), .M00_AXI_bresp(axi_interconnect_0_M00_AXI_BRESP), .M00_AXI_bvalid(axi_interconnect_0_M00_AXI_BVALID), .M00_AXI_rdata(axi_interconnect_0_M00_AXI_RDATA), + .M00_AXI_rid(axi_interconnect_0_M00_AXI_RID), + .M00_AXI_rlast(axi_interconnect_0_M00_AXI_RLAST), .M00_AXI_rready(axi_interconnect_0_M00_AXI_RREADY), .M00_AXI_rresp(axi_interconnect_0_M00_AXI_RRESP), .M00_AXI_rvalid(axi_interconnect_0_M00_AXI_RVALID), .M00_AXI_wdata(axi_interconnect_0_M00_AXI_WDATA), + .M00_AXI_wlast(axi_interconnect_0_M00_AXI_WLAST), .M00_AXI_wready(axi_interconnect_0_M00_AXI_WREADY), + .M00_AXI_wstrb(axi_interconnect_0_M00_AXI_WSTRB), .M00_AXI_wvalid(axi_interconnect_0_M00_AXI_WVALID), - .M01_ACLK(mig_7series_1_ui_clk), - .M01_ARESETN(M00_ARESETN_2), + .M01_ACLK(M01_ACLK_1), + .M01_ARESETN(util_vector_logic_1_Res), .M01_AXI_araddr(axi_interconnect_0_M01_AXI_ARADDR), .M01_AXI_arburst(axi_interconnect_0_M01_AXI_ARBURST), .M01_AXI_arcache(axi_interconnect_0_M01_AXI_ARCACHE), + .M01_AXI_arid(axi_interconnect_0_M01_AXI_ARID), .M01_AXI_arlen(axi_interconnect_0_M01_AXI_ARLEN), .M01_AXI_arlock(axi_interconnect_0_M01_AXI_ARLOCK), .M01_AXI_arprot(axi_interconnect_0_M01_AXI_ARPROT), @@ -426,6 +464,7 @@ module Top .M01_AXI_awaddr(axi_interconnect_0_M01_AXI_AWADDR), .M01_AXI_awburst(axi_interconnect_0_M01_AXI_AWBURST), .M01_AXI_awcache(axi_interconnect_0_M01_AXI_AWCACHE), + .M01_AXI_awid(axi_interconnect_0_M01_AXI_AWID), .M01_AXI_awlen(axi_interconnect_0_M01_AXI_AWLEN), .M01_AXI_awlock(axi_interconnect_0_M01_AXI_AWLOCK), .M01_AXI_awprot(axi_interconnect_0_M01_AXI_AWPROT), @@ -433,10 +472,12 @@ module Top .M01_AXI_awready(axi_interconnect_0_M01_AXI_AWREADY), .M01_AXI_awsize(axi_interconnect_0_M01_AXI_AWSIZE), .M01_AXI_awvalid(axi_interconnect_0_M01_AXI_AWVALID), + .M01_AXI_bid(axi_interconnect_0_M01_AXI_BID), .M01_AXI_bready(axi_interconnect_0_M01_AXI_BREADY), .M01_AXI_bresp(axi_interconnect_0_M01_AXI_BRESP), .M01_AXI_bvalid(axi_interconnect_0_M01_AXI_BVALID), .M01_AXI_rdata(axi_interconnect_0_M01_AXI_RDATA), + .M01_AXI_rid(axi_interconnect_0_M01_AXI_RID), .M01_AXI_rlast(axi_interconnect_0_M01_AXI_RLAST), .M01_AXI_rready(axi_interconnect_0_M01_AXI_RREADY), .M01_AXI_rresp(axi_interconnect_0_M01_AXI_RRESP), @@ -446,94 +487,45 @@ module Top .M01_AXI_wready(axi_interconnect_0_M01_AXI_WREADY), .M01_AXI_wstrb(axi_interconnect_0_M01_AXI_WSTRB), .M01_AXI_wvalid(axi_interconnect_0_M01_AXI_WVALID), - .M02_ACLK(mig_7series_1_c1_ui_clk), - .M02_ARESETN(util_vector_logic_2_Res), + .M02_ACLK(S00_ACLK_1), + .M02_ARESETN({S00_ARESETN_1,S00_ARESETN_1,S00_ARESETN_1,S00_ARESETN_1,S00_ARESETN_1,S00_ARESETN_1,S00_ARESETN_1,S00_ARESETN_1}), .M02_AXI_araddr(axi_interconnect_0_M02_AXI_ARADDR), + .M02_AXI_arburst(axi_interconnect_0_M02_AXI_ARBURST), + .M02_AXI_arcache(axi_interconnect_0_M02_AXI_ARCACHE), + .M02_AXI_arid(axi_interconnect_0_M02_AXI_ARID), + .M02_AXI_arlen(axi_interconnect_0_M02_AXI_ARLEN), + .M02_AXI_arlock(axi_interconnect_0_M02_AXI_ARLOCK), + .M02_AXI_arprot(axi_interconnect_0_M02_AXI_ARPROT), .M02_AXI_arready(axi_interconnect_0_M02_AXI_ARREADY), + .M02_AXI_arsize(axi_interconnect_0_M02_AXI_ARSIZE), .M02_AXI_arvalid(axi_interconnect_0_M02_AXI_ARVALID), .M02_AXI_awaddr(axi_interconnect_0_M02_AXI_AWADDR), + .M02_AXI_awburst(axi_interconnect_0_M02_AXI_AWBURST), + .M02_AXI_awcache(axi_interconnect_0_M02_AXI_AWCACHE), + .M02_AXI_awid(axi_interconnect_0_M02_AXI_AWID), + .M02_AXI_awlen(axi_interconnect_0_M02_AXI_AWLEN), + .M02_AXI_awlock(axi_interconnect_0_M02_AXI_AWLOCK), + .M02_AXI_awprot(axi_interconnect_0_M02_AXI_AWPROT), .M02_AXI_awready(axi_interconnect_0_M02_AXI_AWREADY), + .M02_AXI_awsize(axi_interconnect_0_M02_AXI_AWSIZE), .M02_AXI_awvalid(axi_interconnect_0_M02_AXI_AWVALID), + .M02_AXI_bid(axi_interconnect_0_M02_AXI_BID), .M02_AXI_bready(axi_interconnect_0_M02_AXI_BREADY), .M02_AXI_bresp(axi_interconnect_0_M02_AXI_BRESP), .M02_AXI_bvalid(axi_interconnect_0_M02_AXI_BVALID), .M02_AXI_rdata(axi_interconnect_0_M02_AXI_RDATA), + .M02_AXI_rid(axi_interconnect_0_M02_AXI_RID), + .M02_AXI_rlast(axi_interconnect_0_M02_AXI_RLAST), .M02_AXI_rready(axi_interconnect_0_M02_AXI_RREADY), .M02_AXI_rresp(axi_interconnect_0_M02_AXI_RRESP), .M02_AXI_rvalid(axi_interconnect_0_M02_AXI_RVALID), .M02_AXI_wdata(axi_interconnect_0_M02_AXI_WDATA), + .M02_AXI_wlast(axi_interconnect_0_M02_AXI_WLAST), .M02_AXI_wready(axi_interconnect_0_M02_AXI_WREADY), + .M02_AXI_wstrb(axi_interconnect_0_M02_AXI_WSTRB), .M02_AXI_wvalid(axi_interconnect_0_M02_AXI_WVALID), - .M03_ACLK(mig_7series_1_c1_ui_clk), - .M03_ARESETN(util_vector_logic_2_Res), - .M03_AXI_araddr(axi_interconnect_0_M03_AXI_ARADDR), - .M03_AXI_arburst(axi_interconnect_0_M03_AXI_ARBURST), - .M03_AXI_arcache(axi_interconnect_0_M03_AXI_ARCACHE), - .M03_AXI_arlen(axi_interconnect_0_M03_AXI_ARLEN), - .M03_AXI_arlock(axi_interconnect_0_M03_AXI_ARLOCK), - .M03_AXI_arprot(axi_interconnect_0_M03_AXI_ARPROT), - .M03_AXI_arqos(axi_interconnect_0_M03_AXI_ARQOS), - .M03_AXI_arready(axi_interconnect_0_M03_AXI_ARREADY), - .M03_AXI_arsize(axi_interconnect_0_M03_AXI_ARSIZE), - .M03_AXI_arvalid(axi_interconnect_0_M03_AXI_ARVALID), - .M03_AXI_awaddr(axi_interconnect_0_M03_AXI_AWADDR), - .M03_AXI_awburst(axi_interconnect_0_M03_AXI_AWBURST), - .M03_AXI_awcache(axi_interconnect_0_M03_AXI_AWCACHE), - .M03_AXI_awlen(axi_interconnect_0_M03_AXI_AWLEN), - .M03_AXI_awlock(axi_interconnect_0_M03_AXI_AWLOCK), - .M03_AXI_awprot(axi_interconnect_0_M03_AXI_AWPROT), - .M03_AXI_awqos(axi_interconnect_0_M03_AXI_AWQOS), - .M03_AXI_awready(axi_interconnect_0_M03_AXI_AWREADY), - .M03_AXI_awsize(axi_interconnect_0_M03_AXI_AWSIZE), - .M03_AXI_awvalid(axi_interconnect_0_M03_AXI_AWVALID), - .M03_AXI_bready(axi_interconnect_0_M03_AXI_BREADY), - .M03_AXI_bresp(axi_interconnect_0_M03_AXI_BRESP), - .M03_AXI_bvalid(axi_interconnect_0_M03_AXI_BVALID), - .M03_AXI_rdata(axi_interconnect_0_M03_AXI_RDATA), - .M03_AXI_rlast(axi_interconnect_0_M03_AXI_RLAST), - .M03_AXI_rready(axi_interconnect_0_M03_AXI_RREADY), - .M03_AXI_rresp(axi_interconnect_0_M03_AXI_RRESP), - .M03_AXI_rvalid(axi_interconnect_0_M03_AXI_RVALID), - .M03_AXI_wdata(axi_interconnect_0_M03_AXI_WDATA), - .M03_AXI_wlast(axi_interconnect_0_M03_AXI_WLAST), - .M03_AXI_wready(axi_interconnect_0_M03_AXI_WREADY), - .M03_AXI_wstrb(axi_interconnect_0_M03_AXI_WSTRB), - .M03_AXI_wvalid(axi_interconnect_0_M03_AXI_WVALID), - .M04_ACLK(xdma_1_axi_aclk), - .M04_ARESETN(xdma_1_axi_aresetn), - .M04_AXI_araddr(axi_interconnect_0_M04_AXI_ARADDR), - .M04_AXI_arburst(axi_interconnect_0_M04_AXI_ARBURST), - .M04_AXI_arcache(axi_interconnect_0_M04_AXI_ARCACHE), - .M04_AXI_arlen(axi_interconnect_0_M04_AXI_ARLEN), - .M04_AXI_arlock(axi_interconnect_0_M04_AXI_ARLOCK), - .M04_AXI_arprot(axi_interconnect_0_M04_AXI_ARPROT), - .M04_AXI_arready(axi_interconnect_0_M04_AXI_ARREADY), - .M04_AXI_arsize(axi_interconnect_0_M04_AXI_ARSIZE), - .M04_AXI_arvalid(axi_interconnect_0_M04_AXI_ARVALID), - .M04_AXI_awaddr(axi_interconnect_0_M04_AXI_AWADDR), - .M04_AXI_awburst(axi_interconnect_0_M04_AXI_AWBURST), - .M04_AXI_awcache(axi_interconnect_0_M04_AXI_AWCACHE), - .M04_AXI_awlen(axi_interconnect_0_M04_AXI_AWLEN), - .M04_AXI_awlock(axi_interconnect_0_M04_AXI_AWLOCK), - .M04_AXI_awprot(axi_interconnect_0_M04_AXI_AWPROT), - .M04_AXI_awready(axi_interconnect_0_M04_AXI_AWREADY), - .M04_AXI_awsize(axi_interconnect_0_M04_AXI_AWSIZE), - .M04_AXI_awvalid(axi_interconnect_0_M04_AXI_AWVALID), - .M04_AXI_bready(axi_interconnect_0_M04_AXI_BREADY), - .M04_AXI_bresp(axi_interconnect_0_M04_AXI_BRESP), - .M04_AXI_bvalid(axi_interconnect_0_M04_AXI_BVALID), - .M04_AXI_rdata(axi_interconnect_0_M04_AXI_RDATA), - .M04_AXI_rlast(axi_interconnect_0_M04_AXI_RLAST), - .M04_AXI_rready(axi_interconnect_0_M04_AXI_RREADY), - .M04_AXI_rresp(axi_interconnect_0_M04_AXI_RRESP), - .M04_AXI_rvalid(axi_interconnect_0_M04_AXI_RVALID), - .M04_AXI_wdata(axi_interconnect_0_M04_AXI_WDATA), - .M04_AXI_wlast(axi_interconnect_0_M04_AXI_WLAST), - .M04_AXI_wready(axi_interconnect_0_M04_AXI_WREADY), - .M04_AXI_wstrb(axi_interconnect_0_M04_AXI_WSTRB), - .M04_AXI_wvalid(axi_interconnect_0_M04_AXI_WVALID), - .S00_ACLK(xdma_1_axi_aclk), - .S00_ARESETN(xdma_1_axi_aresetn), + .S00_ACLK(S00_ACLK_1), + .S00_ARESETN(S00_ARESETN_1), .S00_AXI_araddr(S00_AXI_1_ARADDR), .S00_AXI_arburst(S00_AXI_1_ARBURST), .S00_AXI_arcache(S00_AXI_1_ARCACHE), @@ -577,6 +569,44 @@ module Top .ena(axi_bram_ctrl_0_BRAM_PORTA_EN), .rsta(axi_bram_ctrl_0_BRAM_PORTA_RST), .wea(axi_bram_ctrl_0_BRAM_PORTA_WE)); + Top_jtag_axi_0_0 jtag_axi_0 + (.aclk(mig_7series_1_c0_ui_clk), + .aresetn(util_vector_logic_0_Res[0]), + .m_axi_araddr(jtag_axi_0_M_AXI_ARADDR), + .m_axi_arready(jtag_axi_0_M_AXI_ARREADY), + .m_axi_arvalid(jtag_axi_0_M_AXI_ARVALID), + .m_axi_awaddr(jtag_axi_0_M_AXI_AWADDR), + .m_axi_awready(jtag_axi_0_M_AXI_AWREADY), + .m_axi_awvalid(jtag_axi_0_M_AXI_AWVALID), + .m_axi_bready(jtag_axi_0_M_AXI_BREADY), + .m_axi_bresp(jtag_axi_0_M_AXI_BRESP), + .m_axi_bvalid(jtag_axi_0_M_AXI_BVALID), + .m_axi_rdata(jtag_axi_0_M_AXI_RDATA), + .m_axi_rready(jtag_axi_0_M_AXI_RREADY), + .m_axi_rresp(jtag_axi_0_M_AXI_RRESP), + .m_axi_rvalid(jtag_axi_0_M_AXI_RVALID), + .m_axi_wdata(jtag_axi_0_M_AXI_WDATA), + .m_axi_wready(jtag_axi_0_M_AXI_WREADY), + .m_axi_wvalid(jtag_axi_0_M_AXI_WVALID)); + Top_jtag_axi_0_1 jtag_axi_1 + (.aclk(M01_ACLK_1), + .aresetn(util_vector_logic_1_Res[0]), + .m_axi_araddr(jtag_axi_1_M_AXI_ARADDR), + .m_axi_arready(jtag_axi_1_M_AXI_ARREADY), + .m_axi_arvalid(jtag_axi_1_M_AXI_ARVALID), + .m_axi_awaddr(jtag_axi_1_M_AXI_AWADDR), + .m_axi_awready(jtag_axi_1_M_AXI_AWREADY), + .m_axi_awvalid(jtag_axi_1_M_AXI_AWVALID), + .m_axi_bready(jtag_axi_1_M_AXI_BREADY), + .m_axi_bresp(jtag_axi_1_M_AXI_BRESP), + .m_axi_bvalid(jtag_axi_1_M_AXI_BVALID), + .m_axi_rdata(jtag_axi_1_M_AXI_RDATA), + .m_axi_rready(jtag_axi_1_M_AXI_RREADY), + .m_axi_rresp(jtag_axi_1_M_AXI_RRESP), + .m_axi_rvalid(jtag_axi_1_M_AXI_RVALID), + .m_axi_wdata(jtag_axi_1_M_AXI_WDATA), + .m_axi_wready(jtag_axi_1_M_AXI_WREADY), + .m_axi_wvalid(jtag_axi_1_M_AXI_WVALID)); Top_mig_7series_1_0 mig_7series_1 (.c0_aresetn(xlconstant_0_dout), .c0_ddr3_addr(mig_7series_1_C0_DDR3_ADDR), @@ -593,60 +623,62 @@ module Top .c0_ddr3_ras_n(mig_7series_1_C0_DDR3_RAS_N), .c0_ddr3_reset_n(mig_7series_1_C0_DDR3_RESET_N), .c0_ddr3_we_n(mig_7series_1_C0_DDR3_WE_N), - .c0_s_axi_araddr(axi_interconnect_0_M01_AXI_ARADDR), - .c0_s_axi_arburst(axi_interconnect_0_M01_AXI_ARBURST), - .c0_s_axi_arcache(axi_interconnect_0_M01_AXI_ARCACHE), - .c0_s_axi_arid({1'b0,1'b0,1'b0,1'b0}), - .c0_s_axi_arlen(axi_interconnect_0_M01_AXI_ARLEN), - .c0_s_axi_arlock(axi_interconnect_0_M01_AXI_ARLOCK), - .c0_s_axi_arprot(axi_interconnect_0_M01_AXI_ARPROT), - .c0_s_axi_arqos(axi_interconnect_0_M01_AXI_ARQOS), - .c0_s_axi_arready(axi_interconnect_0_M01_AXI_ARREADY), - .c0_s_axi_arsize(axi_interconnect_0_M01_AXI_ARSIZE), - .c0_s_axi_arvalid(axi_interconnect_0_M01_AXI_ARVALID), - .c0_s_axi_awaddr(axi_interconnect_0_M01_AXI_AWADDR), - .c0_s_axi_awburst(axi_interconnect_0_M01_AXI_AWBURST), - .c0_s_axi_awcache(axi_interconnect_0_M01_AXI_AWCACHE), - .c0_s_axi_awid({1'b0,1'b0,1'b0,1'b0}), - .c0_s_axi_awlen(axi_interconnect_0_M01_AXI_AWLEN), - .c0_s_axi_awlock(axi_interconnect_0_M01_AXI_AWLOCK), - .c0_s_axi_awprot(axi_interconnect_0_M01_AXI_AWPROT), - .c0_s_axi_awqos(axi_interconnect_0_M01_AXI_AWQOS), - .c0_s_axi_awready(axi_interconnect_0_M01_AXI_AWREADY), - .c0_s_axi_awsize(axi_interconnect_0_M01_AXI_AWSIZE), - .c0_s_axi_awvalid(axi_interconnect_0_M01_AXI_AWVALID), - .c0_s_axi_bready(axi_interconnect_0_M01_AXI_BREADY), - .c0_s_axi_bresp(axi_interconnect_0_M01_AXI_BRESP), - .c0_s_axi_bvalid(axi_interconnect_0_M01_AXI_BVALID), - .c0_s_axi_ctrl_araddr(axi_interconnect_0_M00_AXI_ARADDR), - .c0_s_axi_ctrl_arready(axi_interconnect_0_M00_AXI_ARREADY), - .c0_s_axi_ctrl_arvalid(axi_interconnect_0_M00_AXI_ARVALID), - .c0_s_axi_ctrl_awaddr(axi_interconnect_0_M00_AXI_AWADDR), - .c0_s_axi_ctrl_awready(axi_interconnect_0_M00_AXI_AWREADY), - .c0_s_axi_ctrl_awvalid(axi_interconnect_0_M00_AXI_AWVALID), - .c0_s_axi_ctrl_bready(axi_interconnect_0_M00_AXI_BREADY), - .c0_s_axi_ctrl_bresp(axi_interconnect_0_M00_AXI_BRESP), - .c0_s_axi_ctrl_bvalid(axi_interconnect_0_M00_AXI_BVALID), - .c0_s_axi_ctrl_rdata(axi_interconnect_0_M00_AXI_RDATA), - .c0_s_axi_ctrl_rready(axi_interconnect_0_M00_AXI_RREADY), - .c0_s_axi_ctrl_rresp(axi_interconnect_0_M00_AXI_RRESP), - .c0_s_axi_ctrl_rvalid(axi_interconnect_0_M00_AXI_RVALID), - .c0_s_axi_ctrl_wdata(axi_interconnect_0_M00_AXI_WDATA), - .c0_s_axi_ctrl_wready(axi_interconnect_0_M00_AXI_WREADY), - .c0_s_axi_ctrl_wvalid(axi_interconnect_0_M00_AXI_WVALID), - .c0_s_axi_rdata(axi_interconnect_0_M01_AXI_RDATA), - .c0_s_axi_rlast(axi_interconnect_0_M01_AXI_RLAST), - .c0_s_axi_rready(axi_interconnect_0_M01_AXI_RREADY), - .c0_s_axi_rresp(axi_interconnect_0_M01_AXI_RRESP), - .c0_s_axi_rvalid(axi_interconnect_0_M01_AXI_RVALID), - .c0_s_axi_wdata(axi_interconnect_0_M01_AXI_WDATA), - .c0_s_axi_wlast(axi_interconnect_0_M01_AXI_WLAST), - .c0_s_axi_wready(axi_interconnect_0_M01_AXI_WREADY), - .c0_s_axi_wstrb(axi_interconnect_0_M01_AXI_WSTRB), - .c0_s_axi_wvalid(axi_interconnect_0_M01_AXI_WVALID), + .c0_s_axi_araddr(axi_interconnect_0_M00_AXI_ARADDR), + .c0_s_axi_arburst(axi_interconnect_0_M00_AXI_ARBURST), + .c0_s_axi_arcache(axi_interconnect_0_M00_AXI_ARCACHE), + .c0_s_axi_arid(axi_interconnect_0_M00_AXI_ARID), + .c0_s_axi_arlen(axi_interconnect_0_M00_AXI_ARLEN), + .c0_s_axi_arlock(axi_interconnect_0_M00_AXI_ARLOCK), + .c0_s_axi_arprot(axi_interconnect_0_M00_AXI_ARPROT), + .c0_s_axi_arqos(axi_interconnect_0_M00_AXI_ARQOS), + .c0_s_axi_arready(axi_interconnect_0_M00_AXI_ARREADY), + .c0_s_axi_arsize(axi_interconnect_0_M00_AXI_ARSIZE), + .c0_s_axi_arvalid(axi_interconnect_0_M00_AXI_ARVALID), + .c0_s_axi_awaddr(axi_interconnect_0_M00_AXI_AWADDR), + .c0_s_axi_awburst(axi_interconnect_0_M00_AXI_AWBURST), + .c0_s_axi_awcache(axi_interconnect_0_M00_AXI_AWCACHE), + .c0_s_axi_awid(axi_interconnect_0_M00_AXI_AWID), + .c0_s_axi_awlen(axi_interconnect_0_M00_AXI_AWLEN), + .c0_s_axi_awlock(axi_interconnect_0_M00_AXI_AWLOCK), + .c0_s_axi_awprot(axi_interconnect_0_M00_AXI_AWPROT), + .c0_s_axi_awqos(axi_interconnect_0_M00_AXI_AWQOS), + .c0_s_axi_awready(axi_interconnect_0_M00_AXI_AWREADY), + .c0_s_axi_awsize(axi_interconnect_0_M00_AXI_AWSIZE), + .c0_s_axi_awvalid(axi_interconnect_0_M00_AXI_AWVALID), + .c0_s_axi_bid(axi_interconnect_0_M00_AXI_BID), + .c0_s_axi_bready(axi_interconnect_0_M00_AXI_BREADY), + .c0_s_axi_bresp(axi_interconnect_0_M00_AXI_BRESP), + .c0_s_axi_bvalid(axi_interconnect_0_M00_AXI_BVALID), + .c0_s_axi_ctrl_araddr(jtag_axi_0_M_AXI_ARADDR[31:0]), + .c0_s_axi_ctrl_arready(jtag_axi_0_M_AXI_ARREADY), + .c0_s_axi_ctrl_arvalid(jtag_axi_0_M_AXI_ARVALID), + .c0_s_axi_ctrl_awaddr(jtag_axi_0_M_AXI_AWADDR[31:0]), + .c0_s_axi_ctrl_awready(jtag_axi_0_M_AXI_AWREADY), + .c0_s_axi_ctrl_awvalid(jtag_axi_0_M_AXI_AWVALID), + .c0_s_axi_ctrl_bready(jtag_axi_0_M_AXI_BREADY), + .c0_s_axi_ctrl_bresp(jtag_axi_0_M_AXI_BRESP), + .c0_s_axi_ctrl_bvalid(jtag_axi_0_M_AXI_BVALID), + .c0_s_axi_ctrl_rdata(jtag_axi_0_M_AXI_RDATA), + .c0_s_axi_ctrl_rready(jtag_axi_0_M_AXI_RREADY), + .c0_s_axi_ctrl_rresp(jtag_axi_0_M_AXI_RRESP), + .c0_s_axi_ctrl_rvalid(jtag_axi_0_M_AXI_RVALID), + .c0_s_axi_ctrl_wdata(jtag_axi_0_M_AXI_WDATA), + .c0_s_axi_ctrl_wready(jtag_axi_0_M_AXI_WREADY), + .c0_s_axi_ctrl_wvalid(jtag_axi_0_M_AXI_WVALID), + .c0_s_axi_rdata(axi_interconnect_0_M00_AXI_RDATA), + .c0_s_axi_rid(axi_interconnect_0_M00_AXI_RID), + .c0_s_axi_rlast(axi_interconnect_0_M00_AXI_RLAST), + .c0_s_axi_rready(axi_interconnect_0_M00_AXI_RREADY), + .c0_s_axi_rresp(axi_interconnect_0_M00_AXI_RRESP), + .c0_s_axi_rvalid(axi_interconnect_0_M00_AXI_RVALID), + .c0_s_axi_wdata(axi_interconnect_0_M00_AXI_WDATA), + .c0_s_axi_wlast(axi_interconnect_0_M00_AXI_WLAST), + .c0_s_axi_wready(axi_interconnect_0_M00_AXI_WREADY), + .c0_s_axi_wstrb(axi_interconnect_0_M00_AXI_WSTRB), + .c0_s_axi_wvalid(axi_interconnect_0_M00_AXI_WVALID), .c0_sys_clk_n(C0_SYS_CLK_0_1_CLK_N), .c0_sys_clk_p(C0_SYS_CLK_0_1_CLK_P), - .c0_ui_clk(mig_7series_1_ui_clk), + .c0_ui_clk(mig_7series_1_c0_ui_clk), .c0_ui_clk_sync_rst(mig_7series_1_c0_ui_clk_sync_rst), .c1_aresetn(xlconstant_0_dout), .c1_ddr3_addr(mig_7series_1_C1_DDR3_ADDR), @@ -663,75 +695,77 @@ module Top .c1_ddr3_ras_n(mig_7series_1_C1_DDR3_RAS_N), .c1_ddr3_reset_n(mig_7series_1_C1_DDR3_RESET_N), .c1_ddr3_we_n(mig_7series_1_C1_DDR3_WE_N), - .c1_s_axi_araddr(axi_interconnect_0_M03_AXI_ARADDR), - .c1_s_axi_arburst(axi_interconnect_0_M03_AXI_ARBURST), - .c1_s_axi_arcache(axi_interconnect_0_M03_AXI_ARCACHE), - .c1_s_axi_arid({1'b0,1'b0,1'b0,1'b0}), - .c1_s_axi_arlen(axi_interconnect_0_M03_AXI_ARLEN), - .c1_s_axi_arlock(axi_interconnect_0_M03_AXI_ARLOCK), - .c1_s_axi_arprot(axi_interconnect_0_M03_AXI_ARPROT), - .c1_s_axi_arqos(axi_interconnect_0_M03_AXI_ARQOS), - .c1_s_axi_arready(axi_interconnect_0_M03_AXI_ARREADY), - .c1_s_axi_arsize(axi_interconnect_0_M03_AXI_ARSIZE), - .c1_s_axi_arvalid(axi_interconnect_0_M03_AXI_ARVALID), - .c1_s_axi_awaddr(axi_interconnect_0_M03_AXI_AWADDR), - .c1_s_axi_awburst(axi_interconnect_0_M03_AXI_AWBURST), - .c1_s_axi_awcache(axi_interconnect_0_M03_AXI_AWCACHE), - .c1_s_axi_awid({1'b0,1'b0,1'b0,1'b0}), - .c1_s_axi_awlen(axi_interconnect_0_M03_AXI_AWLEN), - .c1_s_axi_awlock(axi_interconnect_0_M03_AXI_AWLOCK), - .c1_s_axi_awprot(axi_interconnect_0_M03_AXI_AWPROT), - .c1_s_axi_awqos(axi_interconnect_0_M03_AXI_AWQOS), - .c1_s_axi_awready(axi_interconnect_0_M03_AXI_AWREADY), - .c1_s_axi_awsize(axi_interconnect_0_M03_AXI_AWSIZE), - .c1_s_axi_awvalid(axi_interconnect_0_M03_AXI_AWVALID), - .c1_s_axi_bready(axi_interconnect_0_M03_AXI_BREADY), - .c1_s_axi_bresp(axi_interconnect_0_M03_AXI_BRESP), - .c1_s_axi_bvalid(axi_interconnect_0_M03_AXI_BVALID), - .c1_s_axi_ctrl_araddr(axi_interconnect_0_M02_AXI_ARADDR), - .c1_s_axi_ctrl_arready(axi_interconnect_0_M02_AXI_ARREADY), - .c1_s_axi_ctrl_arvalid(axi_interconnect_0_M02_AXI_ARVALID), - .c1_s_axi_ctrl_awaddr(axi_interconnect_0_M02_AXI_AWADDR), - .c1_s_axi_ctrl_awready(axi_interconnect_0_M02_AXI_AWREADY), - .c1_s_axi_ctrl_awvalid(axi_interconnect_0_M02_AXI_AWVALID), - .c1_s_axi_ctrl_bready(axi_interconnect_0_M02_AXI_BREADY), - .c1_s_axi_ctrl_bresp(axi_interconnect_0_M02_AXI_BRESP), - .c1_s_axi_ctrl_bvalid(axi_interconnect_0_M02_AXI_BVALID), - .c1_s_axi_ctrl_rdata(axi_interconnect_0_M02_AXI_RDATA), - .c1_s_axi_ctrl_rready(axi_interconnect_0_M02_AXI_RREADY), - .c1_s_axi_ctrl_rresp(axi_interconnect_0_M02_AXI_RRESP), - .c1_s_axi_ctrl_rvalid(axi_interconnect_0_M02_AXI_RVALID), - .c1_s_axi_ctrl_wdata(axi_interconnect_0_M02_AXI_WDATA), - .c1_s_axi_ctrl_wready(axi_interconnect_0_M02_AXI_WREADY), - .c1_s_axi_ctrl_wvalid(axi_interconnect_0_M02_AXI_WVALID), - .c1_s_axi_rdata(axi_interconnect_0_M03_AXI_RDATA), - .c1_s_axi_rlast(axi_interconnect_0_M03_AXI_RLAST), - .c1_s_axi_rready(axi_interconnect_0_M03_AXI_RREADY), - .c1_s_axi_rresp(axi_interconnect_0_M03_AXI_RRESP), - .c1_s_axi_rvalid(axi_interconnect_0_M03_AXI_RVALID), - .c1_s_axi_wdata(axi_interconnect_0_M03_AXI_WDATA), - .c1_s_axi_wlast(axi_interconnect_0_M03_AXI_WLAST), - .c1_s_axi_wready(axi_interconnect_0_M03_AXI_WREADY), - .c1_s_axi_wstrb(axi_interconnect_0_M03_AXI_WSTRB), - .c1_s_axi_wvalid(axi_interconnect_0_M03_AXI_WVALID), + .c1_s_axi_araddr(axi_interconnect_0_M01_AXI_ARADDR), + .c1_s_axi_arburst(axi_interconnect_0_M01_AXI_ARBURST), + .c1_s_axi_arcache(axi_interconnect_0_M01_AXI_ARCACHE), + .c1_s_axi_arid(axi_interconnect_0_M01_AXI_ARID), + .c1_s_axi_arlen(axi_interconnect_0_M01_AXI_ARLEN), + .c1_s_axi_arlock(axi_interconnect_0_M01_AXI_ARLOCK), + .c1_s_axi_arprot(axi_interconnect_0_M01_AXI_ARPROT), + .c1_s_axi_arqos(axi_interconnect_0_M01_AXI_ARQOS), + .c1_s_axi_arready(axi_interconnect_0_M01_AXI_ARREADY), + .c1_s_axi_arsize(axi_interconnect_0_M01_AXI_ARSIZE), + .c1_s_axi_arvalid(axi_interconnect_0_M01_AXI_ARVALID), + .c1_s_axi_awaddr(axi_interconnect_0_M01_AXI_AWADDR), + .c1_s_axi_awburst(axi_interconnect_0_M01_AXI_AWBURST), + .c1_s_axi_awcache(axi_interconnect_0_M01_AXI_AWCACHE), + .c1_s_axi_awid(axi_interconnect_0_M01_AXI_AWID), + .c1_s_axi_awlen(axi_interconnect_0_M01_AXI_AWLEN), + .c1_s_axi_awlock(axi_interconnect_0_M01_AXI_AWLOCK), + .c1_s_axi_awprot(axi_interconnect_0_M01_AXI_AWPROT), + .c1_s_axi_awqos(axi_interconnect_0_M01_AXI_AWQOS), + .c1_s_axi_awready(axi_interconnect_0_M01_AXI_AWREADY), + .c1_s_axi_awsize(axi_interconnect_0_M01_AXI_AWSIZE), + .c1_s_axi_awvalid(axi_interconnect_0_M01_AXI_AWVALID), + .c1_s_axi_bid(axi_interconnect_0_M01_AXI_BID), + .c1_s_axi_bready(axi_interconnect_0_M01_AXI_BREADY), + .c1_s_axi_bresp(axi_interconnect_0_M01_AXI_BRESP), + .c1_s_axi_bvalid(axi_interconnect_0_M01_AXI_BVALID), + .c1_s_axi_ctrl_araddr(jtag_axi_1_M_AXI_ARADDR[31:0]), + .c1_s_axi_ctrl_arready(jtag_axi_1_M_AXI_ARREADY), + .c1_s_axi_ctrl_arvalid(jtag_axi_1_M_AXI_ARVALID), + .c1_s_axi_ctrl_awaddr(jtag_axi_1_M_AXI_AWADDR[31:0]), + .c1_s_axi_ctrl_awready(jtag_axi_1_M_AXI_AWREADY), + .c1_s_axi_ctrl_awvalid(jtag_axi_1_M_AXI_AWVALID), + .c1_s_axi_ctrl_bready(jtag_axi_1_M_AXI_BREADY), + .c1_s_axi_ctrl_bresp(jtag_axi_1_M_AXI_BRESP), + .c1_s_axi_ctrl_bvalid(jtag_axi_1_M_AXI_BVALID), + .c1_s_axi_ctrl_rdata(jtag_axi_1_M_AXI_RDATA), + .c1_s_axi_ctrl_rready(jtag_axi_1_M_AXI_RREADY), + .c1_s_axi_ctrl_rresp(jtag_axi_1_M_AXI_RRESP), + .c1_s_axi_ctrl_rvalid(jtag_axi_1_M_AXI_RVALID), + .c1_s_axi_ctrl_wdata(jtag_axi_1_M_AXI_WDATA), + .c1_s_axi_ctrl_wready(jtag_axi_1_M_AXI_WREADY), + .c1_s_axi_ctrl_wvalid(jtag_axi_1_M_AXI_WVALID), + .c1_s_axi_rdata(axi_interconnect_0_M01_AXI_RDATA), + .c1_s_axi_rid(axi_interconnect_0_M01_AXI_RID), + .c1_s_axi_rlast(axi_interconnect_0_M01_AXI_RLAST), + .c1_s_axi_rready(axi_interconnect_0_M01_AXI_RREADY), + .c1_s_axi_rresp(axi_interconnect_0_M01_AXI_RRESP), + .c1_s_axi_rvalid(axi_interconnect_0_M01_AXI_RVALID), + .c1_s_axi_wdata(axi_interconnect_0_M01_AXI_WDATA), + .c1_s_axi_wlast(axi_interconnect_0_M01_AXI_WLAST), + .c1_s_axi_wready(axi_interconnect_0_M01_AXI_WREADY), + .c1_s_axi_wstrb(axi_interconnect_0_M01_AXI_WSTRB), + .c1_s_axi_wvalid(axi_interconnect_0_M01_AXI_WVALID), .c1_sys_clk_n(C1_SYS_CLK_0_1_CLK_N), .c1_sys_clk_p(C1_SYS_CLK_0_1_CLK_P), - .c1_ui_clk(mig_7series_1_c1_ui_clk), + .c1_ui_clk(M01_ACLK_1), .c1_ui_clk_sync_rst(mig_7series_1_c1_ui_clk_sync_rst), .sys_rst(xlconstant_2_dout)); Top_util_ds_buf_0_0 util_ds_buf_0 (.IBUF_DS_N(pcie_clkin_1_CLK_N), .IBUF_DS_P(pcie_clkin_1_CLK_P), .IBUF_OUT(util_ds_buf_0_IBUF_OUT)); - Top_util_vector_logic_1_3 util_vector_logic_1 + Top_util_vector_logic_0_0 util_vector_logic_0 (.Op1({mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst}), - .Res(M00_ARESETN_2)); - Top_util_vector_logic_1_4 util_vector_logic_2 + .Res(util_vector_logic_0_Res)); + Top_util_vector_logic_0_1 util_vector_logic_1 (.Op1({mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst}), - .Res(util_vector_logic_2_Res)); + .Res(util_vector_logic_1_Res)); Top_xdma_1_0 xdma_1 - (.axi_aclk(xdma_1_axi_aclk), - .axi_aresetn(xdma_1_axi_aresetn), + (.axi_aclk(S00_ACLK_1), + .axi_aresetn(S00_ARESETN_1), .cfg_mgmt_addr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), .cfg_mgmt_byte_enable({1'b0,1'b0,1'b0,1'b0}), .cfg_mgmt_read(1'b0), @@ -793,26 +827,48 @@ module Top_axi_interconnect_0_0 M00_ACLK, M00_ARESETN, M00_AXI_araddr, + M00_AXI_arburst, + M00_AXI_arcache, + M00_AXI_arid, + M00_AXI_arlen, + M00_AXI_arlock, + M00_AXI_arprot, + M00_AXI_arqos, M00_AXI_arready, + M00_AXI_arsize, M00_AXI_arvalid, M00_AXI_awaddr, + M00_AXI_awburst, + M00_AXI_awcache, + M00_AXI_awid, + M00_AXI_awlen, + M00_AXI_awlock, + M00_AXI_awprot, + M00_AXI_awqos, M00_AXI_awready, + M00_AXI_awsize, M00_AXI_awvalid, + M00_AXI_bid, M00_AXI_bready, M00_AXI_bresp, M00_AXI_bvalid, M00_AXI_rdata, + M00_AXI_rid, + M00_AXI_rlast, M00_AXI_rready, M00_AXI_rresp, M00_AXI_rvalid, M00_AXI_wdata, + M00_AXI_wlast, M00_AXI_wready, + M00_AXI_wstrb, M00_AXI_wvalid, M01_ACLK, M01_ARESETN, M01_AXI_araddr, M01_AXI_arburst, M01_AXI_arcache, + M01_AXI_arid, M01_AXI_arlen, M01_AXI_arlock, M01_AXI_arprot, @@ -823,6 +879,7 @@ module Top_axi_interconnect_0_0 M01_AXI_awaddr, M01_AXI_awburst, M01_AXI_awcache, + M01_AXI_awid, M01_AXI_awlen, M01_AXI_awlock, M01_AXI_awprot, @@ -830,10 +887,12 @@ module Top_axi_interconnect_0_0 M01_AXI_awready, M01_AXI_awsize, M01_AXI_awvalid, + M01_AXI_bid, M01_AXI_bready, M01_AXI_bresp, M01_AXI_bvalid, M01_AXI_rdata, + M01_AXI_rid, M01_AXI_rlast, M01_AXI_rready, M01_AXI_rresp, @@ -846,89 +905,40 @@ module Top_axi_interconnect_0_0 M02_ACLK, M02_ARESETN, M02_AXI_araddr, + M02_AXI_arburst, + M02_AXI_arcache, + M02_AXI_arid, + M02_AXI_arlen, + M02_AXI_arlock, + M02_AXI_arprot, M02_AXI_arready, + M02_AXI_arsize, M02_AXI_arvalid, M02_AXI_awaddr, + M02_AXI_awburst, + M02_AXI_awcache, + M02_AXI_awid, + M02_AXI_awlen, + M02_AXI_awlock, + M02_AXI_awprot, M02_AXI_awready, + M02_AXI_awsize, M02_AXI_awvalid, + M02_AXI_bid, M02_AXI_bready, M02_AXI_bresp, M02_AXI_bvalid, M02_AXI_rdata, + M02_AXI_rid, + M02_AXI_rlast, M02_AXI_rready, M02_AXI_rresp, M02_AXI_rvalid, M02_AXI_wdata, + M02_AXI_wlast, M02_AXI_wready, + M02_AXI_wstrb, M02_AXI_wvalid, - M03_ACLK, - M03_ARESETN, - M03_AXI_araddr, - M03_AXI_arburst, - M03_AXI_arcache, - M03_AXI_arlen, - M03_AXI_arlock, - M03_AXI_arprot, - M03_AXI_arqos, - M03_AXI_arready, - M03_AXI_arsize, - M03_AXI_arvalid, - M03_AXI_awaddr, - M03_AXI_awburst, - M03_AXI_awcache, - M03_AXI_awlen, - M03_AXI_awlock, - M03_AXI_awprot, - M03_AXI_awqos, - M03_AXI_awready, - M03_AXI_awsize, - M03_AXI_awvalid, - M03_AXI_bready, - M03_AXI_bresp, - M03_AXI_bvalid, - M03_AXI_rdata, - M03_AXI_rlast, - M03_AXI_rready, - M03_AXI_rresp, - M03_AXI_rvalid, - M03_AXI_wdata, - M03_AXI_wlast, - M03_AXI_wready, - M03_AXI_wstrb, - M03_AXI_wvalid, - M04_ACLK, - M04_ARESETN, - M04_AXI_araddr, - M04_AXI_arburst, - M04_AXI_arcache, - M04_AXI_arlen, - M04_AXI_arlock, - M04_AXI_arprot, - M04_AXI_arready, - M04_AXI_arsize, - M04_AXI_arvalid, - M04_AXI_awaddr, - M04_AXI_awburst, - M04_AXI_awcache, - M04_AXI_awlen, - M04_AXI_awlock, - M04_AXI_awprot, - M04_AXI_awready, - M04_AXI_awsize, - M04_AXI_awvalid, - M04_AXI_bready, - M04_AXI_bresp, - M04_AXI_bvalid, - M04_AXI_rdata, - M04_AXI_rlast, - M04_AXI_rready, - M04_AXI_rresp, - M04_AXI_rvalid, - M04_AXI_wdata, - M04_AXI_wlast, - M04_AXI_wready, - M04_AXI_wstrb, - M04_AXI_wvalid, S00_ACLK, S00_ARESETN, S00_AXI_araddr, @@ -970,27 +980,49 @@ module Top_axi_interconnect_0_0 input ARESETN; input M00_ACLK; input [7:0]M00_ARESETN; - output [31:0]M00_AXI_araddr; + output [30:0]M00_AXI_araddr; + output [1:0]M00_AXI_arburst; + output [3:0]M00_AXI_arcache; + output [3:0]M00_AXI_arid; + output [7:0]M00_AXI_arlen; + output M00_AXI_arlock; + output [2:0]M00_AXI_arprot; + output [3:0]M00_AXI_arqos; input M00_AXI_arready; + output [2:0]M00_AXI_arsize; output M00_AXI_arvalid; - output [31:0]M00_AXI_awaddr; + output [30:0]M00_AXI_awaddr; + output [1:0]M00_AXI_awburst; + output [3:0]M00_AXI_awcache; + output [3:0]M00_AXI_awid; + output [7:0]M00_AXI_awlen; + output M00_AXI_awlock; + output [2:0]M00_AXI_awprot; + output [3:0]M00_AXI_awqos; input M00_AXI_awready; + output [2:0]M00_AXI_awsize; output M00_AXI_awvalid; + input [3:0]M00_AXI_bid; output M00_AXI_bready; input [1:0]M00_AXI_bresp; input M00_AXI_bvalid; - input [31:0]M00_AXI_rdata; + input [63:0]M00_AXI_rdata; + input [3:0]M00_AXI_rid; + input M00_AXI_rlast; output M00_AXI_rready; input [1:0]M00_AXI_rresp; input M00_AXI_rvalid; - output [31:0]M00_AXI_wdata; + output [63:0]M00_AXI_wdata; + output M00_AXI_wlast; input M00_AXI_wready; + output [7:0]M00_AXI_wstrb; output M00_AXI_wvalid; input M01_ACLK; input [7:0]M01_ARESETN; output [30:0]M01_AXI_araddr; output [1:0]M01_AXI_arburst; output [3:0]M01_AXI_arcache; + output [3:0]M01_AXI_arid; output [7:0]M01_AXI_arlen; output M01_AXI_arlock; output [2:0]M01_AXI_arprot; @@ -1001,6 +1033,7 @@ module Top_axi_interconnect_0_0 output [30:0]M01_AXI_awaddr; output [1:0]M01_AXI_awburst; output [3:0]M01_AXI_awcache; + output [3:0]M01_AXI_awid; output [7:0]M01_AXI_awlen; output M01_AXI_awlock; output [2:0]M01_AXI_awprot; @@ -1008,105 +1041,58 @@ module Top_axi_interconnect_0_0 input M01_AXI_awready; output [2:0]M01_AXI_awsize; output M01_AXI_awvalid; + input [3:0]M01_AXI_bid; output M01_AXI_bready; input [1:0]M01_AXI_bresp; input M01_AXI_bvalid; - input [511:0]M01_AXI_rdata; + input [63:0]M01_AXI_rdata; + input [3:0]M01_AXI_rid; input M01_AXI_rlast; output M01_AXI_rready; input [1:0]M01_AXI_rresp; input M01_AXI_rvalid; - output [511:0]M01_AXI_wdata; + output [63:0]M01_AXI_wdata; output M01_AXI_wlast; input M01_AXI_wready; - output [63:0]M01_AXI_wstrb; + output [7:0]M01_AXI_wstrb; output M01_AXI_wvalid; input M02_ACLK; input [7:0]M02_ARESETN; - output [31:0]M02_AXI_araddr; + output [63:0]M02_AXI_araddr; + output [1:0]M02_AXI_arburst; + output [3:0]M02_AXI_arcache; + output [3:0]M02_AXI_arid; + output [7:0]M02_AXI_arlen; + output M02_AXI_arlock; + output [2:0]M02_AXI_arprot; input M02_AXI_arready; + output [2:0]M02_AXI_arsize; output M02_AXI_arvalid; - output [31:0]M02_AXI_awaddr; + output [63:0]M02_AXI_awaddr; + output [1:0]M02_AXI_awburst; + output [3:0]M02_AXI_awcache; + output [3:0]M02_AXI_awid; + output [7:0]M02_AXI_awlen; + output M02_AXI_awlock; + output [2:0]M02_AXI_awprot; input M02_AXI_awready; + output [2:0]M02_AXI_awsize; output M02_AXI_awvalid; + input [3:0]M02_AXI_bid; output M02_AXI_bready; input [1:0]M02_AXI_bresp; input M02_AXI_bvalid; - input [31:0]M02_AXI_rdata; + input [63:0]M02_AXI_rdata; + input [3:0]M02_AXI_rid; + input M02_AXI_rlast; output M02_AXI_rready; input [1:0]M02_AXI_rresp; input M02_AXI_rvalid; - output [31:0]M02_AXI_wdata; + output [63:0]M02_AXI_wdata; + output M02_AXI_wlast; input M02_AXI_wready; + output [7:0]M02_AXI_wstrb; output M02_AXI_wvalid; - input M03_ACLK; - input [7:0]M03_ARESETN; - output [30:0]M03_AXI_araddr; - output [1:0]M03_AXI_arburst; - output [3:0]M03_AXI_arcache; - output [7:0]M03_AXI_arlen; - output M03_AXI_arlock; - output [2:0]M03_AXI_arprot; - output [3:0]M03_AXI_arqos; - input M03_AXI_arready; - output [2:0]M03_AXI_arsize; - output M03_AXI_arvalid; - output [30:0]M03_AXI_awaddr; - output [1:0]M03_AXI_awburst; - output [3:0]M03_AXI_awcache; - output [7:0]M03_AXI_awlen; - output M03_AXI_awlock; - output [2:0]M03_AXI_awprot; - output [3:0]M03_AXI_awqos; - input M03_AXI_awready; - output [2:0]M03_AXI_awsize; - output M03_AXI_awvalid; - output M03_AXI_bready; - input [1:0]M03_AXI_bresp; - input M03_AXI_bvalid; - input [511:0]M03_AXI_rdata; - input M03_AXI_rlast; - output M03_AXI_rready; - input [1:0]M03_AXI_rresp; - input M03_AXI_rvalid; - output [511:0]M03_AXI_wdata; - output M03_AXI_wlast; - input M03_AXI_wready; - output [63:0]M03_AXI_wstrb; - output M03_AXI_wvalid; - input M04_ACLK; - input M04_ARESETN; - output [12:0]M04_AXI_araddr; - output [1:0]M04_AXI_arburst; - output [3:0]M04_AXI_arcache; - output [7:0]M04_AXI_arlen; - output M04_AXI_arlock; - output [2:0]M04_AXI_arprot; - input M04_AXI_arready; - output [2:0]M04_AXI_arsize; - output M04_AXI_arvalid; - output [12:0]M04_AXI_awaddr; - output [1:0]M04_AXI_awburst; - output [3:0]M04_AXI_awcache; - output [7:0]M04_AXI_awlen; - output M04_AXI_awlock; - output [2:0]M04_AXI_awprot; - input M04_AXI_awready; - output [2:0]M04_AXI_awsize; - output M04_AXI_awvalid; - output M04_AXI_bready; - input [1:0]M04_AXI_bresp; - input M04_AXI_bvalid; - input [31:0]M04_AXI_rdata; - input M04_AXI_rlast; - output M04_AXI_rready; - input [1:0]M04_AXI_rresp; - input M04_AXI_rvalid; - output [31:0]M04_AXI_wdata; - output M04_AXI_wlast; - input M04_AXI_wready; - output [3:0]M04_AXI_wstrb; - output M04_AXI_wvalid; input S00_ACLK; input S00_ARESETN; input [63:0]S00_AXI_araddr; @@ -1116,9 +1102,9 @@ module Top_axi_interconnect_0_0 input [7:0]S00_AXI_arlen; input [0:0]S00_AXI_arlock; input [2:0]S00_AXI_arprot; - output S00_AXI_arready; + output [0:0]S00_AXI_arready; input [2:0]S00_AXI_arsize; - input S00_AXI_arvalid; + input [0:0]S00_AXI_arvalid; input [63:0]S00_AXI_awaddr; input [1:0]S00_AXI_awburst; input [3:0]S00_AXI_awcache; @@ -1126,24 +1112,24 @@ module Top_axi_interconnect_0_0 input [7:0]S00_AXI_awlen; input [0:0]S00_AXI_awlock; input [2:0]S00_AXI_awprot; - output S00_AXI_awready; + output [0:0]S00_AXI_awready; input [2:0]S00_AXI_awsize; - input S00_AXI_awvalid; + input [0:0]S00_AXI_awvalid; output [3:0]S00_AXI_bid; - input S00_AXI_bready; + input [0:0]S00_AXI_bready; output [1:0]S00_AXI_bresp; - output S00_AXI_bvalid; + output [0:0]S00_AXI_bvalid; output [63:0]S00_AXI_rdata; output [3:0]S00_AXI_rid; - output S00_AXI_rlast; - input S00_AXI_rready; + output [0:0]S00_AXI_rlast; + input [0:0]S00_AXI_rready; output [1:0]S00_AXI_rresp; - output S00_AXI_rvalid; + output [0:0]S00_AXI_rvalid; input [63:0]S00_AXI_wdata; - input S00_AXI_wlast; - output S00_AXI_wready; + input [0:0]S00_AXI_wlast; + output [0:0]S00_AXI_wready; input [7:0]S00_AXI_wstrb; - input S00_AXI_wvalid; + input [0:0]S00_AXI_wvalid; wire M00_ACLK_1; wire [7:0]M00_ARESETN_1; @@ -1151,10 +1137,6 @@ module Top_axi_interconnect_0_0 wire [7:0]M01_ARESETN_1; wire M02_ACLK_1; wire [7:0]M02_ARESETN_1; - wire M03_ACLK_1; - wire [7:0]M03_ARESETN_1; - wire M04_ACLK_1; - wire M04_ARESETN_1; wire S00_ACLK_1; wire S00_ARESETN_1; wire axi_interconnect_0_ACLK_net; @@ -1166,9 +1148,9 @@ module Top_axi_interconnect_0_0 wire [7:0]axi_interconnect_0_to_s00_couplers_ARLEN; wire [0:0]axi_interconnect_0_to_s00_couplers_ARLOCK; wire [2:0]axi_interconnect_0_to_s00_couplers_ARPROT; - wire axi_interconnect_0_to_s00_couplers_ARREADY; + wire [0:0]axi_interconnect_0_to_s00_couplers_ARREADY; wire [2:0]axi_interconnect_0_to_s00_couplers_ARSIZE; - wire axi_interconnect_0_to_s00_couplers_ARVALID; + wire [0:0]axi_interconnect_0_to_s00_couplers_ARVALID; wire [63:0]axi_interconnect_0_to_s00_couplers_AWADDR; wire [1:0]axi_interconnect_0_to_s00_couplers_AWBURST; wire [3:0]axi_interconnect_0_to_s00_couplers_AWCACHE; @@ -1176,43 +1158,65 @@ module Top_axi_interconnect_0_0 wire [7:0]axi_interconnect_0_to_s00_couplers_AWLEN; wire [0:0]axi_interconnect_0_to_s00_couplers_AWLOCK; wire [2:0]axi_interconnect_0_to_s00_couplers_AWPROT; - wire axi_interconnect_0_to_s00_couplers_AWREADY; + wire [0:0]axi_interconnect_0_to_s00_couplers_AWREADY; wire [2:0]axi_interconnect_0_to_s00_couplers_AWSIZE; - wire axi_interconnect_0_to_s00_couplers_AWVALID; + wire [0:0]axi_interconnect_0_to_s00_couplers_AWVALID; wire [3:0]axi_interconnect_0_to_s00_couplers_BID; - wire axi_interconnect_0_to_s00_couplers_BREADY; + wire [0:0]axi_interconnect_0_to_s00_couplers_BREADY; wire [1:0]axi_interconnect_0_to_s00_couplers_BRESP; - wire axi_interconnect_0_to_s00_couplers_BVALID; + wire [0:0]axi_interconnect_0_to_s00_couplers_BVALID; wire [63:0]axi_interconnect_0_to_s00_couplers_RDATA; wire [3:0]axi_interconnect_0_to_s00_couplers_RID; - wire axi_interconnect_0_to_s00_couplers_RLAST; - wire axi_interconnect_0_to_s00_couplers_RREADY; + wire [0:0]axi_interconnect_0_to_s00_couplers_RLAST; + wire [0:0]axi_interconnect_0_to_s00_couplers_RREADY; wire [1:0]axi_interconnect_0_to_s00_couplers_RRESP; - wire axi_interconnect_0_to_s00_couplers_RVALID; + wire [0:0]axi_interconnect_0_to_s00_couplers_RVALID; wire [63:0]axi_interconnect_0_to_s00_couplers_WDATA; - wire axi_interconnect_0_to_s00_couplers_WLAST; - wire axi_interconnect_0_to_s00_couplers_WREADY; + wire [0:0]axi_interconnect_0_to_s00_couplers_WLAST; + wire [0:0]axi_interconnect_0_to_s00_couplers_WREADY; wire [7:0]axi_interconnect_0_to_s00_couplers_WSTRB; - wire axi_interconnect_0_to_s00_couplers_WVALID; - wire [31:0]m00_couplers_to_axi_interconnect_0_ARADDR; + wire [0:0]axi_interconnect_0_to_s00_couplers_WVALID; + wire [30:0]m00_couplers_to_axi_interconnect_0_ARADDR; + wire [1:0]m00_couplers_to_axi_interconnect_0_ARBURST; + wire [3:0]m00_couplers_to_axi_interconnect_0_ARCACHE; + wire [3:0]m00_couplers_to_axi_interconnect_0_ARID; + wire [7:0]m00_couplers_to_axi_interconnect_0_ARLEN; + wire m00_couplers_to_axi_interconnect_0_ARLOCK; + wire [2:0]m00_couplers_to_axi_interconnect_0_ARPROT; + wire [3:0]m00_couplers_to_axi_interconnect_0_ARQOS; wire m00_couplers_to_axi_interconnect_0_ARREADY; + wire [2:0]m00_couplers_to_axi_interconnect_0_ARSIZE; wire m00_couplers_to_axi_interconnect_0_ARVALID; - wire [31:0]m00_couplers_to_axi_interconnect_0_AWADDR; + wire [30:0]m00_couplers_to_axi_interconnect_0_AWADDR; + wire [1:0]m00_couplers_to_axi_interconnect_0_AWBURST; + wire [3:0]m00_couplers_to_axi_interconnect_0_AWCACHE; + wire [3:0]m00_couplers_to_axi_interconnect_0_AWID; + wire [7:0]m00_couplers_to_axi_interconnect_0_AWLEN; + wire m00_couplers_to_axi_interconnect_0_AWLOCK; + wire [2:0]m00_couplers_to_axi_interconnect_0_AWPROT; + wire [3:0]m00_couplers_to_axi_interconnect_0_AWQOS; wire m00_couplers_to_axi_interconnect_0_AWREADY; + wire [2:0]m00_couplers_to_axi_interconnect_0_AWSIZE; wire m00_couplers_to_axi_interconnect_0_AWVALID; + wire [3:0]m00_couplers_to_axi_interconnect_0_BID; wire m00_couplers_to_axi_interconnect_0_BREADY; wire [1:0]m00_couplers_to_axi_interconnect_0_BRESP; wire m00_couplers_to_axi_interconnect_0_BVALID; - wire [31:0]m00_couplers_to_axi_interconnect_0_RDATA; + wire [63:0]m00_couplers_to_axi_interconnect_0_RDATA; + wire [3:0]m00_couplers_to_axi_interconnect_0_RID; + wire m00_couplers_to_axi_interconnect_0_RLAST; wire m00_couplers_to_axi_interconnect_0_RREADY; wire [1:0]m00_couplers_to_axi_interconnect_0_RRESP; wire m00_couplers_to_axi_interconnect_0_RVALID; - wire [31:0]m00_couplers_to_axi_interconnect_0_WDATA; + wire [63:0]m00_couplers_to_axi_interconnect_0_WDATA; + wire m00_couplers_to_axi_interconnect_0_WLAST; wire m00_couplers_to_axi_interconnect_0_WREADY; + wire [7:0]m00_couplers_to_axi_interconnect_0_WSTRB; wire m00_couplers_to_axi_interconnect_0_WVALID; wire [30:0]m01_couplers_to_axi_interconnect_0_ARADDR; wire [1:0]m01_couplers_to_axi_interconnect_0_ARBURST; wire [3:0]m01_couplers_to_axi_interconnect_0_ARCACHE; + wire [3:0]m01_couplers_to_axi_interconnect_0_ARID; wire [7:0]m01_couplers_to_axi_interconnect_0_ARLEN; wire m01_couplers_to_axi_interconnect_0_ARLOCK; wire [2:0]m01_couplers_to_axi_interconnect_0_ARPROT; @@ -1223,6 +1227,7 @@ module Top_axi_interconnect_0_0 wire [30:0]m01_couplers_to_axi_interconnect_0_AWADDR; wire [1:0]m01_couplers_to_axi_interconnect_0_AWBURST; wire [3:0]m01_couplers_to_axi_interconnect_0_AWCACHE; + wire [3:0]m01_couplers_to_axi_interconnect_0_AWID; wire [7:0]m01_couplers_to_axi_interconnect_0_AWLEN; wire m01_couplers_to_axi_interconnect_0_AWLOCK; wire [2:0]m01_couplers_to_axi_interconnect_0_AWPROT; @@ -1230,135 +1235,95 @@ module Top_axi_interconnect_0_0 wire m01_couplers_to_axi_interconnect_0_AWREADY; wire [2:0]m01_couplers_to_axi_interconnect_0_AWSIZE; wire m01_couplers_to_axi_interconnect_0_AWVALID; + wire [3:0]m01_couplers_to_axi_interconnect_0_BID; wire m01_couplers_to_axi_interconnect_0_BREADY; wire [1:0]m01_couplers_to_axi_interconnect_0_BRESP; wire m01_couplers_to_axi_interconnect_0_BVALID; - wire [511:0]m01_couplers_to_axi_interconnect_0_RDATA; + wire [63:0]m01_couplers_to_axi_interconnect_0_RDATA; + wire [3:0]m01_couplers_to_axi_interconnect_0_RID; wire m01_couplers_to_axi_interconnect_0_RLAST; wire m01_couplers_to_axi_interconnect_0_RREADY; wire [1:0]m01_couplers_to_axi_interconnect_0_RRESP; wire m01_couplers_to_axi_interconnect_0_RVALID; - wire [511:0]m01_couplers_to_axi_interconnect_0_WDATA; + wire [63:0]m01_couplers_to_axi_interconnect_0_WDATA; wire m01_couplers_to_axi_interconnect_0_WLAST; wire m01_couplers_to_axi_interconnect_0_WREADY; - wire [63:0]m01_couplers_to_axi_interconnect_0_WSTRB; + wire [7:0]m01_couplers_to_axi_interconnect_0_WSTRB; wire m01_couplers_to_axi_interconnect_0_WVALID; - wire [31:0]m02_couplers_to_axi_interconnect_0_ARADDR; + wire [63:0]m02_couplers_to_axi_interconnect_0_ARADDR; + wire [1:0]m02_couplers_to_axi_interconnect_0_ARBURST; + wire [3:0]m02_couplers_to_axi_interconnect_0_ARCACHE; + wire [3:0]m02_couplers_to_axi_interconnect_0_ARID; + wire [7:0]m02_couplers_to_axi_interconnect_0_ARLEN; + wire m02_couplers_to_axi_interconnect_0_ARLOCK; + wire [2:0]m02_couplers_to_axi_interconnect_0_ARPROT; wire m02_couplers_to_axi_interconnect_0_ARREADY; + wire [2:0]m02_couplers_to_axi_interconnect_0_ARSIZE; wire m02_couplers_to_axi_interconnect_0_ARVALID; - wire [31:0]m02_couplers_to_axi_interconnect_0_AWADDR; + wire [63:0]m02_couplers_to_axi_interconnect_0_AWADDR; + wire [1:0]m02_couplers_to_axi_interconnect_0_AWBURST; + wire [3:0]m02_couplers_to_axi_interconnect_0_AWCACHE; + wire [3:0]m02_couplers_to_axi_interconnect_0_AWID; + wire [7:0]m02_couplers_to_axi_interconnect_0_AWLEN; + wire m02_couplers_to_axi_interconnect_0_AWLOCK; + wire [2:0]m02_couplers_to_axi_interconnect_0_AWPROT; wire m02_couplers_to_axi_interconnect_0_AWREADY; + wire [2:0]m02_couplers_to_axi_interconnect_0_AWSIZE; wire m02_couplers_to_axi_interconnect_0_AWVALID; + wire [3:0]m02_couplers_to_axi_interconnect_0_BID; wire m02_couplers_to_axi_interconnect_0_BREADY; wire [1:0]m02_couplers_to_axi_interconnect_0_BRESP; wire m02_couplers_to_axi_interconnect_0_BVALID; - wire [31:0]m02_couplers_to_axi_interconnect_0_RDATA; + wire [63:0]m02_couplers_to_axi_interconnect_0_RDATA; + wire [3:0]m02_couplers_to_axi_interconnect_0_RID; + wire m02_couplers_to_axi_interconnect_0_RLAST; wire m02_couplers_to_axi_interconnect_0_RREADY; wire [1:0]m02_couplers_to_axi_interconnect_0_RRESP; wire m02_couplers_to_axi_interconnect_0_RVALID; - wire [31:0]m02_couplers_to_axi_interconnect_0_WDATA; + wire [63:0]m02_couplers_to_axi_interconnect_0_WDATA; + wire m02_couplers_to_axi_interconnect_0_WLAST; wire m02_couplers_to_axi_interconnect_0_WREADY; + wire [7:0]m02_couplers_to_axi_interconnect_0_WSTRB; wire m02_couplers_to_axi_interconnect_0_WVALID; - wire [30:0]m03_couplers_to_axi_interconnect_0_ARADDR; - wire [1:0]m03_couplers_to_axi_interconnect_0_ARBURST; - wire [3:0]m03_couplers_to_axi_interconnect_0_ARCACHE; - wire [7:0]m03_couplers_to_axi_interconnect_0_ARLEN; - wire m03_couplers_to_axi_interconnect_0_ARLOCK; - wire [2:0]m03_couplers_to_axi_interconnect_0_ARPROT; - wire [3:0]m03_couplers_to_axi_interconnect_0_ARQOS; - wire m03_couplers_to_axi_interconnect_0_ARREADY; - wire [2:0]m03_couplers_to_axi_interconnect_0_ARSIZE; - wire m03_couplers_to_axi_interconnect_0_ARVALID; - wire [30:0]m03_couplers_to_axi_interconnect_0_AWADDR; - wire [1:0]m03_couplers_to_axi_interconnect_0_AWBURST; - wire [3:0]m03_couplers_to_axi_interconnect_0_AWCACHE; - wire [7:0]m03_couplers_to_axi_interconnect_0_AWLEN; - wire m03_couplers_to_axi_interconnect_0_AWLOCK; - wire [2:0]m03_couplers_to_axi_interconnect_0_AWPROT; - wire [3:0]m03_couplers_to_axi_interconnect_0_AWQOS; - wire m03_couplers_to_axi_interconnect_0_AWREADY; - wire [2:0]m03_couplers_to_axi_interconnect_0_AWSIZE; - wire m03_couplers_to_axi_interconnect_0_AWVALID; - wire m03_couplers_to_axi_interconnect_0_BREADY; - wire [1:0]m03_couplers_to_axi_interconnect_0_BRESP; - wire m03_couplers_to_axi_interconnect_0_BVALID; - wire [511:0]m03_couplers_to_axi_interconnect_0_RDATA; - wire m03_couplers_to_axi_interconnect_0_RLAST; - wire m03_couplers_to_axi_interconnect_0_RREADY; - wire [1:0]m03_couplers_to_axi_interconnect_0_RRESP; - wire m03_couplers_to_axi_interconnect_0_RVALID; - wire [511:0]m03_couplers_to_axi_interconnect_0_WDATA; - wire m03_couplers_to_axi_interconnect_0_WLAST; - wire m03_couplers_to_axi_interconnect_0_WREADY; - wire [63:0]m03_couplers_to_axi_interconnect_0_WSTRB; - wire m03_couplers_to_axi_interconnect_0_WVALID; - wire [12:0]m04_couplers_to_axi_interconnect_0_ARADDR; - wire [1:0]m04_couplers_to_axi_interconnect_0_ARBURST; - wire [3:0]m04_couplers_to_axi_interconnect_0_ARCACHE; - wire [7:0]m04_couplers_to_axi_interconnect_0_ARLEN; - wire m04_couplers_to_axi_interconnect_0_ARLOCK; - wire [2:0]m04_couplers_to_axi_interconnect_0_ARPROT; - wire m04_couplers_to_axi_interconnect_0_ARREADY; - wire [2:0]m04_couplers_to_axi_interconnect_0_ARSIZE; - wire m04_couplers_to_axi_interconnect_0_ARVALID; - wire [12:0]m04_couplers_to_axi_interconnect_0_AWADDR; - wire [1:0]m04_couplers_to_axi_interconnect_0_AWBURST; - wire [3:0]m04_couplers_to_axi_interconnect_0_AWCACHE; - wire [7:0]m04_couplers_to_axi_interconnect_0_AWLEN; - wire m04_couplers_to_axi_interconnect_0_AWLOCK; - wire [2:0]m04_couplers_to_axi_interconnect_0_AWPROT; - wire m04_couplers_to_axi_interconnect_0_AWREADY; - wire [2:0]m04_couplers_to_axi_interconnect_0_AWSIZE; - wire m04_couplers_to_axi_interconnect_0_AWVALID; - wire m04_couplers_to_axi_interconnect_0_BREADY; - wire [1:0]m04_couplers_to_axi_interconnect_0_BRESP; - wire m04_couplers_to_axi_interconnect_0_BVALID; - wire [31:0]m04_couplers_to_axi_interconnect_0_RDATA; - wire m04_couplers_to_axi_interconnect_0_RLAST; - wire m04_couplers_to_axi_interconnect_0_RREADY; - wire [1:0]m04_couplers_to_axi_interconnect_0_RRESP; - wire m04_couplers_to_axi_interconnect_0_RVALID; - wire [31:0]m04_couplers_to_axi_interconnect_0_WDATA; - wire m04_couplers_to_axi_interconnect_0_WLAST; - wire m04_couplers_to_axi_interconnect_0_WREADY; - wire [3:0]m04_couplers_to_axi_interconnect_0_WSTRB; - wire m04_couplers_to_axi_interconnect_0_WVALID; wire [63:0]s00_couplers_to_xbar_ARADDR; wire [1:0]s00_couplers_to_xbar_ARBURST; wire [3:0]s00_couplers_to_xbar_ARCACHE; + wire [3:0]s00_couplers_to_xbar_ARID; wire [7:0]s00_couplers_to_xbar_ARLEN; wire [0:0]s00_couplers_to_xbar_ARLOCK; wire [2:0]s00_couplers_to_xbar_ARPROT; - wire [3:0]s00_couplers_to_xbar_ARQOS; wire [0:0]s00_couplers_to_xbar_ARREADY; wire [2:0]s00_couplers_to_xbar_ARSIZE; - wire s00_couplers_to_xbar_ARVALID; + wire [0:0]s00_couplers_to_xbar_ARVALID; wire [63:0]s00_couplers_to_xbar_AWADDR; wire [1:0]s00_couplers_to_xbar_AWBURST; wire [3:0]s00_couplers_to_xbar_AWCACHE; + wire [3:0]s00_couplers_to_xbar_AWID; wire [7:0]s00_couplers_to_xbar_AWLEN; wire [0:0]s00_couplers_to_xbar_AWLOCK; wire [2:0]s00_couplers_to_xbar_AWPROT; - wire [3:0]s00_couplers_to_xbar_AWQOS; wire [0:0]s00_couplers_to_xbar_AWREADY; wire [2:0]s00_couplers_to_xbar_AWSIZE; - wire s00_couplers_to_xbar_AWVALID; - wire s00_couplers_to_xbar_BREADY; + wire [0:0]s00_couplers_to_xbar_AWVALID; + wire [3:0]s00_couplers_to_xbar_BID; + wire [0:0]s00_couplers_to_xbar_BREADY; wire [1:0]s00_couplers_to_xbar_BRESP; wire [0:0]s00_couplers_to_xbar_BVALID; - wire [511:0]s00_couplers_to_xbar_RDATA; + wire [63:0]s00_couplers_to_xbar_RDATA; + wire [3:0]s00_couplers_to_xbar_RID; wire [0:0]s00_couplers_to_xbar_RLAST; - wire s00_couplers_to_xbar_RREADY; + wire [0:0]s00_couplers_to_xbar_RREADY; wire [1:0]s00_couplers_to_xbar_RRESP; wire [0:0]s00_couplers_to_xbar_RVALID; - wire [511:0]s00_couplers_to_xbar_WDATA; - wire s00_couplers_to_xbar_WLAST; + wire [63:0]s00_couplers_to_xbar_WDATA; + wire [0:0]s00_couplers_to_xbar_WLAST; wire [0:0]s00_couplers_to_xbar_WREADY; - wire [63:0]s00_couplers_to_xbar_WSTRB; - wire s00_couplers_to_xbar_WVALID; + wire [7:0]s00_couplers_to_xbar_WSTRB; + wire [0:0]s00_couplers_to_xbar_WVALID; wire [63:0]xbar_to_m00_couplers_ARADDR; wire [1:0]xbar_to_m00_couplers_ARBURST; wire [3:0]xbar_to_m00_couplers_ARCACHE; + wire [3:0]xbar_to_m00_couplers_ARID; wire [7:0]xbar_to_m00_couplers_ARLEN; wire [0:0]xbar_to_m00_couplers_ARLOCK; wire [2:0]xbar_to_m00_couplers_ARPROT; @@ -1370,6 +1335,7 @@ module Top_axi_interconnect_0_0 wire [63:0]xbar_to_m00_couplers_AWADDR; wire [1:0]xbar_to_m00_couplers_AWBURST; wire [3:0]xbar_to_m00_couplers_AWCACHE; + wire [3:0]xbar_to_m00_couplers_AWID; wire [7:0]xbar_to_m00_couplers_AWLEN; wire [0:0]xbar_to_m00_couplers_AWLOCK; wire [2:0]xbar_to_m00_couplers_AWPROT; @@ -1378,22 +1344,25 @@ module Top_axi_interconnect_0_0 wire [3:0]xbar_to_m00_couplers_AWREGION; wire [2:0]xbar_to_m00_couplers_AWSIZE; wire [0:0]xbar_to_m00_couplers_AWVALID; + wire [3:0]xbar_to_m00_couplers_BID; wire [0:0]xbar_to_m00_couplers_BREADY; wire [1:0]xbar_to_m00_couplers_BRESP; wire xbar_to_m00_couplers_BVALID; - wire [511:0]xbar_to_m00_couplers_RDATA; + wire [63:0]xbar_to_m00_couplers_RDATA; + wire [3:0]xbar_to_m00_couplers_RID; wire xbar_to_m00_couplers_RLAST; wire [0:0]xbar_to_m00_couplers_RREADY; wire [1:0]xbar_to_m00_couplers_RRESP; wire xbar_to_m00_couplers_RVALID; - wire [511:0]xbar_to_m00_couplers_WDATA; + wire [63:0]xbar_to_m00_couplers_WDATA; wire [0:0]xbar_to_m00_couplers_WLAST; wire xbar_to_m00_couplers_WREADY; - wire [63:0]xbar_to_m00_couplers_WSTRB; + wire [7:0]xbar_to_m00_couplers_WSTRB; wire [0:0]xbar_to_m00_couplers_WVALID; wire [127:64]xbar_to_m01_couplers_ARADDR; wire [3:2]xbar_to_m01_couplers_ARBURST; wire [7:4]xbar_to_m01_couplers_ARCACHE; + wire [7:4]xbar_to_m01_couplers_ARID; wire [15:8]xbar_to_m01_couplers_ARLEN; wire [1:1]xbar_to_m01_couplers_ARLOCK; wire [5:3]xbar_to_m01_couplers_ARPROT; @@ -1405,6 +1374,7 @@ module Top_axi_interconnect_0_0 wire [127:64]xbar_to_m01_couplers_AWADDR; wire [3:2]xbar_to_m01_couplers_AWBURST; wire [7:4]xbar_to_m01_couplers_AWCACHE; + wire [7:4]xbar_to_m01_couplers_AWID; wire [15:8]xbar_to_m01_couplers_AWLEN; wire [1:1]xbar_to_m01_couplers_AWLOCK; wire [5:3]xbar_to_m01_couplers_AWPROT; @@ -1413,195 +1383,1928 @@ module Top_axi_interconnect_0_0 wire [7:4]xbar_to_m01_couplers_AWREGION; wire [5:3]xbar_to_m01_couplers_AWSIZE; wire [1:1]xbar_to_m01_couplers_AWVALID; + wire [3:0]xbar_to_m01_couplers_BID; wire [1:1]xbar_to_m01_couplers_BREADY; wire [1:0]xbar_to_m01_couplers_BRESP; wire xbar_to_m01_couplers_BVALID; - wire [511:0]xbar_to_m01_couplers_RDATA; + wire [63:0]xbar_to_m01_couplers_RDATA; + wire [3:0]xbar_to_m01_couplers_RID; wire xbar_to_m01_couplers_RLAST; wire [1:1]xbar_to_m01_couplers_RREADY; wire [1:0]xbar_to_m01_couplers_RRESP; wire xbar_to_m01_couplers_RVALID; - wire [1023:512]xbar_to_m01_couplers_WDATA; + wire [127:64]xbar_to_m01_couplers_WDATA; wire [1:1]xbar_to_m01_couplers_WLAST; wire xbar_to_m01_couplers_WREADY; - wire [127:64]xbar_to_m01_couplers_WSTRB; + wire [15:8]xbar_to_m01_couplers_WSTRB; wire [1:1]xbar_to_m01_couplers_WVALID; wire [191:128]xbar_to_m02_couplers_ARADDR; wire [5:4]xbar_to_m02_couplers_ARBURST; wire [11:8]xbar_to_m02_couplers_ARCACHE; + wire [11:8]xbar_to_m02_couplers_ARID; wire [23:16]xbar_to_m02_couplers_ARLEN; wire [2:2]xbar_to_m02_couplers_ARLOCK; wire [8:6]xbar_to_m02_couplers_ARPROT; - wire [11:8]xbar_to_m02_couplers_ARQOS; wire xbar_to_m02_couplers_ARREADY; - wire [11:8]xbar_to_m02_couplers_ARREGION; wire [8:6]xbar_to_m02_couplers_ARSIZE; wire [2:2]xbar_to_m02_couplers_ARVALID; wire [191:128]xbar_to_m02_couplers_AWADDR; wire [5:4]xbar_to_m02_couplers_AWBURST; wire [11:8]xbar_to_m02_couplers_AWCACHE; + wire [11:8]xbar_to_m02_couplers_AWID; wire [23:16]xbar_to_m02_couplers_AWLEN; wire [2:2]xbar_to_m02_couplers_AWLOCK; wire [8:6]xbar_to_m02_couplers_AWPROT; - wire [11:8]xbar_to_m02_couplers_AWQOS; wire xbar_to_m02_couplers_AWREADY; - wire [11:8]xbar_to_m02_couplers_AWREGION; wire [8:6]xbar_to_m02_couplers_AWSIZE; wire [2:2]xbar_to_m02_couplers_AWVALID; + wire [3:0]xbar_to_m02_couplers_BID; wire [2:2]xbar_to_m02_couplers_BREADY; wire [1:0]xbar_to_m02_couplers_BRESP; wire xbar_to_m02_couplers_BVALID; - wire [511:0]xbar_to_m02_couplers_RDATA; + wire [63:0]xbar_to_m02_couplers_RDATA; + wire [3:0]xbar_to_m02_couplers_RID; wire xbar_to_m02_couplers_RLAST; wire [2:2]xbar_to_m02_couplers_RREADY; wire [1:0]xbar_to_m02_couplers_RRESP; wire xbar_to_m02_couplers_RVALID; - wire [1535:1024]xbar_to_m02_couplers_WDATA; + wire [191:128]xbar_to_m02_couplers_WDATA; wire [2:2]xbar_to_m02_couplers_WLAST; wire xbar_to_m02_couplers_WREADY; - wire [191:128]xbar_to_m02_couplers_WSTRB; + wire [23:16]xbar_to_m02_couplers_WSTRB; wire [2:2]xbar_to_m02_couplers_WVALID; - wire [255:192]xbar_to_m03_couplers_ARADDR; - wire [7:6]xbar_to_m03_couplers_ARBURST; - wire [15:12]xbar_to_m03_couplers_ARCACHE; - wire [31:24]xbar_to_m03_couplers_ARLEN; - wire [3:3]xbar_to_m03_couplers_ARLOCK; - wire [11:9]xbar_to_m03_couplers_ARPROT; - wire [15:12]xbar_to_m03_couplers_ARQOS; - wire xbar_to_m03_couplers_ARREADY; - wire [15:12]xbar_to_m03_couplers_ARREGION; - wire [11:9]xbar_to_m03_couplers_ARSIZE; - wire [3:3]xbar_to_m03_couplers_ARVALID; - wire [255:192]xbar_to_m03_couplers_AWADDR; - wire [7:6]xbar_to_m03_couplers_AWBURST; - wire [15:12]xbar_to_m03_couplers_AWCACHE; - wire [31:24]xbar_to_m03_couplers_AWLEN; - wire [3:3]xbar_to_m03_couplers_AWLOCK; - wire [11:9]xbar_to_m03_couplers_AWPROT; - wire [15:12]xbar_to_m03_couplers_AWQOS; - wire xbar_to_m03_couplers_AWREADY; - wire [15:12]xbar_to_m03_couplers_AWREGION; - wire [11:9]xbar_to_m03_couplers_AWSIZE; - wire [3:3]xbar_to_m03_couplers_AWVALID; - wire [3:3]xbar_to_m03_couplers_BREADY; - wire [1:0]xbar_to_m03_couplers_BRESP; - wire xbar_to_m03_couplers_BVALID; - wire [511:0]xbar_to_m03_couplers_RDATA; - wire xbar_to_m03_couplers_RLAST; - wire [3:3]xbar_to_m03_couplers_RREADY; - wire [1:0]xbar_to_m03_couplers_RRESP; - wire xbar_to_m03_couplers_RVALID; - wire [2047:1536]xbar_to_m03_couplers_WDATA; - wire [3:3]xbar_to_m03_couplers_WLAST; - wire xbar_to_m03_couplers_WREADY; - wire [255:192]xbar_to_m03_couplers_WSTRB; - wire [3:3]xbar_to_m03_couplers_WVALID; - wire [319:256]xbar_to_m04_couplers_ARADDR; - wire [9:8]xbar_to_m04_couplers_ARBURST; - wire [19:16]xbar_to_m04_couplers_ARCACHE; - wire [39:32]xbar_to_m04_couplers_ARLEN; - wire [4:4]xbar_to_m04_couplers_ARLOCK; - wire [14:12]xbar_to_m04_couplers_ARPROT; - wire [19:16]xbar_to_m04_couplers_ARQOS; - wire xbar_to_m04_couplers_ARREADY; - wire [19:16]xbar_to_m04_couplers_ARREGION; - wire [14:12]xbar_to_m04_couplers_ARSIZE; - wire [4:4]xbar_to_m04_couplers_ARVALID; - wire [319:256]xbar_to_m04_couplers_AWADDR; - wire [9:8]xbar_to_m04_couplers_AWBURST; - wire [19:16]xbar_to_m04_couplers_AWCACHE; - wire [39:32]xbar_to_m04_couplers_AWLEN; - wire [4:4]xbar_to_m04_couplers_AWLOCK; - wire [14:12]xbar_to_m04_couplers_AWPROT; - wire [19:16]xbar_to_m04_couplers_AWQOS; - wire xbar_to_m04_couplers_AWREADY; - wire [19:16]xbar_to_m04_couplers_AWREGION; - wire [14:12]xbar_to_m04_couplers_AWSIZE; - wire [4:4]xbar_to_m04_couplers_AWVALID; - wire [4:4]xbar_to_m04_couplers_BREADY; - wire [1:0]xbar_to_m04_couplers_BRESP; - wire xbar_to_m04_couplers_BVALID; - wire [511:0]xbar_to_m04_couplers_RDATA; - wire xbar_to_m04_couplers_RLAST; - wire [4:4]xbar_to_m04_couplers_RREADY; - wire [1:0]xbar_to_m04_couplers_RRESP; - wire xbar_to_m04_couplers_RVALID; - wire [2559:2048]xbar_to_m04_couplers_WDATA; - wire [4:4]xbar_to_m04_couplers_WLAST; - wire xbar_to_m04_couplers_WREADY; - wire [319:256]xbar_to_m04_couplers_WSTRB; - wire [4:4]xbar_to_m04_couplers_WVALID; + assign M00_ACLK_1 = M00_ACLK; + assign M00_ARESETN_1 = M00_ARESETN[7:0]; + assign M00_AXI_araddr[30:0] = m00_couplers_to_axi_interconnect_0_ARADDR; + assign M00_AXI_arburst[1:0] = m00_couplers_to_axi_interconnect_0_ARBURST; + assign M00_AXI_arcache[3:0] = m00_couplers_to_axi_interconnect_0_ARCACHE; + assign M00_AXI_arid[3:0] = m00_couplers_to_axi_interconnect_0_ARID; + assign M00_AXI_arlen[7:0] = m00_couplers_to_axi_interconnect_0_ARLEN; + assign M00_AXI_arlock = m00_couplers_to_axi_interconnect_0_ARLOCK; + assign M00_AXI_arprot[2:0] = m00_couplers_to_axi_interconnect_0_ARPROT; + assign M00_AXI_arqos[3:0] = m00_couplers_to_axi_interconnect_0_ARQOS; + assign M00_AXI_arsize[2:0] = m00_couplers_to_axi_interconnect_0_ARSIZE; + assign M00_AXI_arvalid = m00_couplers_to_axi_interconnect_0_ARVALID; + assign M00_AXI_awaddr[30:0] = m00_couplers_to_axi_interconnect_0_AWADDR; + assign M00_AXI_awburst[1:0] = m00_couplers_to_axi_interconnect_0_AWBURST; + assign M00_AXI_awcache[3:0] = m00_couplers_to_axi_interconnect_0_AWCACHE; + assign M00_AXI_awid[3:0] = m00_couplers_to_axi_interconnect_0_AWID; + assign M00_AXI_awlen[7:0] = m00_couplers_to_axi_interconnect_0_AWLEN; + assign M00_AXI_awlock = m00_couplers_to_axi_interconnect_0_AWLOCK; + assign M00_AXI_awprot[2:0] = m00_couplers_to_axi_interconnect_0_AWPROT; + assign M00_AXI_awqos[3:0] = m00_couplers_to_axi_interconnect_0_AWQOS; + assign M00_AXI_awsize[2:0] = m00_couplers_to_axi_interconnect_0_AWSIZE; + assign M00_AXI_awvalid = m00_couplers_to_axi_interconnect_0_AWVALID; + assign M00_AXI_bready = m00_couplers_to_axi_interconnect_0_BREADY; + assign M00_AXI_rready = m00_couplers_to_axi_interconnect_0_RREADY; + assign M00_AXI_wdata[63:0] = m00_couplers_to_axi_interconnect_0_WDATA; + assign M00_AXI_wlast = m00_couplers_to_axi_interconnect_0_WLAST; + assign M00_AXI_wstrb[7:0] = m00_couplers_to_axi_interconnect_0_WSTRB; + assign M00_AXI_wvalid = m00_couplers_to_axi_interconnect_0_WVALID; + assign M01_ACLK_1 = M01_ACLK; + assign M01_ARESETN_1 = M01_ARESETN[7:0]; + assign M01_AXI_araddr[30:0] = m01_couplers_to_axi_interconnect_0_ARADDR; + assign M01_AXI_arburst[1:0] = m01_couplers_to_axi_interconnect_0_ARBURST; + assign M01_AXI_arcache[3:0] = m01_couplers_to_axi_interconnect_0_ARCACHE; + assign M01_AXI_arid[3:0] = m01_couplers_to_axi_interconnect_0_ARID; + assign M01_AXI_arlen[7:0] = m01_couplers_to_axi_interconnect_0_ARLEN; + assign M01_AXI_arlock = m01_couplers_to_axi_interconnect_0_ARLOCK; + assign M01_AXI_arprot[2:0] = m01_couplers_to_axi_interconnect_0_ARPROT; + assign M01_AXI_arqos[3:0] = m01_couplers_to_axi_interconnect_0_ARQOS; + assign M01_AXI_arsize[2:0] = m01_couplers_to_axi_interconnect_0_ARSIZE; + assign M01_AXI_arvalid = m01_couplers_to_axi_interconnect_0_ARVALID; + assign M01_AXI_awaddr[30:0] = m01_couplers_to_axi_interconnect_0_AWADDR; + assign M01_AXI_awburst[1:0] = m01_couplers_to_axi_interconnect_0_AWBURST; + assign M01_AXI_awcache[3:0] = m01_couplers_to_axi_interconnect_0_AWCACHE; + assign M01_AXI_awid[3:0] = m01_couplers_to_axi_interconnect_0_AWID; + assign M01_AXI_awlen[7:0] = m01_couplers_to_axi_interconnect_0_AWLEN; + assign M01_AXI_awlock = m01_couplers_to_axi_interconnect_0_AWLOCK; + assign M01_AXI_awprot[2:0] = m01_couplers_to_axi_interconnect_0_AWPROT; + assign M01_AXI_awqos[3:0] = m01_couplers_to_axi_interconnect_0_AWQOS; + assign M01_AXI_awsize[2:0] = m01_couplers_to_axi_interconnect_0_AWSIZE; + assign M01_AXI_awvalid = m01_couplers_to_axi_interconnect_0_AWVALID; + assign M01_AXI_bready = m01_couplers_to_axi_interconnect_0_BREADY; + assign M01_AXI_rready = m01_couplers_to_axi_interconnect_0_RREADY; + assign M01_AXI_wdata[63:0] = m01_couplers_to_axi_interconnect_0_WDATA; + assign M01_AXI_wlast = m01_couplers_to_axi_interconnect_0_WLAST; + assign M01_AXI_wstrb[7:0] = m01_couplers_to_axi_interconnect_0_WSTRB; + assign M01_AXI_wvalid = m01_couplers_to_axi_interconnect_0_WVALID; + assign M02_ACLK_1 = M02_ACLK; + assign M02_ARESETN_1 = M02_ARESETN[7:0]; + assign M02_AXI_araddr[63:0] = m02_couplers_to_axi_interconnect_0_ARADDR; + assign M02_AXI_arburst[1:0] = m02_couplers_to_axi_interconnect_0_ARBURST; + assign M02_AXI_arcache[3:0] = m02_couplers_to_axi_interconnect_0_ARCACHE; + assign M02_AXI_arid[3:0] = m02_couplers_to_axi_interconnect_0_ARID; + assign M02_AXI_arlen[7:0] = m02_couplers_to_axi_interconnect_0_ARLEN; + assign M02_AXI_arlock = m02_couplers_to_axi_interconnect_0_ARLOCK; + assign M02_AXI_arprot[2:0] = m02_couplers_to_axi_interconnect_0_ARPROT; + assign M02_AXI_arsize[2:0] = m02_couplers_to_axi_interconnect_0_ARSIZE; + assign M02_AXI_arvalid = m02_couplers_to_axi_interconnect_0_ARVALID; + assign M02_AXI_awaddr[63:0] = m02_couplers_to_axi_interconnect_0_AWADDR; + assign M02_AXI_awburst[1:0] = m02_couplers_to_axi_interconnect_0_AWBURST; + assign M02_AXI_awcache[3:0] = m02_couplers_to_axi_interconnect_0_AWCACHE; + assign M02_AXI_awid[3:0] = m02_couplers_to_axi_interconnect_0_AWID; + assign M02_AXI_awlen[7:0] = m02_couplers_to_axi_interconnect_0_AWLEN; + assign M02_AXI_awlock = m02_couplers_to_axi_interconnect_0_AWLOCK; + assign M02_AXI_awprot[2:0] = m02_couplers_to_axi_interconnect_0_AWPROT; + assign M02_AXI_awsize[2:0] = m02_couplers_to_axi_interconnect_0_AWSIZE; + assign M02_AXI_awvalid = m02_couplers_to_axi_interconnect_0_AWVALID; + assign M02_AXI_bready = m02_couplers_to_axi_interconnect_0_BREADY; + assign M02_AXI_rready = m02_couplers_to_axi_interconnect_0_RREADY; + assign M02_AXI_wdata[63:0] = m02_couplers_to_axi_interconnect_0_WDATA; + assign M02_AXI_wlast = m02_couplers_to_axi_interconnect_0_WLAST; + assign M02_AXI_wstrb[7:0] = m02_couplers_to_axi_interconnect_0_WSTRB; + assign M02_AXI_wvalid = m02_couplers_to_axi_interconnect_0_WVALID; + assign S00_ACLK_1 = S00_ACLK; + assign S00_ARESETN_1 = S00_ARESETN; + assign S00_AXI_arready[0] = axi_interconnect_0_to_s00_couplers_ARREADY; + assign S00_AXI_awready[0] = axi_interconnect_0_to_s00_couplers_AWREADY; + assign S00_AXI_bid[3:0] = axi_interconnect_0_to_s00_couplers_BID; + assign S00_AXI_bresp[1:0] = axi_interconnect_0_to_s00_couplers_BRESP; + assign S00_AXI_bvalid[0] = axi_interconnect_0_to_s00_couplers_BVALID; + assign S00_AXI_rdata[63:0] = axi_interconnect_0_to_s00_couplers_RDATA; + assign S00_AXI_rid[3:0] = axi_interconnect_0_to_s00_couplers_RID; + assign S00_AXI_rlast[0] = axi_interconnect_0_to_s00_couplers_RLAST; + assign S00_AXI_rresp[1:0] = axi_interconnect_0_to_s00_couplers_RRESP; + assign S00_AXI_rvalid[0] = axi_interconnect_0_to_s00_couplers_RVALID; + assign S00_AXI_wready[0] = axi_interconnect_0_to_s00_couplers_WREADY; + assign axi_interconnect_0_ACLK_net = ACLK; + assign axi_interconnect_0_ARESETN_net = ARESETN; + assign axi_interconnect_0_to_s00_couplers_ARADDR = S00_AXI_araddr[63:0]; + assign axi_interconnect_0_to_s00_couplers_ARBURST = S00_AXI_arburst[1:0]; + assign axi_interconnect_0_to_s00_couplers_ARCACHE = S00_AXI_arcache[3:0]; + assign axi_interconnect_0_to_s00_couplers_ARID = S00_AXI_arid[3:0]; + assign axi_interconnect_0_to_s00_couplers_ARLEN = S00_AXI_arlen[7:0]; + assign axi_interconnect_0_to_s00_couplers_ARLOCK = S00_AXI_arlock[0]; + assign axi_interconnect_0_to_s00_couplers_ARPROT = S00_AXI_arprot[2:0]; + assign axi_interconnect_0_to_s00_couplers_ARSIZE = S00_AXI_arsize[2:0]; + assign axi_interconnect_0_to_s00_couplers_ARVALID = S00_AXI_arvalid[0]; + assign axi_interconnect_0_to_s00_couplers_AWADDR = S00_AXI_awaddr[63:0]; + assign axi_interconnect_0_to_s00_couplers_AWBURST = S00_AXI_awburst[1:0]; + assign axi_interconnect_0_to_s00_couplers_AWCACHE = S00_AXI_awcache[3:0]; + assign axi_interconnect_0_to_s00_couplers_AWID = S00_AXI_awid[3:0]; + assign axi_interconnect_0_to_s00_couplers_AWLEN = S00_AXI_awlen[7:0]; + assign axi_interconnect_0_to_s00_couplers_AWLOCK = S00_AXI_awlock[0]; + assign axi_interconnect_0_to_s00_couplers_AWPROT = S00_AXI_awprot[2:0]; + assign axi_interconnect_0_to_s00_couplers_AWSIZE = S00_AXI_awsize[2:0]; + assign axi_interconnect_0_to_s00_couplers_AWVALID = S00_AXI_awvalid[0]; + assign axi_interconnect_0_to_s00_couplers_BREADY = S00_AXI_bready[0]; + assign axi_interconnect_0_to_s00_couplers_RREADY = S00_AXI_rready[0]; + assign axi_interconnect_0_to_s00_couplers_WDATA = S00_AXI_wdata[63:0]; + assign axi_interconnect_0_to_s00_couplers_WLAST = S00_AXI_wlast[0]; + assign axi_interconnect_0_to_s00_couplers_WSTRB = S00_AXI_wstrb[7:0]; + assign axi_interconnect_0_to_s00_couplers_WVALID = S00_AXI_wvalid[0]; + assign m00_couplers_to_axi_interconnect_0_ARREADY = M00_AXI_arready; + assign m00_couplers_to_axi_interconnect_0_AWREADY = M00_AXI_awready; + assign m00_couplers_to_axi_interconnect_0_BID = M00_AXI_bid[3:0]; + assign m00_couplers_to_axi_interconnect_0_BRESP = M00_AXI_bresp[1:0]; + assign m00_couplers_to_axi_interconnect_0_BVALID = M00_AXI_bvalid; + assign m00_couplers_to_axi_interconnect_0_RDATA = M00_AXI_rdata[63:0]; + assign m00_couplers_to_axi_interconnect_0_RID = M00_AXI_rid[3:0]; + assign m00_couplers_to_axi_interconnect_0_RLAST = M00_AXI_rlast; + assign m00_couplers_to_axi_interconnect_0_RRESP = M00_AXI_rresp[1:0]; + assign m00_couplers_to_axi_interconnect_0_RVALID = M00_AXI_rvalid; + assign m00_couplers_to_axi_interconnect_0_WREADY = M00_AXI_wready; + assign m01_couplers_to_axi_interconnect_0_ARREADY = M01_AXI_arready; + assign m01_couplers_to_axi_interconnect_0_AWREADY = M01_AXI_awready; + assign m01_couplers_to_axi_interconnect_0_BID = M01_AXI_bid[3:0]; + assign m01_couplers_to_axi_interconnect_0_BRESP = M01_AXI_bresp[1:0]; + assign m01_couplers_to_axi_interconnect_0_BVALID = M01_AXI_bvalid; + assign m01_couplers_to_axi_interconnect_0_RDATA = M01_AXI_rdata[63:0]; + assign m01_couplers_to_axi_interconnect_0_RID = M01_AXI_rid[3:0]; + assign m01_couplers_to_axi_interconnect_0_RLAST = M01_AXI_rlast; + assign m01_couplers_to_axi_interconnect_0_RRESP = M01_AXI_rresp[1:0]; + assign m01_couplers_to_axi_interconnect_0_RVALID = M01_AXI_rvalid; + assign m01_couplers_to_axi_interconnect_0_WREADY = M01_AXI_wready; + assign m02_couplers_to_axi_interconnect_0_ARREADY = M02_AXI_arready; + assign m02_couplers_to_axi_interconnect_0_AWREADY = M02_AXI_awready; + assign m02_couplers_to_axi_interconnect_0_BID = M02_AXI_bid[3:0]; + assign m02_couplers_to_axi_interconnect_0_BRESP = M02_AXI_bresp[1:0]; + assign m02_couplers_to_axi_interconnect_0_BVALID = M02_AXI_bvalid; + assign m02_couplers_to_axi_interconnect_0_RDATA = M02_AXI_rdata[63:0]; + assign m02_couplers_to_axi_interconnect_0_RID = M02_AXI_rid[3:0]; + assign m02_couplers_to_axi_interconnect_0_RLAST = M02_AXI_rlast; + assign m02_couplers_to_axi_interconnect_0_RRESP = M02_AXI_rresp[1:0]; + assign m02_couplers_to_axi_interconnect_0_RVALID = M02_AXI_rvalid; + assign m02_couplers_to_axi_interconnect_0_WREADY = M02_AXI_wready; + m00_couplers_imp_JY9FDQ m00_couplers + (.M_ACLK(M00_ACLK_1), + .M_ARESETN(M00_ARESETN_1), + .M_AXI_araddr(m00_couplers_to_axi_interconnect_0_ARADDR), + .M_AXI_arburst(m00_couplers_to_axi_interconnect_0_ARBURST), + .M_AXI_arcache(m00_couplers_to_axi_interconnect_0_ARCACHE), + .M_AXI_arid(m00_couplers_to_axi_interconnect_0_ARID), + .M_AXI_arlen(m00_couplers_to_axi_interconnect_0_ARLEN), + .M_AXI_arlock(m00_couplers_to_axi_interconnect_0_ARLOCK), + .M_AXI_arprot(m00_couplers_to_axi_interconnect_0_ARPROT), + .M_AXI_arqos(m00_couplers_to_axi_interconnect_0_ARQOS), + .M_AXI_arready(m00_couplers_to_axi_interconnect_0_ARREADY), + .M_AXI_arsize(m00_couplers_to_axi_interconnect_0_ARSIZE), + .M_AXI_arvalid(m00_couplers_to_axi_interconnect_0_ARVALID), + .M_AXI_awaddr(m00_couplers_to_axi_interconnect_0_AWADDR), + .M_AXI_awburst(m00_couplers_to_axi_interconnect_0_AWBURST), + .M_AXI_awcache(m00_couplers_to_axi_interconnect_0_AWCACHE), + .M_AXI_awid(m00_couplers_to_axi_interconnect_0_AWID), + .M_AXI_awlen(m00_couplers_to_axi_interconnect_0_AWLEN), + .M_AXI_awlock(m00_couplers_to_axi_interconnect_0_AWLOCK), + .M_AXI_awprot(m00_couplers_to_axi_interconnect_0_AWPROT), + .M_AXI_awqos(m00_couplers_to_axi_interconnect_0_AWQOS), + .M_AXI_awready(m00_couplers_to_axi_interconnect_0_AWREADY), + .M_AXI_awsize(m00_couplers_to_axi_interconnect_0_AWSIZE), + .M_AXI_awvalid(m00_couplers_to_axi_interconnect_0_AWVALID), + .M_AXI_bid(m00_couplers_to_axi_interconnect_0_BID), + .M_AXI_bready(m00_couplers_to_axi_interconnect_0_BREADY), + .M_AXI_bresp(m00_couplers_to_axi_interconnect_0_BRESP), + .M_AXI_bvalid(m00_couplers_to_axi_interconnect_0_BVALID), + .M_AXI_rdata(m00_couplers_to_axi_interconnect_0_RDATA), + .M_AXI_rid(m00_couplers_to_axi_interconnect_0_RID), + .M_AXI_rlast(m00_couplers_to_axi_interconnect_0_RLAST), + .M_AXI_rready(m00_couplers_to_axi_interconnect_0_RREADY), + .M_AXI_rresp(m00_couplers_to_axi_interconnect_0_RRESP), + .M_AXI_rvalid(m00_couplers_to_axi_interconnect_0_RVALID), + .M_AXI_wdata(m00_couplers_to_axi_interconnect_0_WDATA), + .M_AXI_wlast(m00_couplers_to_axi_interconnect_0_WLAST), + .M_AXI_wready(m00_couplers_to_axi_interconnect_0_WREADY), + .M_AXI_wstrb(m00_couplers_to_axi_interconnect_0_WSTRB), + .M_AXI_wvalid(m00_couplers_to_axi_interconnect_0_WVALID), + .S_ACLK(axi_interconnect_0_ACLK_net), + .S_ARESETN(axi_interconnect_0_ARESETN_net), + .S_AXI_araddr(xbar_to_m00_couplers_ARADDR), + .S_AXI_arburst(xbar_to_m00_couplers_ARBURST), + .S_AXI_arcache(xbar_to_m00_couplers_ARCACHE), + .S_AXI_arid(xbar_to_m00_couplers_ARID), + .S_AXI_arlen(xbar_to_m00_couplers_ARLEN), + .S_AXI_arlock(xbar_to_m00_couplers_ARLOCK), + .S_AXI_arprot(xbar_to_m00_couplers_ARPROT), + .S_AXI_arqos(xbar_to_m00_couplers_ARQOS), + .S_AXI_arready(xbar_to_m00_couplers_ARREADY), + .S_AXI_arregion(xbar_to_m00_couplers_ARREGION), + .S_AXI_arsize(xbar_to_m00_couplers_ARSIZE), + .S_AXI_arvalid(xbar_to_m00_couplers_ARVALID), + .S_AXI_awaddr(xbar_to_m00_couplers_AWADDR), + .S_AXI_awburst(xbar_to_m00_couplers_AWBURST), + .S_AXI_awcache(xbar_to_m00_couplers_AWCACHE), + .S_AXI_awid(xbar_to_m00_couplers_AWID), + .S_AXI_awlen(xbar_to_m00_couplers_AWLEN), + .S_AXI_awlock(xbar_to_m00_couplers_AWLOCK), + .S_AXI_awprot(xbar_to_m00_couplers_AWPROT), + .S_AXI_awqos(xbar_to_m00_couplers_AWQOS), + .S_AXI_awready(xbar_to_m00_couplers_AWREADY), + .S_AXI_awregion(xbar_to_m00_couplers_AWREGION), + .S_AXI_awsize(xbar_to_m00_couplers_AWSIZE), + .S_AXI_awvalid(xbar_to_m00_couplers_AWVALID), + .S_AXI_bid(xbar_to_m00_couplers_BID), + .S_AXI_bready(xbar_to_m00_couplers_BREADY), + .S_AXI_bresp(xbar_to_m00_couplers_BRESP), + .S_AXI_bvalid(xbar_to_m00_couplers_BVALID), + .S_AXI_rdata(xbar_to_m00_couplers_RDATA), + .S_AXI_rid(xbar_to_m00_couplers_RID), + .S_AXI_rlast(xbar_to_m00_couplers_RLAST), + .S_AXI_rready(xbar_to_m00_couplers_RREADY), + .S_AXI_rresp(xbar_to_m00_couplers_RRESP), + .S_AXI_rvalid(xbar_to_m00_couplers_RVALID), + .S_AXI_wdata(xbar_to_m00_couplers_WDATA), + .S_AXI_wlast(xbar_to_m00_couplers_WLAST), + .S_AXI_wready(xbar_to_m00_couplers_WREADY), + .S_AXI_wstrb(xbar_to_m00_couplers_WSTRB), + .S_AXI_wvalid(xbar_to_m00_couplers_WVALID)); + m01_couplers_imp_16V7BMJ m01_couplers + (.M_ACLK(M01_ACLK_1), + .M_ARESETN(M01_ARESETN_1), + .M_AXI_araddr(m01_couplers_to_axi_interconnect_0_ARADDR), + .M_AXI_arburst(m01_couplers_to_axi_interconnect_0_ARBURST), + .M_AXI_arcache(m01_couplers_to_axi_interconnect_0_ARCACHE), + .M_AXI_arid(m01_couplers_to_axi_interconnect_0_ARID), + .M_AXI_arlen(m01_couplers_to_axi_interconnect_0_ARLEN), + .M_AXI_arlock(m01_couplers_to_axi_interconnect_0_ARLOCK), + .M_AXI_arprot(m01_couplers_to_axi_interconnect_0_ARPROT), + .M_AXI_arqos(m01_couplers_to_axi_interconnect_0_ARQOS), + .M_AXI_arready(m01_couplers_to_axi_interconnect_0_ARREADY), + .M_AXI_arsize(m01_couplers_to_axi_interconnect_0_ARSIZE), + .M_AXI_arvalid(m01_couplers_to_axi_interconnect_0_ARVALID), + .M_AXI_awaddr(m01_couplers_to_axi_interconnect_0_AWADDR), + .M_AXI_awburst(m01_couplers_to_axi_interconnect_0_AWBURST), + .M_AXI_awcache(m01_couplers_to_axi_interconnect_0_AWCACHE), + .M_AXI_awid(m01_couplers_to_axi_interconnect_0_AWID), + .M_AXI_awlen(m01_couplers_to_axi_interconnect_0_AWLEN), + .M_AXI_awlock(m01_couplers_to_axi_interconnect_0_AWLOCK), + .M_AXI_awprot(m01_couplers_to_axi_interconnect_0_AWPROT), + .M_AXI_awqos(m01_couplers_to_axi_interconnect_0_AWQOS), + .M_AXI_awready(m01_couplers_to_axi_interconnect_0_AWREADY), + .M_AXI_awsize(m01_couplers_to_axi_interconnect_0_AWSIZE), + .M_AXI_awvalid(m01_couplers_to_axi_interconnect_0_AWVALID), + .M_AXI_bid(m01_couplers_to_axi_interconnect_0_BID), + .M_AXI_bready(m01_couplers_to_axi_interconnect_0_BREADY), + .M_AXI_bresp(m01_couplers_to_axi_interconnect_0_BRESP), + .M_AXI_bvalid(m01_couplers_to_axi_interconnect_0_BVALID), + .M_AXI_rdata(m01_couplers_to_axi_interconnect_0_RDATA), + .M_AXI_rid(m01_couplers_to_axi_interconnect_0_RID), + .M_AXI_rlast(m01_couplers_to_axi_interconnect_0_RLAST), + .M_AXI_rready(m01_couplers_to_axi_interconnect_0_RREADY), + .M_AXI_rresp(m01_couplers_to_axi_interconnect_0_RRESP), + .M_AXI_rvalid(m01_couplers_to_axi_interconnect_0_RVALID), + .M_AXI_wdata(m01_couplers_to_axi_interconnect_0_WDATA), + .M_AXI_wlast(m01_couplers_to_axi_interconnect_0_WLAST), + .M_AXI_wready(m01_couplers_to_axi_interconnect_0_WREADY), + .M_AXI_wstrb(m01_couplers_to_axi_interconnect_0_WSTRB), + .M_AXI_wvalid(m01_couplers_to_axi_interconnect_0_WVALID), + .S_ACLK(axi_interconnect_0_ACLK_net), + .S_ARESETN(axi_interconnect_0_ARESETN_net), + .S_AXI_araddr(xbar_to_m01_couplers_ARADDR), + .S_AXI_arburst(xbar_to_m01_couplers_ARBURST), + .S_AXI_arcache(xbar_to_m01_couplers_ARCACHE), + .S_AXI_arid(xbar_to_m01_couplers_ARID), + .S_AXI_arlen(xbar_to_m01_couplers_ARLEN), + .S_AXI_arlock(xbar_to_m01_couplers_ARLOCK), + .S_AXI_arprot(xbar_to_m01_couplers_ARPROT), + .S_AXI_arqos(xbar_to_m01_couplers_ARQOS), + .S_AXI_arready(xbar_to_m01_couplers_ARREADY), + .S_AXI_arregion(xbar_to_m01_couplers_ARREGION), + .S_AXI_arsize(xbar_to_m01_couplers_ARSIZE), + .S_AXI_arvalid(xbar_to_m01_couplers_ARVALID), + .S_AXI_awaddr(xbar_to_m01_couplers_AWADDR), + .S_AXI_awburst(xbar_to_m01_couplers_AWBURST), + .S_AXI_awcache(xbar_to_m01_couplers_AWCACHE), + .S_AXI_awid(xbar_to_m01_couplers_AWID), + .S_AXI_awlen(xbar_to_m01_couplers_AWLEN), + .S_AXI_awlock(xbar_to_m01_couplers_AWLOCK), + .S_AXI_awprot(xbar_to_m01_couplers_AWPROT), + .S_AXI_awqos(xbar_to_m01_couplers_AWQOS), + .S_AXI_awready(xbar_to_m01_couplers_AWREADY), + .S_AXI_awregion(xbar_to_m01_couplers_AWREGION), + .S_AXI_awsize(xbar_to_m01_couplers_AWSIZE), + .S_AXI_awvalid(xbar_to_m01_couplers_AWVALID), + .S_AXI_bid(xbar_to_m01_couplers_BID), + .S_AXI_bready(xbar_to_m01_couplers_BREADY), + .S_AXI_bresp(xbar_to_m01_couplers_BRESP), + .S_AXI_bvalid(xbar_to_m01_couplers_BVALID), + .S_AXI_rdata(xbar_to_m01_couplers_RDATA), + .S_AXI_rid(xbar_to_m01_couplers_RID), + .S_AXI_rlast(xbar_to_m01_couplers_RLAST), + .S_AXI_rready(xbar_to_m01_couplers_RREADY), + .S_AXI_rresp(xbar_to_m01_couplers_RRESP), + .S_AXI_rvalid(xbar_to_m01_couplers_RVALID), + .S_AXI_wdata(xbar_to_m01_couplers_WDATA), + .S_AXI_wlast(xbar_to_m01_couplers_WLAST), + .S_AXI_wready(xbar_to_m01_couplers_WREADY), + .S_AXI_wstrb(xbar_to_m01_couplers_WSTRB), + .S_AXI_wvalid(xbar_to_m01_couplers_WVALID)); + m02_couplers_imp_B0MBTH m02_couplers + (.M_ACLK(M02_ACLK_1), + .M_ARESETN(M02_ARESETN_1[0]), + .M_AXI_araddr(m02_couplers_to_axi_interconnect_0_ARADDR), + .M_AXI_arburst(m02_couplers_to_axi_interconnect_0_ARBURST), + .M_AXI_arcache(m02_couplers_to_axi_interconnect_0_ARCACHE), + .M_AXI_arid(m02_couplers_to_axi_interconnect_0_ARID), + .M_AXI_arlen(m02_couplers_to_axi_interconnect_0_ARLEN), + .M_AXI_arlock(m02_couplers_to_axi_interconnect_0_ARLOCK), + .M_AXI_arprot(m02_couplers_to_axi_interconnect_0_ARPROT), + .M_AXI_arready(m02_couplers_to_axi_interconnect_0_ARREADY), + .M_AXI_arsize(m02_couplers_to_axi_interconnect_0_ARSIZE), + .M_AXI_arvalid(m02_couplers_to_axi_interconnect_0_ARVALID), + .M_AXI_awaddr(m02_couplers_to_axi_interconnect_0_AWADDR), + .M_AXI_awburst(m02_couplers_to_axi_interconnect_0_AWBURST), + .M_AXI_awcache(m02_couplers_to_axi_interconnect_0_AWCACHE), + .M_AXI_awid(m02_couplers_to_axi_interconnect_0_AWID), + .M_AXI_awlen(m02_couplers_to_axi_interconnect_0_AWLEN), + .M_AXI_awlock(m02_couplers_to_axi_interconnect_0_AWLOCK), + .M_AXI_awprot(m02_couplers_to_axi_interconnect_0_AWPROT), + .M_AXI_awready(m02_couplers_to_axi_interconnect_0_AWREADY), + .M_AXI_awsize(m02_couplers_to_axi_interconnect_0_AWSIZE), + .M_AXI_awvalid(m02_couplers_to_axi_interconnect_0_AWVALID), + .M_AXI_bid(m02_couplers_to_axi_interconnect_0_BID), + .M_AXI_bready(m02_couplers_to_axi_interconnect_0_BREADY), + .M_AXI_bresp(m02_couplers_to_axi_interconnect_0_BRESP), + .M_AXI_bvalid(m02_couplers_to_axi_interconnect_0_BVALID), + .M_AXI_rdata(m02_couplers_to_axi_interconnect_0_RDATA), + .M_AXI_rid(m02_couplers_to_axi_interconnect_0_RID), + .M_AXI_rlast(m02_couplers_to_axi_interconnect_0_RLAST), + .M_AXI_rready(m02_couplers_to_axi_interconnect_0_RREADY), + .M_AXI_rresp(m02_couplers_to_axi_interconnect_0_RRESP), + .M_AXI_rvalid(m02_couplers_to_axi_interconnect_0_RVALID), + .M_AXI_wdata(m02_couplers_to_axi_interconnect_0_WDATA), + .M_AXI_wlast(m02_couplers_to_axi_interconnect_0_WLAST), + .M_AXI_wready(m02_couplers_to_axi_interconnect_0_WREADY), + .M_AXI_wstrb(m02_couplers_to_axi_interconnect_0_WSTRB), + .M_AXI_wvalid(m02_couplers_to_axi_interconnect_0_WVALID), + .S_ACLK(axi_interconnect_0_ACLK_net), + .S_ARESETN(axi_interconnect_0_ARESETN_net), + .S_AXI_araddr(xbar_to_m02_couplers_ARADDR), + .S_AXI_arburst(xbar_to_m02_couplers_ARBURST), + .S_AXI_arcache(xbar_to_m02_couplers_ARCACHE), + .S_AXI_arid(xbar_to_m02_couplers_ARID), + .S_AXI_arlen(xbar_to_m02_couplers_ARLEN), + .S_AXI_arlock(xbar_to_m02_couplers_ARLOCK), + .S_AXI_arprot(xbar_to_m02_couplers_ARPROT), + .S_AXI_arready(xbar_to_m02_couplers_ARREADY), + .S_AXI_arsize(xbar_to_m02_couplers_ARSIZE), + .S_AXI_arvalid(xbar_to_m02_couplers_ARVALID), + .S_AXI_awaddr(xbar_to_m02_couplers_AWADDR), + .S_AXI_awburst(xbar_to_m02_couplers_AWBURST), + .S_AXI_awcache(xbar_to_m02_couplers_AWCACHE), + .S_AXI_awid(xbar_to_m02_couplers_AWID), + .S_AXI_awlen(xbar_to_m02_couplers_AWLEN), + .S_AXI_awlock(xbar_to_m02_couplers_AWLOCK), + .S_AXI_awprot(xbar_to_m02_couplers_AWPROT), + .S_AXI_awready(xbar_to_m02_couplers_AWREADY), + .S_AXI_awsize(xbar_to_m02_couplers_AWSIZE), + .S_AXI_awvalid(xbar_to_m02_couplers_AWVALID), + .S_AXI_bid(xbar_to_m02_couplers_BID), + .S_AXI_bready(xbar_to_m02_couplers_BREADY), + .S_AXI_bresp(xbar_to_m02_couplers_BRESP), + .S_AXI_bvalid(xbar_to_m02_couplers_BVALID), + .S_AXI_rdata(xbar_to_m02_couplers_RDATA), + .S_AXI_rid(xbar_to_m02_couplers_RID), + .S_AXI_rlast(xbar_to_m02_couplers_RLAST), + .S_AXI_rready(xbar_to_m02_couplers_RREADY), + .S_AXI_rresp(xbar_to_m02_couplers_RRESP), + .S_AXI_rvalid(xbar_to_m02_couplers_RVALID), + .S_AXI_wdata(xbar_to_m02_couplers_WDATA), + .S_AXI_wlast(xbar_to_m02_couplers_WLAST), + .S_AXI_wready(xbar_to_m02_couplers_WREADY), + .S_AXI_wstrb(xbar_to_m02_couplers_WSTRB), + .S_AXI_wvalid(xbar_to_m02_couplers_WVALID)); + s00_couplers_imp_1UB271G s00_couplers + (.M_ACLK(axi_interconnect_0_ACLK_net), + .M_ARESETN(axi_interconnect_0_ARESETN_net), + .M_AXI_araddr(s00_couplers_to_xbar_ARADDR), + .M_AXI_arburst(s00_couplers_to_xbar_ARBURST), + .M_AXI_arcache(s00_couplers_to_xbar_ARCACHE), + .M_AXI_arid(s00_couplers_to_xbar_ARID), + .M_AXI_arlen(s00_couplers_to_xbar_ARLEN), + .M_AXI_arlock(s00_couplers_to_xbar_ARLOCK), + .M_AXI_arprot(s00_couplers_to_xbar_ARPROT), + .M_AXI_arready(s00_couplers_to_xbar_ARREADY), + .M_AXI_arsize(s00_couplers_to_xbar_ARSIZE), + .M_AXI_arvalid(s00_couplers_to_xbar_ARVALID), + .M_AXI_awaddr(s00_couplers_to_xbar_AWADDR), + .M_AXI_awburst(s00_couplers_to_xbar_AWBURST), + .M_AXI_awcache(s00_couplers_to_xbar_AWCACHE), + .M_AXI_awid(s00_couplers_to_xbar_AWID), + .M_AXI_awlen(s00_couplers_to_xbar_AWLEN), + .M_AXI_awlock(s00_couplers_to_xbar_AWLOCK), + .M_AXI_awprot(s00_couplers_to_xbar_AWPROT), + .M_AXI_awready(s00_couplers_to_xbar_AWREADY), + .M_AXI_awsize(s00_couplers_to_xbar_AWSIZE), + .M_AXI_awvalid(s00_couplers_to_xbar_AWVALID), + .M_AXI_bid(s00_couplers_to_xbar_BID), + .M_AXI_bready(s00_couplers_to_xbar_BREADY), + .M_AXI_bresp(s00_couplers_to_xbar_BRESP), + .M_AXI_bvalid(s00_couplers_to_xbar_BVALID), + .M_AXI_rdata(s00_couplers_to_xbar_RDATA), + .M_AXI_rid(s00_couplers_to_xbar_RID), + .M_AXI_rlast(s00_couplers_to_xbar_RLAST), + .M_AXI_rready(s00_couplers_to_xbar_RREADY), + .M_AXI_rresp(s00_couplers_to_xbar_RRESP), + .M_AXI_rvalid(s00_couplers_to_xbar_RVALID), + .M_AXI_wdata(s00_couplers_to_xbar_WDATA), + .M_AXI_wlast(s00_couplers_to_xbar_WLAST), + .M_AXI_wready(s00_couplers_to_xbar_WREADY), + .M_AXI_wstrb(s00_couplers_to_xbar_WSTRB), + .M_AXI_wvalid(s00_couplers_to_xbar_WVALID), + .S_ACLK(S00_ACLK_1), + .S_ARESETN(S00_ARESETN_1), + .S_AXI_araddr(axi_interconnect_0_to_s00_couplers_ARADDR), + .S_AXI_arburst(axi_interconnect_0_to_s00_couplers_ARBURST), + .S_AXI_arcache(axi_interconnect_0_to_s00_couplers_ARCACHE), + .S_AXI_arid(axi_interconnect_0_to_s00_couplers_ARID), + .S_AXI_arlen(axi_interconnect_0_to_s00_couplers_ARLEN), + .S_AXI_arlock(axi_interconnect_0_to_s00_couplers_ARLOCK), + .S_AXI_arprot(axi_interconnect_0_to_s00_couplers_ARPROT), + .S_AXI_arready(axi_interconnect_0_to_s00_couplers_ARREADY), + .S_AXI_arsize(axi_interconnect_0_to_s00_couplers_ARSIZE), + .S_AXI_arvalid(axi_interconnect_0_to_s00_couplers_ARVALID), + .S_AXI_awaddr(axi_interconnect_0_to_s00_couplers_AWADDR), + .S_AXI_awburst(axi_interconnect_0_to_s00_couplers_AWBURST), + .S_AXI_awcache(axi_interconnect_0_to_s00_couplers_AWCACHE), + .S_AXI_awid(axi_interconnect_0_to_s00_couplers_AWID), + .S_AXI_awlen(axi_interconnect_0_to_s00_couplers_AWLEN), + .S_AXI_awlock(axi_interconnect_0_to_s00_couplers_AWLOCK), + .S_AXI_awprot(axi_interconnect_0_to_s00_couplers_AWPROT), + .S_AXI_awready(axi_interconnect_0_to_s00_couplers_AWREADY), + .S_AXI_awsize(axi_interconnect_0_to_s00_couplers_AWSIZE), + .S_AXI_awvalid(axi_interconnect_0_to_s00_couplers_AWVALID), + .S_AXI_bid(axi_interconnect_0_to_s00_couplers_BID), + .S_AXI_bready(axi_interconnect_0_to_s00_couplers_BREADY), + .S_AXI_bresp(axi_interconnect_0_to_s00_couplers_BRESP), + .S_AXI_bvalid(axi_interconnect_0_to_s00_couplers_BVALID), + .S_AXI_rdata(axi_interconnect_0_to_s00_couplers_RDATA), + .S_AXI_rid(axi_interconnect_0_to_s00_couplers_RID), + .S_AXI_rlast(axi_interconnect_0_to_s00_couplers_RLAST), + .S_AXI_rready(axi_interconnect_0_to_s00_couplers_RREADY), + .S_AXI_rresp(axi_interconnect_0_to_s00_couplers_RRESP), + .S_AXI_rvalid(axi_interconnect_0_to_s00_couplers_RVALID), + .S_AXI_wdata(axi_interconnect_0_to_s00_couplers_WDATA), + .S_AXI_wlast(axi_interconnect_0_to_s00_couplers_WLAST), + .S_AXI_wready(axi_interconnect_0_to_s00_couplers_WREADY), + .S_AXI_wstrb(axi_interconnect_0_to_s00_couplers_WSTRB), + .S_AXI_wvalid(axi_interconnect_0_to_s00_couplers_WVALID)); Top_xbar_0 xbar - (.aclk(axi_interconnect_0_ACLK_net), - .aresetn(axi_interconnect_0_ARESETN_net), - .m_axi_araddr({M04_AXI_araddr,M03_AXI_araddr,M02_AXI_araddr,M01_AXI_araddr,M00_AXI_araddr}), - .m_axi_arburst({M04_AXI_arburst,M03_AXI_arburst,M02_AXI_arburst,M01_AXI_arburst,M00_AXI_arburst}), - .m_axi_arcache({M04_AXI_arcache,M03_AXI_arcache,M02_AXI_arcache,M01_AXI_arcache,M00_AXI_arcache}), - .m_axi_arlen({M04_AXI_arlen,M03_AXI_arlen,M02_AXI_arlen,M01_AXI_arlen,M00_AXI_arlen}), - .m_axi_arlock({M04_AXI_arlock,M03_AXI_arlock,M02_AXI_arlock,M01_AXI_arlock,M00_AXI_arlock}), - .m_axi_arprot({M04_AXI_arprot,M03_AXI_arprot,M02_AXI_arprot,M01_AXI_arprot,M00_AXI_arprot}), - .m_axi_arqos({M04_AXI_arqos,M03_AXI_arqos,M02_AXI_arqos,M01_AXI_arqos,M00_AXI_arqos}), - .m_axi_arready({M04_AXI_arready,M03_AXI_arready,M02_AXI_arready,M01_AXI_arready,M00_AXI_arready}), - .m_axi_arregion({M04_AXI_arregion,M03_AXI_arregion,M02_AXI_arregion,M01_AXI_arregion,M00_AXI_arregion}), - .m_axi_arsize({M04_AXI_arsize,M03_AXI_arsize,M02_AXI_arsize,M01_AXI_arsize,M00_AXI_arsize}), - .m_axi_arvalid({M04_AXI_arvalid,M03_AXI_arvalid,M02_AXI_arvalid,M01_AXI_arvalid,M00_AXI_arvalid}), - .m_axi_awaddr({M04_AXI_awaddr,M03_AXI_awaddr,M02_AXI_awaddr,M01_AXI_awaddr,M00_AXI_awaddr}), - .m_axi_awburst({M04_AXI_awburst,M03_AXI_awburst,M02_AXI_awburst,M01_AXI_awburst,M00_AXI_awburst}), - .m_axi_awcache({M04_AXI_awcache,M03_AXI_awcache,M02_AXI_awcache,M01_AXI_awcache,M00_AXI_awcache}), - .m_axi_awlen({M04_AXI_awlen,M03_AXI_awlen,M02_AXI_awlen,M01_AXI_awlen,M00_AXI_awlen}), - .m_axi_awlock({M04_AXI_awlock,M03_AXI_awlock,M02_AXI_awlock,M01_AXI_awlock,M00_AXI_awlock}), - .m_axi_awprot({M04_AXI_awprot,M03_AXI_awprot,M02_AXI_awprot,M01_AXI_awprot,M00_AXI_awprot}), - .m_axi_awqos({M04_AXI_awqos,M03_AXI_awqos,M02_AXI_awqos,M01_AXI_awqos,M00_AXI_awqos}), - .m_axi_awready({M04_AXI_awready,M03_AXI_awready,M02_AXI_awready,M01_AXI_awready,M00_AXI_awready}), - .m_axi_awregion({M04_AXI_awregion,M03_AXI_awregion,M02_AXI_awregion,M01_AXI_awregion,M00_AXI_awregion}), - .m_axi_awsize({M04_AXI_awsize,M03_AXI_awsize,M02_AXI_awsize,M01_AXI_awsize,M00_AXI_awsize}), - .m_axi_awvalid({M04_AXI_awvalid,M03_AXI_awvalid,M02_AXI_awvalid,M01_AXI_awvalid,M00_AXI_awvalid}), - .m_axi_bready({M04_AXI_bready,M03_AXI_bready,M02_AXI_bready,M01_AXI_bready,M00_AXI_bready}), - .m_axi_bresp({M04_AXI_bresp,M03_AXI_bresp,M02_AXI_bresp,M01_AXI_bresp,M00_AXI_bresp}), - .m_axi_bvalid({M04_AXI_bvalid,M03_AXI_bvalid,M02_AXI_bvalid,M01_AXI_bvalid,M00_AXI_bvalid}), - .m_axi_rdata({M04_AXI_rdata,M03_AXI_rdata,M02_AXI_rdata,M01_AXI_rdata,M00_AXI_rdata}), - .m_axi_rlast({M04_AXI_rlast,M03_AXI_rlast,M02_AXI_rlast,M01_AXI_rlast,M00_AXI_rlast}), - .m_axi_rready({M04_AXI_rready,M03_AXI_rready,M02_AXI_rready,M01_AXI_rready,M00_AXI_rready}), - .m_axi_rresp({M04_AXI_rresp,M03_AXI_rresp,M02_AXI_rresp,M01_AXI_rresp,M00_AXI_rresp}), - .m_axi_rvalid({M04_AXI_rvalid,M03_AXI_rvalid,M02_AXI_rvalid,M01_AXI_rvalid,M00_AXI_rvalid}), - .m_axi_wdata({M04_AXI_wdata,M03_AXI_wdata,M02_AXI_wdata,M01_AXI_wdata,M00_AXI_wdata}), - .m_axi_wlast({M04_AXI_wlast,M03_AXI_wlast,M02_AXI_wlast,M01_AXI_wlast,M00_AXI_wlast}), - .m_axi_wready({M04_AXI_wready,M03_AXI_wready,M02_AXI_wready,M01_AXI_wready,M00_AXI_wready}), - .m_axi_wstrb({M04_AXI_wstrb,M03_AXI_wstrb,M02_AXI_wstrb,M01_AXI_wstrb,M00_AXI_wstrb}), - .m_axi_wvalid({M04_AXI_wvalid,M03_AXI_wvalid,M02_AXI_wvalid,M01_AXI_wvalid,M00_AXI_wvalid}), - .s_axi_araddr(S00_AXI_araddr), - .s_axi_arburst(S00_AXI_arburst), - .s_axi_arcache(S00_AXI_arcache), - .s_axi_arlen(S00_AXI_arlen), - .s_axi_arlock(S00_AXI_arlock), - .s_axi_arprot(S00_AXI_arprot), - .s_axi_arqos(S00_AXI_arqos), - .s_axi_arready(S00_AXI_arready), - .s_axi_arsize(S00_AXI_arsize), - .s_axi_arvalid(S00_AXI_arvalid), - .s_axi_awaddr(S00_AXI_awaddr), - .s_axi_awburst(S00_AXI_awburst), - .s_axi_awcache(S00_AXI_awcache), - .s_axi_awlen(S00_AXI_awlen), - .s_axi_awlock(S00_AXI_awlock), - .s_axi_awprot(S00_AXI_awprot), - .s_axi_awqos(S00_AXI_awqos), - .s_axi_awready(S00_AXI_awready), - .s_axi_awsize(S00_AXI_awsize), - .s_axi_awvalid(S00_AXI_awvalid), - .s_axi_bready(S00_AXI_bready), - .s_axi_bresp(S00_AXI_bresp), - .s_axi_bvalid(S00_AXI_bvalid), - .s_axi_rdata(S00_AXI_rdata), - .s_axi_rlast(S00_AXI_rlast), - .s_axi_rready(S00_AXI_rready), - .s_axi_rresp(S00_AXI_rresp), - .s_axi_rvalid(S00_AXI_rvalid), - .s_axi_wdata(S00_AXI_wdata), - .s_axi_wlast(S00_AXI_wlast), - .s_axi_wready(S00_AXI_wready), - .s_axi_wstrb(S00_AXI_wstrb), - .s_axi_wvalid(S00_AXI_wvalid)); - + (.aclk(axi_interconnect_0_ACLK_net), + .aresetn(axi_interconnect_0_ARESETN_net), + .m_axi_araddr({xbar_to_m02_couplers_ARADDR,xbar_to_m01_couplers_ARADDR,xbar_to_m00_couplers_ARADDR}), + .m_axi_arburst({xbar_to_m02_couplers_ARBURST,xbar_to_m01_couplers_ARBURST,xbar_to_m00_couplers_ARBURST}), + .m_axi_arcache({xbar_to_m02_couplers_ARCACHE,xbar_to_m01_couplers_ARCACHE,xbar_to_m00_couplers_ARCACHE}), + .m_axi_arid({xbar_to_m02_couplers_ARID,xbar_to_m01_couplers_ARID,xbar_to_m00_couplers_ARID}), + .m_axi_arlen({xbar_to_m02_couplers_ARLEN,xbar_to_m01_couplers_ARLEN,xbar_to_m00_couplers_ARLEN}), + .m_axi_arlock({xbar_to_m02_couplers_ARLOCK,xbar_to_m01_couplers_ARLOCK,xbar_to_m00_couplers_ARLOCK}), + .m_axi_arprot({xbar_to_m02_couplers_ARPROT,xbar_to_m01_couplers_ARPROT,xbar_to_m00_couplers_ARPROT}), + .m_axi_arqos({xbar_to_m01_couplers_ARQOS,xbar_to_m00_couplers_ARQOS}), + .m_axi_arready({xbar_to_m02_couplers_ARREADY,xbar_to_m01_couplers_ARREADY,xbar_to_m00_couplers_ARREADY}), + .m_axi_arregion({xbar_to_m01_couplers_ARREGION,xbar_to_m00_couplers_ARREGION}), + .m_axi_arsize({xbar_to_m02_couplers_ARSIZE,xbar_to_m01_couplers_ARSIZE,xbar_to_m00_couplers_ARSIZE}), + .m_axi_arvalid({xbar_to_m02_couplers_ARVALID,xbar_to_m01_couplers_ARVALID,xbar_to_m00_couplers_ARVALID}), + .m_axi_awaddr({xbar_to_m02_couplers_AWADDR,xbar_to_m01_couplers_AWADDR,xbar_to_m00_couplers_AWADDR}), + .m_axi_awburst({xbar_to_m02_couplers_AWBURST,xbar_to_m01_couplers_AWBURST,xbar_to_m00_couplers_AWBURST}), + .m_axi_awcache({xbar_to_m02_couplers_AWCACHE,xbar_to_m01_couplers_AWCACHE,xbar_to_m00_couplers_AWCACHE}), + .m_axi_awid({xbar_to_m02_couplers_AWID,xbar_to_m01_couplers_AWID,xbar_to_m00_couplers_AWID}), + .m_axi_awlen({xbar_to_m02_couplers_AWLEN,xbar_to_m01_couplers_AWLEN,xbar_to_m00_couplers_AWLEN}), + .m_axi_awlock({xbar_to_m02_couplers_AWLOCK,xbar_to_m01_couplers_AWLOCK,xbar_to_m00_couplers_AWLOCK}), + .m_axi_awprot({xbar_to_m02_couplers_AWPROT,xbar_to_m01_couplers_AWPROT,xbar_to_m00_couplers_AWPROT}), + .m_axi_awqos({xbar_to_m01_couplers_AWQOS,xbar_to_m00_couplers_AWQOS}), + .m_axi_awready({xbar_to_m02_couplers_AWREADY,xbar_to_m01_couplers_AWREADY,xbar_to_m00_couplers_AWREADY}), + .m_axi_awregion({xbar_to_m01_couplers_AWREGION,xbar_to_m00_couplers_AWREGION}), + .m_axi_awsize({xbar_to_m02_couplers_AWSIZE,xbar_to_m01_couplers_AWSIZE,xbar_to_m00_couplers_AWSIZE}), + .m_axi_awvalid({xbar_to_m02_couplers_AWVALID,xbar_to_m01_couplers_AWVALID,xbar_to_m00_couplers_AWVALID}), + .m_axi_bid({xbar_to_m02_couplers_BID,xbar_to_m01_couplers_BID,xbar_to_m00_couplers_BID}), + .m_axi_bready({xbar_to_m02_couplers_BREADY,xbar_to_m01_couplers_BREADY,xbar_to_m00_couplers_BREADY}), + .m_axi_bresp({xbar_to_m02_couplers_BRESP,xbar_to_m01_couplers_BRESP,xbar_to_m00_couplers_BRESP}), + .m_axi_bvalid({xbar_to_m02_couplers_BVALID,xbar_to_m01_couplers_BVALID,xbar_to_m00_couplers_BVALID}), + .m_axi_rdata({xbar_to_m02_couplers_RDATA,xbar_to_m01_couplers_RDATA,xbar_to_m00_couplers_RDATA}), + .m_axi_rid({xbar_to_m02_couplers_RID,xbar_to_m01_couplers_RID,xbar_to_m00_couplers_RID}), + .m_axi_rlast({xbar_to_m02_couplers_RLAST,xbar_to_m01_couplers_RLAST,xbar_to_m00_couplers_RLAST}), + .m_axi_rready({xbar_to_m02_couplers_RREADY,xbar_to_m01_couplers_RREADY,xbar_to_m00_couplers_RREADY}), + .m_axi_rresp({xbar_to_m02_couplers_RRESP,xbar_to_m01_couplers_RRESP,xbar_to_m00_couplers_RRESP}), + .m_axi_rvalid({xbar_to_m02_couplers_RVALID,xbar_to_m01_couplers_RVALID,xbar_to_m00_couplers_RVALID}), + .m_axi_wdata({xbar_to_m02_couplers_WDATA,xbar_to_m01_couplers_WDATA,xbar_to_m00_couplers_WDATA}), + .m_axi_wlast({xbar_to_m02_couplers_WLAST,xbar_to_m01_couplers_WLAST,xbar_to_m00_couplers_WLAST}), + .m_axi_wready({xbar_to_m02_couplers_WREADY,xbar_to_m01_couplers_WREADY,xbar_to_m00_couplers_WREADY}), + .m_axi_wstrb({xbar_to_m02_couplers_WSTRB,xbar_to_m01_couplers_WSTRB,xbar_to_m00_couplers_WSTRB}), + .m_axi_wvalid({xbar_to_m02_couplers_WVALID,xbar_to_m01_couplers_WVALID,xbar_to_m00_couplers_WVALID}), + .s_axi_araddr(s00_couplers_to_xbar_ARADDR), + .s_axi_arburst(s00_couplers_to_xbar_ARBURST), + .s_axi_arcache(s00_couplers_to_xbar_ARCACHE), + .s_axi_arid(s00_couplers_to_xbar_ARID), + .s_axi_arlen(s00_couplers_to_xbar_ARLEN), + .s_axi_arlock(s00_couplers_to_xbar_ARLOCK), + .s_axi_arprot(s00_couplers_to_xbar_ARPROT), + .s_axi_arqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_arready(s00_couplers_to_xbar_ARREADY), + .s_axi_arsize(s00_couplers_to_xbar_ARSIZE), + .s_axi_arvalid(s00_couplers_to_xbar_ARVALID), + .s_axi_awaddr(s00_couplers_to_xbar_AWADDR), + .s_axi_awburst(s00_couplers_to_xbar_AWBURST), + .s_axi_awcache(s00_couplers_to_xbar_AWCACHE), + .s_axi_awid(s00_couplers_to_xbar_AWID), + .s_axi_awlen(s00_couplers_to_xbar_AWLEN), + .s_axi_awlock(s00_couplers_to_xbar_AWLOCK), + .s_axi_awprot(s00_couplers_to_xbar_AWPROT), + .s_axi_awqos({1'b0,1'b0,1'b0,1'b0}), + .s_axi_awready(s00_couplers_to_xbar_AWREADY), + .s_axi_awsize(s00_couplers_to_xbar_AWSIZE), + .s_axi_awvalid(s00_couplers_to_xbar_AWVALID), + .s_axi_bid(s00_couplers_to_xbar_BID), + .s_axi_bready(s00_couplers_to_xbar_BREADY), + .s_axi_bresp(s00_couplers_to_xbar_BRESP), + .s_axi_bvalid(s00_couplers_to_xbar_BVALID), + .s_axi_rdata(s00_couplers_to_xbar_RDATA), + .s_axi_rid(s00_couplers_to_xbar_RID), + .s_axi_rlast(s00_couplers_to_xbar_RLAST), + .s_axi_rready(s00_couplers_to_xbar_RREADY), + .s_axi_rresp(s00_couplers_to_xbar_RRESP), + .s_axi_rvalid(s00_couplers_to_xbar_RVALID), + .s_axi_wdata(s00_couplers_to_xbar_WDATA), + .s_axi_wlast(s00_couplers_to_xbar_WLAST), + .s_axi_wready(s00_couplers_to_xbar_WREADY), + .s_axi_wstrb(s00_couplers_to_xbar_WSTRB), + .s_axi_wvalid(s00_couplers_to_xbar_WVALID)); +endmodule + +module m00_couplers_imp_JY9FDQ + (M_ACLK, + M_ARESETN, + M_AXI_araddr, + M_AXI_arburst, + M_AXI_arcache, + M_AXI_arid, + M_AXI_arlen, + M_AXI_arlock, + M_AXI_arprot, + M_AXI_arqos, + M_AXI_arready, + M_AXI_arsize, + M_AXI_arvalid, + M_AXI_awaddr, + M_AXI_awburst, + M_AXI_awcache, + M_AXI_awid, + M_AXI_awlen, + M_AXI_awlock, + M_AXI_awprot, + M_AXI_awqos, + M_AXI_awready, + M_AXI_awsize, + M_AXI_awvalid, + M_AXI_bid, + M_AXI_bready, + M_AXI_bresp, + M_AXI_bvalid, + M_AXI_rdata, + M_AXI_rid, + M_AXI_rlast, + M_AXI_rready, + M_AXI_rresp, + M_AXI_rvalid, + M_AXI_wdata, + M_AXI_wlast, + M_AXI_wready, + M_AXI_wstrb, + M_AXI_wvalid, + S_ACLK, + S_ARESETN, + S_AXI_araddr, + S_AXI_arburst, + S_AXI_arcache, + S_AXI_arid, + S_AXI_arlen, + S_AXI_arlock, + S_AXI_arprot, + S_AXI_arqos, + S_AXI_arready, + S_AXI_arregion, + S_AXI_arsize, + S_AXI_arvalid, + S_AXI_awaddr, + S_AXI_awburst, + S_AXI_awcache, + S_AXI_awid, + S_AXI_awlen, + S_AXI_awlock, + S_AXI_awprot, + S_AXI_awqos, + S_AXI_awready, + S_AXI_awregion, + S_AXI_awsize, + S_AXI_awvalid, + S_AXI_bid, + S_AXI_bready, + S_AXI_bresp, + S_AXI_bvalid, + S_AXI_rdata, + S_AXI_rid, + S_AXI_rlast, + S_AXI_rready, + S_AXI_rresp, + S_AXI_rvalid, + S_AXI_wdata, + S_AXI_wlast, + S_AXI_wready, + S_AXI_wstrb, + S_AXI_wvalid); + input M_ACLK; + input [7:0]M_ARESETN; + output [30:0]M_AXI_araddr; + output [1:0]M_AXI_arburst; + output [3:0]M_AXI_arcache; + output [3:0]M_AXI_arid; + output [7:0]M_AXI_arlen; + output M_AXI_arlock; + output [2:0]M_AXI_arprot; + output [3:0]M_AXI_arqos; + input M_AXI_arready; + output [2:0]M_AXI_arsize; + output M_AXI_arvalid; + output [30:0]M_AXI_awaddr; + output [1:0]M_AXI_awburst; + output [3:0]M_AXI_awcache; + output [3:0]M_AXI_awid; + output [7:0]M_AXI_awlen; + output M_AXI_awlock; + output [2:0]M_AXI_awprot; + output [3:0]M_AXI_awqos; + input M_AXI_awready; + output [2:0]M_AXI_awsize; + output M_AXI_awvalid; + input [3:0]M_AXI_bid; + output M_AXI_bready; + input [1:0]M_AXI_bresp; + input M_AXI_bvalid; + input [63:0]M_AXI_rdata; + input [3:0]M_AXI_rid; + input M_AXI_rlast; + output M_AXI_rready; + input [1:0]M_AXI_rresp; + input M_AXI_rvalid; + output [63:0]M_AXI_wdata; + output M_AXI_wlast; + input M_AXI_wready; + output [7:0]M_AXI_wstrb; + output M_AXI_wvalid; + input S_ACLK; + input S_ARESETN; + input [63:0]S_AXI_araddr; + input [1:0]S_AXI_arburst; + input [3:0]S_AXI_arcache; + input [3:0]S_AXI_arid; + input [7:0]S_AXI_arlen; + input [0:0]S_AXI_arlock; + input [2:0]S_AXI_arprot; + input [3:0]S_AXI_arqos; + output S_AXI_arready; + input [3:0]S_AXI_arregion; + input [2:0]S_AXI_arsize; + input S_AXI_arvalid; + input [63:0]S_AXI_awaddr; + input [1:0]S_AXI_awburst; + input [3:0]S_AXI_awcache; + input [3:0]S_AXI_awid; + input [7:0]S_AXI_awlen; + input [0:0]S_AXI_awlock; + input [2:0]S_AXI_awprot; + input [3:0]S_AXI_awqos; + output S_AXI_awready; + input [3:0]S_AXI_awregion; + input [2:0]S_AXI_awsize; + input S_AXI_awvalid; + output [3:0]S_AXI_bid; + input S_AXI_bready; + output [1:0]S_AXI_bresp; + output S_AXI_bvalid; + output [63:0]S_AXI_rdata; + output [3:0]S_AXI_rid; + output S_AXI_rlast; + input S_AXI_rready; + output [1:0]S_AXI_rresp; + output S_AXI_rvalid; + input [63:0]S_AXI_wdata; + input S_AXI_wlast; + output S_AXI_wready; + input [7:0]S_AXI_wstrb; + input S_AXI_wvalid; + + wire M_ACLK_1; + wire [7:0]M_ARESETN_1; + wire S_ACLK_1; + wire S_ARESETN_1; + wire [30:0]auto_cc_to_m00_couplers_ARADDR; + wire [1:0]auto_cc_to_m00_couplers_ARBURST; + wire [3:0]auto_cc_to_m00_couplers_ARCACHE; + wire [3:0]auto_cc_to_m00_couplers_ARID; + wire [7:0]auto_cc_to_m00_couplers_ARLEN; + wire [0:0]auto_cc_to_m00_couplers_ARLOCK; + wire [2:0]auto_cc_to_m00_couplers_ARPROT; + wire [3:0]auto_cc_to_m00_couplers_ARQOS; + wire auto_cc_to_m00_couplers_ARREADY; + wire [2:0]auto_cc_to_m00_couplers_ARSIZE; + wire auto_cc_to_m00_couplers_ARVALID; + wire [30:0]auto_cc_to_m00_couplers_AWADDR; + wire [1:0]auto_cc_to_m00_couplers_AWBURST; + wire [3:0]auto_cc_to_m00_couplers_AWCACHE; + wire [3:0]auto_cc_to_m00_couplers_AWID; + wire [7:0]auto_cc_to_m00_couplers_AWLEN; + wire [0:0]auto_cc_to_m00_couplers_AWLOCK; + wire [2:0]auto_cc_to_m00_couplers_AWPROT; + wire [3:0]auto_cc_to_m00_couplers_AWQOS; + wire auto_cc_to_m00_couplers_AWREADY; + wire [2:0]auto_cc_to_m00_couplers_AWSIZE; + wire auto_cc_to_m00_couplers_AWVALID; + wire [3:0]auto_cc_to_m00_couplers_BID; + wire auto_cc_to_m00_couplers_BREADY; + wire [1:0]auto_cc_to_m00_couplers_BRESP; + wire auto_cc_to_m00_couplers_BVALID; + wire [63:0]auto_cc_to_m00_couplers_RDATA; + wire [3:0]auto_cc_to_m00_couplers_RID; + wire auto_cc_to_m00_couplers_RLAST; + wire auto_cc_to_m00_couplers_RREADY; + wire [1:0]auto_cc_to_m00_couplers_RRESP; + wire auto_cc_to_m00_couplers_RVALID; + wire [63:0]auto_cc_to_m00_couplers_WDATA; + wire auto_cc_to_m00_couplers_WLAST; + wire auto_cc_to_m00_couplers_WREADY; + wire [7:0]auto_cc_to_m00_couplers_WSTRB; + wire auto_cc_to_m00_couplers_WVALID; + wire [63:0]m00_couplers_to_auto_cc_ARADDR; + wire [1:0]m00_couplers_to_auto_cc_ARBURST; + wire [3:0]m00_couplers_to_auto_cc_ARCACHE; + wire [3:0]m00_couplers_to_auto_cc_ARID; + wire [7:0]m00_couplers_to_auto_cc_ARLEN; + wire [0:0]m00_couplers_to_auto_cc_ARLOCK; + wire [2:0]m00_couplers_to_auto_cc_ARPROT; + wire [3:0]m00_couplers_to_auto_cc_ARQOS; + wire m00_couplers_to_auto_cc_ARREADY; + wire [3:0]m00_couplers_to_auto_cc_ARREGION; + wire [2:0]m00_couplers_to_auto_cc_ARSIZE; + wire m00_couplers_to_auto_cc_ARVALID; + wire [63:0]m00_couplers_to_auto_cc_AWADDR; + wire [1:0]m00_couplers_to_auto_cc_AWBURST; + wire [3:0]m00_couplers_to_auto_cc_AWCACHE; + wire [3:0]m00_couplers_to_auto_cc_AWID; + wire [7:0]m00_couplers_to_auto_cc_AWLEN; + wire [0:0]m00_couplers_to_auto_cc_AWLOCK; + wire [2:0]m00_couplers_to_auto_cc_AWPROT; + wire [3:0]m00_couplers_to_auto_cc_AWQOS; + wire m00_couplers_to_auto_cc_AWREADY; + wire [3:0]m00_couplers_to_auto_cc_AWREGION; + wire [2:0]m00_couplers_to_auto_cc_AWSIZE; + wire m00_couplers_to_auto_cc_AWVALID; + wire [3:0]m00_couplers_to_auto_cc_BID; + wire m00_couplers_to_auto_cc_BREADY; + wire [1:0]m00_couplers_to_auto_cc_BRESP; + wire m00_couplers_to_auto_cc_BVALID; + wire [63:0]m00_couplers_to_auto_cc_RDATA; + wire [3:0]m00_couplers_to_auto_cc_RID; + wire m00_couplers_to_auto_cc_RLAST; + wire m00_couplers_to_auto_cc_RREADY; + wire [1:0]m00_couplers_to_auto_cc_RRESP; + wire m00_couplers_to_auto_cc_RVALID; + wire [63:0]m00_couplers_to_auto_cc_WDATA; + wire m00_couplers_to_auto_cc_WLAST; + wire m00_couplers_to_auto_cc_WREADY; + wire [7:0]m00_couplers_to_auto_cc_WSTRB; + wire m00_couplers_to_auto_cc_WVALID; + + assign M_ACLK_1 = M_ACLK; + assign M_ARESETN_1 = M_ARESETN[7:0]; + assign M_AXI_araddr[30:0] = auto_cc_to_m00_couplers_ARADDR; + assign M_AXI_arburst[1:0] = auto_cc_to_m00_couplers_ARBURST; + assign M_AXI_arcache[3:0] = auto_cc_to_m00_couplers_ARCACHE; + assign M_AXI_arid[3:0] = auto_cc_to_m00_couplers_ARID; + assign M_AXI_arlen[7:0] = auto_cc_to_m00_couplers_ARLEN; + assign M_AXI_arlock = auto_cc_to_m00_couplers_ARLOCK; + assign M_AXI_arprot[2:0] = auto_cc_to_m00_couplers_ARPROT; + assign M_AXI_arqos[3:0] = auto_cc_to_m00_couplers_ARQOS; + assign M_AXI_arsize[2:0] = auto_cc_to_m00_couplers_ARSIZE; + assign M_AXI_arvalid = auto_cc_to_m00_couplers_ARVALID; + assign M_AXI_awaddr[30:0] = auto_cc_to_m00_couplers_AWADDR; + assign M_AXI_awburst[1:0] = auto_cc_to_m00_couplers_AWBURST; + assign M_AXI_awcache[3:0] = auto_cc_to_m00_couplers_AWCACHE; + assign M_AXI_awid[3:0] = auto_cc_to_m00_couplers_AWID; + assign M_AXI_awlen[7:0] = auto_cc_to_m00_couplers_AWLEN; + assign M_AXI_awlock = auto_cc_to_m00_couplers_AWLOCK; + assign M_AXI_awprot[2:0] = auto_cc_to_m00_couplers_AWPROT; + assign M_AXI_awqos[3:0] = auto_cc_to_m00_couplers_AWQOS; + assign M_AXI_awsize[2:0] = auto_cc_to_m00_couplers_AWSIZE; + assign M_AXI_awvalid = auto_cc_to_m00_couplers_AWVALID; + assign M_AXI_bready = auto_cc_to_m00_couplers_BREADY; + assign M_AXI_rready = auto_cc_to_m00_couplers_RREADY; + assign M_AXI_wdata[63:0] = auto_cc_to_m00_couplers_WDATA; + assign M_AXI_wlast = auto_cc_to_m00_couplers_WLAST; + assign M_AXI_wstrb[7:0] = auto_cc_to_m00_couplers_WSTRB; + assign M_AXI_wvalid = auto_cc_to_m00_couplers_WVALID; + assign S_ACLK_1 = S_ACLK; + assign S_ARESETN_1 = S_ARESETN; + assign S_AXI_arready = m00_couplers_to_auto_cc_ARREADY; + assign S_AXI_awready = m00_couplers_to_auto_cc_AWREADY; + assign S_AXI_bid[3:0] = m00_couplers_to_auto_cc_BID; + assign S_AXI_bresp[1:0] = m00_couplers_to_auto_cc_BRESP; + assign S_AXI_bvalid = m00_couplers_to_auto_cc_BVALID; + assign S_AXI_rdata[63:0] = m00_couplers_to_auto_cc_RDATA; + assign S_AXI_rid[3:0] = m00_couplers_to_auto_cc_RID; + assign S_AXI_rlast = m00_couplers_to_auto_cc_RLAST; + assign S_AXI_rresp[1:0] = m00_couplers_to_auto_cc_RRESP; + assign S_AXI_rvalid = m00_couplers_to_auto_cc_RVALID; + assign S_AXI_wready = m00_couplers_to_auto_cc_WREADY; + assign auto_cc_to_m00_couplers_ARREADY = M_AXI_arready; + assign auto_cc_to_m00_couplers_AWREADY = M_AXI_awready; + assign auto_cc_to_m00_couplers_BID = M_AXI_bid[3:0]; + assign auto_cc_to_m00_couplers_BRESP = M_AXI_bresp[1:0]; + assign auto_cc_to_m00_couplers_BVALID = M_AXI_bvalid; + assign auto_cc_to_m00_couplers_RDATA = M_AXI_rdata[63:0]; + assign auto_cc_to_m00_couplers_RID = M_AXI_rid[3:0]; + assign auto_cc_to_m00_couplers_RLAST = M_AXI_rlast; + assign auto_cc_to_m00_couplers_RRESP = M_AXI_rresp[1:0]; + assign auto_cc_to_m00_couplers_RVALID = M_AXI_rvalid; + assign auto_cc_to_m00_couplers_WREADY = M_AXI_wready; + assign m00_couplers_to_auto_cc_ARADDR = S_AXI_araddr[63:0]; + assign m00_couplers_to_auto_cc_ARBURST = S_AXI_arburst[1:0]; + assign m00_couplers_to_auto_cc_ARCACHE = S_AXI_arcache[3:0]; + assign m00_couplers_to_auto_cc_ARID = S_AXI_arid[3:0]; + assign m00_couplers_to_auto_cc_ARLEN = S_AXI_arlen[7:0]; + assign m00_couplers_to_auto_cc_ARLOCK = S_AXI_arlock[0]; + assign m00_couplers_to_auto_cc_ARPROT = S_AXI_arprot[2:0]; + assign m00_couplers_to_auto_cc_ARQOS = S_AXI_arqos[3:0]; + assign m00_couplers_to_auto_cc_ARREGION = S_AXI_arregion[3:0]; + assign m00_couplers_to_auto_cc_ARSIZE = S_AXI_arsize[2:0]; + assign m00_couplers_to_auto_cc_ARVALID = S_AXI_arvalid; + assign m00_couplers_to_auto_cc_AWADDR = S_AXI_awaddr[63:0]; + assign m00_couplers_to_auto_cc_AWBURST = S_AXI_awburst[1:0]; + assign m00_couplers_to_auto_cc_AWCACHE = S_AXI_awcache[3:0]; + assign m00_couplers_to_auto_cc_AWID = S_AXI_awid[3:0]; + assign m00_couplers_to_auto_cc_AWLEN = S_AXI_awlen[7:0]; + assign m00_couplers_to_auto_cc_AWLOCK = S_AXI_awlock[0]; + assign m00_couplers_to_auto_cc_AWPROT = S_AXI_awprot[2:0]; + assign m00_couplers_to_auto_cc_AWQOS = S_AXI_awqos[3:0]; + assign m00_couplers_to_auto_cc_AWREGION = S_AXI_awregion[3:0]; + assign m00_couplers_to_auto_cc_AWSIZE = S_AXI_awsize[2:0]; + assign m00_couplers_to_auto_cc_AWVALID = S_AXI_awvalid; + assign m00_couplers_to_auto_cc_BREADY = S_AXI_bready; + assign m00_couplers_to_auto_cc_RREADY = S_AXI_rready; + assign m00_couplers_to_auto_cc_WDATA = S_AXI_wdata[63:0]; + assign m00_couplers_to_auto_cc_WLAST = S_AXI_wlast; + assign m00_couplers_to_auto_cc_WSTRB = S_AXI_wstrb[7:0]; + assign m00_couplers_to_auto_cc_WVALID = S_AXI_wvalid; + Top_auto_cc_0 auto_cc + (.m_axi_aclk(M_ACLK_1), + .m_axi_araddr(auto_cc_to_m00_couplers_ARADDR), + .m_axi_arburst(auto_cc_to_m00_couplers_ARBURST), + .m_axi_arcache(auto_cc_to_m00_couplers_ARCACHE), + .m_axi_aresetn(M_ARESETN_1[0]), + .m_axi_arid(auto_cc_to_m00_couplers_ARID), + .m_axi_arlen(auto_cc_to_m00_couplers_ARLEN), + .m_axi_arlock(auto_cc_to_m00_couplers_ARLOCK), + .m_axi_arprot(auto_cc_to_m00_couplers_ARPROT), + .m_axi_arqos(auto_cc_to_m00_couplers_ARQOS), + .m_axi_arready(auto_cc_to_m00_couplers_ARREADY), + .m_axi_arsize(auto_cc_to_m00_couplers_ARSIZE), + .m_axi_arvalid(auto_cc_to_m00_couplers_ARVALID), + .m_axi_awaddr(auto_cc_to_m00_couplers_AWADDR), + .m_axi_awburst(auto_cc_to_m00_couplers_AWBURST), + .m_axi_awcache(auto_cc_to_m00_couplers_AWCACHE), + .m_axi_awid(auto_cc_to_m00_couplers_AWID), + .m_axi_awlen(auto_cc_to_m00_couplers_AWLEN), + .m_axi_awlock(auto_cc_to_m00_couplers_AWLOCK), + .m_axi_awprot(auto_cc_to_m00_couplers_AWPROT), + .m_axi_awqos(auto_cc_to_m00_couplers_AWQOS), + .m_axi_awready(auto_cc_to_m00_couplers_AWREADY), + .m_axi_awsize(auto_cc_to_m00_couplers_AWSIZE), + .m_axi_awvalid(auto_cc_to_m00_couplers_AWVALID), + .m_axi_bid(auto_cc_to_m00_couplers_BID), + .m_axi_bready(auto_cc_to_m00_couplers_BREADY), + .m_axi_bresp(auto_cc_to_m00_couplers_BRESP), + .m_axi_bvalid(auto_cc_to_m00_couplers_BVALID), + .m_axi_rdata(auto_cc_to_m00_couplers_RDATA), + .m_axi_rid(auto_cc_to_m00_couplers_RID), + .m_axi_rlast(auto_cc_to_m00_couplers_RLAST), + .m_axi_rready(auto_cc_to_m00_couplers_RREADY), + .m_axi_rresp(auto_cc_to_m00_couplers_RRESP), + .m_axi_rvalid(auto_cc_to_m00_couplers_RVALID), + .m_axi_wdata(auto_cc_to_m00_couplers_WDATA), + .m_axi_wlast(auto_cc_to_m00_couplers_WLAST), + .m_axi_wready(auto_cc_to_m00_couplers_WREADY), + .m_axi_wstrb(auto_cc_to_m00_couplers_WSTRB), + .m_axi_wvalid(auto_cc_to_m00_couplers_WVALID), + .s_axi_aclk(S_ACLK_1), + .s_axi_araddr(m00_couplers_to_auto_cc_ARADDR[30:0]), + .s_axi_arburst(m00_couplers_to_auto_cc_ARBURST), + .s_axi_arcache(m00_couplers_to_auto_cc_ARCACHE), + .s_axi_aresetn(S_ARESETN_1), + .s_axi_arid(m00_couplers_to_auto_cc_ARID), + .s_axi_arlen(m00_couplers_to_auto_cc_ARLEN), + .s_axi_arlock(m00_couplers_to_auto_cc_ARLOCK), + .s_axi_arprot(m00_couplers_to_auto_cc_ARPROT), + .s_axi_arqos(m00_couplers_to_auto_cc_ARQOS), + .s_axi_arready(m00_couplers_to_auto_cc_ARREADY), + .s_axi_arregion(m00_couplers_to_auto_cc_ARREGION), + .s_axi_arsize(m00_couplers_to_auto_cc_ARSIZE), + .s_axi_arvalid(m00_couplers_to_auto_cc_ARVALID), + .s_axi_awaddr(m00_couplers_to_auto_cc_AWADDR[30:0]), + .s_axi_awburst(m00_couplers_to_auto_cc_AWBURST), + .s_axi_awcache(m00_couplers_to_auto_cc_AWCACHE), + .s_axi_awid(m00_couplers_to_auto_cc_AWID), + .s_axi_awlen(m00_couplers_to_auto_cc_AWLEN), + .s_axi_awlock(m00_couplers_to_auto_cc_AWLOCK), + .s_axi_awprot(m00_couplers_to_auto_cc_AWPROT), + .s_axi_awqos(m00_couplers_to_auto_cc_AWQOS), + .s_axi_awready(m00_couplers_to_auto_cc_AWREADY), + .s_axi_awregion(m00_couplers_to_auto_cc_AWREGION), + .s_axi_awsize(m00_couplers_to_auto_cc_AWSIZE), + .s_axi_awvalid(m00_couplers_to_auto_cc_AWVALID), + .s_axi_bid(m00_couplers_to_auto_cc_BID), + .s_axi_bready(m00_couplers_to_auto_cc_BREADY), + .s_axi_bresp(m00_couplers_to_auto_cc_BRESP), + .s_axi_bvalid(m00_couplers_to_auto_cc_BVALID), + .s_axi_rdata(m00_couplers_to_auto_cc_RDATA), + .s_axi_rid(m00_couplers_to_auto_cc_RID), + .s_axi_rlast(m00_couplers_to_auto_cc_RLAST), + .s_axi_rready(m00_couplers_to_auto_cc_RREADY), + .s_axi_rresp(m00_couplers_to_auto_cc_RRESP), + .s_axi_rvalid(m00_couplers_to_auto_cc_RVALID), + .s_axi_wdata(m00_couplers_to_auto_cc_WDATA), + .s_axi_wlast(m00_couplers_to_auto_cc_WLAST), + .s_axi_wready(m00_couplers_to_auto_cc_WREADY), + .s_axi_wstrb(m00_couplers_to_auto_cc_WSTRB), + .s_axi_wvalid(m00_couplers_to_auto_cc_WVALID)); +endmodule + +module m01_couplers_imp_16V7BMJ + (M_ACLK, + M_ARESETN, + M_AXI_araddr, + M_AXI_arburst, + M_AXI_arcache, + M_AXI_arid, + M_AXI_arlen, + M_AXI_arlock, + M_AXI_arprot, + M_AXI_arqos, + M_AXI_arready, + M_AXI_arsize, + M_AXI_arvalid, + M_AXI_awaddr, + M_AXI_awburst, + M_AXI_awcache, + M_AXI_awid, + M_AXI_awlen, + M_AXI_awlock, + M_AXI_awprot, + M_AXI_awqos, + M_AXI_awready, + M_AXI_awsize, + M_AXI_awvalid, + M_AXI_bid, + M_AXI_bready, + M_AXI_bresp, + M_AXI_bvalid, + M_AXI_rdata, + M_AXI_rid, + M_AXI_rlast, + M_AXI_rready, + M_AXI_rresp, + M_AXI_rvalid, + M_AXI_wdata, + M_AXI_wlast, + M_AXI_wready, + M_AXI_wstrb, + M_AXI_wvalid, + S_ACLK, + S_ARESETN, + S_AXI_araddr, + S_AXI_arburst, + S_AXI_arcache, + S_AXI_arid, + S_AXI_arlen, + S_AXI_arlock, + S_AXI_arprot, + S_AXI_arqos, + S_AXI_arready, + S_AXI_arregion, + S_AXI_arsize, + S_AXI_arvalid, + S_AXI_awaddr, + S_AXI_awburst, + S_AXI_awcache, + S_AXI_awid, + S_AXI_awlen, + S_AXI_awlock, + S_AXI_awprot, + S_AXI_awqos, + S_AXI_awready, + S_AXI_awregion, + S_AXI_awsize, + S_AXI_awvalid, + S_AXI_bid, + S_AXI_bready, + S_AXI_bresp, + S_AXI_bvalid, + S_AXI_rdata, + S_AXI_rid, + S_AXI_rlast, + S_AXI_rready, + S_AXI_rresp, + S_AXI_rvalid, + S_AXI_wdata, + S_AXI_wlast, + S_AXI_wready, + S_AXI_wstrb, + S_AXI_wvalid); + input M_ACLK; + input [7:0]M_ARESETN; + output [30:0]M_AXI_araddr; + output [1:0]M_AXI_arburst; + output [3:0]M_AXI_arcache; + output [3:0]M_AXI_arid; + output [7:0]M_AXI_arlen; + output M_AXI_arlock; + output [2:0]M_AXI_arprot; + output [3:0]M_AXI_arqos; + input M_AXI_arready; + output [2:0]M_AXI_arsize; + output M_AXI_arvalid; + output [30:0]M_AXI_awaddr; + output [1:0]M_AXI_awburst; + output [3:0]M_AXI_awcache; + output [3:0]M_AXI_awid; + output [7:0]M_AXI_awlen; + output M_AXI_awlock; + output [2:0]M_AXI_awprot; + output [3:0]M_AXI_awqos; + input M_AXI_awready; + output [2:0]M_AXI_awsize; + output M_AXI_awvalid; + input [3:0]M_AXI_bid; + output M_AXI_bready; + input [1:0]M_AXI_bresp; + input M_AXI_bvalid; + input [63:0]M_AXI_rdata; + input [3:0]M_AXI_rid; + input M_AXI_rlast; + output M_AXI_rready; + input [1:0]M_AXI_rresp; + input M_AXI_rvalid; + output [63:0]M_AXI_wdata; + output M_AXI_wlast; + input M_AXI_wready; + output [7:0]M_AXI_wstrb; + output M_AXI_wvalid; + input S_ACLK; + input S_ARESETN; + input [63:0]S_AXI_araddr; + input [1:0]S_AXI_arburst; + input [3:0]S_AXI_arcache; + input [3:0]S_AXI_arid; + input [7:0]S_AXI_arlen; + input [0:0]S_AXI_arlock; + input [2:0]S_AXI_arprot; + input [3:0]S_AXI_arqos; + output S_AXI_arready; + input [3:0]S_AXI_arregion; + input [2:0]S_AXI_arsize; + input S_AXI_arvalid; + input [63:0]S_AXI_awaddr; + input [1:0]S_AXI_awburst; + input [3:0]S_AXI_awcache; + input [3:0]S_AXI_awid; + input [7:0]S_AXI_awlen; + input [0:0]S_AXI_awlock; + input [2:0]S_AXI_awprot; + input [3:0]S_AXI_awqos; + output S_AXI_awready; + input [3:0]S_AXI_awregion; + input [2:0]S_AXI_awsize; + input S_AXI_awvalid; + output [3:0]S_AXI_bid; + input S_AXI_bready; + output [1:0]S_AXI_bresp; + output S_AXI_bvalid; + output [63:0]S_AXI_rdata; + output [3:0]S_AXI_rid; + output S_AXI_rlast; + input S_AXI_rready; + output [1:0]S_AXI_rresp; + output S_AXI_rvalid; + input [63:0]S_AXI_wdata; + input S_AXI_wlast; + output S_AXI_wready; + input [7:0]S_AXI_wstrb; + input S_AXI_wvalid; + + wire M_ACLK_1; + wire [7:0]M_ARESETN_1; + wire S_ACLK_1; + wire S_ARESETN_1; + wire [30:0]auto_cc_to_m01_couplers_ARADDR; + wire [1:0]auto_cc_to_m01_couplers_ARBURST; + wire [3:0]auto_cc_to_m01_couplers_ARCACHE; + wire [3:0]auto_cc_to_m01_couplers_ARID; + wire [7:0]auto_cc_to_m01_couplers_ARLEN; + wire [0:0]auto_cc_to_m01_couplers_ARLOCK; + wire [2:0]auto_cc_to_m01_couplers_ARPROT; + wire [3:0]auto_cc_to_m01_couplers_ARQOS; + wire auto_cc_to_m01_couplers_ARREADY; + wire [2:0]auto_cc_to_m01_couplers_ARSIZE; + wire auto_cc_to_m01_couplers_ARVALID; + wire [30:0]auto_cc_to_m01_couplers_AWADDR; + wire [1:0]auto_cc_to_m01_couplers_AWBURST; + wire [3:0]auto_cc_to_m01_couplers_AWCACHE; + wire [3:0]auto_cc_to_m01_couplers_AWID; + wire [7:0]auto_cc_to_m01_couplers_AWLEN; + wire [0:0]auto_cc_to_m01_couplers_AWLOCK; + wire [2:0]auto_cc_to_m01_couplers_AWPROT; + wire [3:0]auto_cc_to_m01_couplers_AWQOS; + wire auto_cc_to_m01_couplers_AWREADY; + wire [2:0]auto_cc_to_m01_couplers_AWSIZE; + wire auto_cc_to_m01_couplers_AWVALID; + wire [3:0]auto_cc_to_m01_couplers_BID; + wire auto_cc_to_m01_couplers_BREADY; + wire [1:0]auto_cc_to_m01_couplers_BRESP; + wire auto_cc_to_m01_couplers_BVALID; + wire [63:0]auto_cc_to_m01_couplers_RDATA; + wire [3:0]auto_cc_to_m01_couplers_RID; + wire auto_cc_to_m01_couplers_RLAST; + wire auto_cc_to_m01_couplers_RREADY; + wire [1:0]auto_cc_to_m01_couplers_RRESP; + wire auto_cc_to_m01_couplers_RVALID; + wire [63:0]auto_cc_to_m01_couplers_WDATA; + wire auto_cc_to_m01_couplers_WLAST; + wire auto_cc_to_m01_couplers_WREADY; + wire [7:0]auto_cc_to_m01_couplers_WSTRB; + wire auto_cc_to_m01_couplers_WVALID; + wire [63:0]m01_couplers_to_auto_cc_ARADDR; + wire [1:0]m01_couplers_to_auto_cc_ARBURST; + wire [3:0]m01_couplers_to_auto_cc_ARCACHE; + wire [3:0]m01_couplers_to_auto_cc_ARID; + wire [7:0]m01_couplers_to_auto_cc_ARLEN; + wire [0:0]m01_couplers_to_auto_cc_ARLOCK; + wire [2:0]m01_couplers_to_auto_cc_ARPROT; + wire [3:0]m01_couplers_to_auto_cc_ARQOS; + wire m01_couplers_to_auto_cc_ARREADY; + wire [3:0]m01_couplers_to_auto_cc_ARREGION; + wire [2:0]m01_couplers_to_auto_cc_ARSIZE; + wire m01_couplers_to_auto_cc_ARVALID; + wire [63:0]m01_couplers_to_auto_cc_AWADDR; + wire [1:0]m01_couplers_to_auto_cc_AWBURST; + wire [3:0]m01_couplers_to_auto_cc_AWCACHE; + wire [3:0]m01_couplers_to_auto_cc_AWID; + wire [7:0]m01_couplers_to_auto_cc_AWLEN; + wire [0:0]m01_couplers_to_auto_cc_AWLOCK; + wire [2:0]m01_couplers_to_auto_cc_AWPROT; + wire [3:0]m01_couplers_to_auto_cc_AWQOS; + wire m01_couplers_to_auto_cc_AWREADY; + wire [3:0]m01_couplers_to_auto_cc_AWREGION; + wire [2:0]m01_couplers_to_auto_cc_AWSIZE; + wire m01_couplers_to_auto_cc_AWVALID; + wire [3:0]m01_couplers_to_auto_cc_BID; + wire m01_couplers_to_auto_cc_BREADY; + wire [1:0]m01_couplers_to_auto_cc_BRESP; + wire m01_couplers_to_auto_cc_BVALID; + wire [63:0]m01_couplers_to_auto_cc_RDATA; + wire [3:0]m01_couplers_to_auto_cc_RID; + wire m01_couplers_to_auto_cc_RLAST; + wire m01_couplers_to_auto_cc_RREADY; + wire [1:0]m01_couplers_to_auto_cc_RRESP; + wire m01_couplers_to_auto_cc_RVALID; + wire [63:0]m01_couplers_to_auto_cc_WDATA; + wire m01_couplers_to_auto_cc_WLAST; + wire m01_couplers_to_auto_cc_WREADY; + wire [7:0]m01_couplers_to_auto_cc_WSTRB; + wire m01_couplers_to_auto_cc_WVALID; + + assign M_ACLK_1 = M_ACLK; + assign M_ARESETN_1 = M_ARESETN[7:0]; + assign M_AXI_araddr[30:0] = auto_cc_to_m01_couplers_ARADDR; + assign M_AXI_arburst[1:0] = auto_cc_to_m01_couplers_ARBURST; + assign M_AXI_arcache[3:0] = auto_cc_to_m01_couplers_ARCACHE; + assign M_AXI_arid[3:0] = auto_cc_to_m01_couplers_ARID; + assign M_AXI_arlen[7:0] = auto_cc_to_m01_couplers_ARLEN; + assign M_AXI_arlock = auto_cc_to_m01_couplers_ARLOCK; + assign M_AXI_arprot[2:0] = auto_cc_to_m01_couplers_ARPROT; + assign M_AXI_arqos[3:0] = auto_cc_to_m01_couplers_ARQOS; + assign M_AXI_arsize[2:0] = auto_cc_to_m01_couplers_ARSIZE; + assign M_AXI_arvalid = auto_cc_to_m01_couplers_ARVALID; + assign M_AXI_awaddr[30:0] = auto_cc_to_m01_couplers_AWADDR; + assign M_AXI_awburst[1:0] = auto_cc_to_m01_couplers_AWBURST; + assign M_AXI_awcache[3:0] = auto_cc_to_m01_couplers_AWCACHE; + assign M_AXI_awid[3:0] = auto_cc_to_m01_couplers_AWID; + assign M_AXI_awlen[7:0] = auto_cc_to_m01_couplers_AWLEN; + assign M_AXI_awlock = auto_cc_to_m01_couplers_AWLOCK; + assign M_AXI_awprot[2:0] = auto_cc_to_m01_couplers_AWPROT; + assign M_AXI_awqos[3:0] = auto_cc_to_m01_couplers_AWQOS; + assign M_AXI_awsize[2:0] = auto_cc_to_m01_couplers_AWSIZE; + assign M_AXI_awvalid = auto_cc_to_m01_couplers_AWVALID; + assign M_AXI_bready = auto_cc_to_m01_couplers_BREADY; + assign M_AXI_rready = auto_cc_to_m01_couplers_RREADY; + assign M_AXI_wdata[63:0] = auto_cc_to_m01_couplers_WDATA; + assign M_AXI_wlast = auto_cc_to_m01_couplers_WLAST; + assign M_AXI_wstrb[7:0] = auto_cc_to_m01_couplers_WSTRB; + assign M_AXI_wvalid = auto_cc_to_m01_couplers_WVALID; + assign S_ACLK_1 = S_ACLK; + assign S_ARESETN_1 = S_ARESETN; + assign S_AXI_arready = m01_couplers_to_auto_cc_ARREADY; + assign S_AXI_awready = m01_couplers_to_auto_cc_AWREADY; + assign S_AXI_bid[3:0] = m01_couplers_to_auto_cc_BID; + assign S_AXI_bresp[1:0] = m01_couplers_to_auto_cc_BRESP; + assign S_AXI_bvalid = m01_couplers_to_auto_cc_BVALID; + assign S_AXI_rdata[63:0] = m01_couplers_to_auto_cc_RDATA; + assign S_AXI_rid[3:0] = m01_couplers_to_auto_cc_RID; + assign S_AXI_rlast = m01_couplers_to_auto_cc_RLAST; + assign S_AXI_rresp[1:0] = m01_couplers_to_auto_cc_RRESP; + assign S_AXI_rvalid = m01_couplers_to_auto_cc_RVALID; + assign S_AXI_wready = m01_couplers_to_auto_cc_WREADY; + assign auto_cc_to_m01_couplers_ARREADY = M_AXI_arready; + assign auto_cc_to_m01_couplers_AWREADY = M_AXI_awready; + assign auto_cc_to_m01_couplers_BID = M_AXI_bid[3:0]; + assign auto_cc_to_m01_couplers_BRESP = M_AXI_bresp[1:0]; + assign auto_cc_to_m01_couplers_BVALID = M_AXI_bvalid; + assign auto_cc_to_m01_couplers_RDATA = M_AXI_rdata[63:0]; + assign auto_cc_to_m01_couplers_RID = M_AXI_rid[3:0]; + assign auto_cc_to_m01_couplers_RLAST = M_AXI_rlast; + assign auto_cc_to_m01_couplers_RRESP = M_AXI_rresp[1:0]; + assign auto_cc_to_m01_couplers_RVALID = M_AXI_rvalid; + assign auto_cc_to_m01_couplers_WREADY = M_AXI_wready; + assign m01_couplers_to_auto_cc_ARADDR = S_AXI_araddr[63:0]; + assign m01_couplers_to_auto_cc_ARBURST = S_AXI_arburst[1:0]; + assign m01_couplers_to_auto_cc_ARCACHE = S_AXI_arcache[3:0]; + assign m01_couplers_to_auto_cc_ARID = S_AXI_arid[3:0]; + assign m01_couplers_to_auto_cc_ARLEN = S_AXI_arlen[7:0]; + assign m01_couplers_to_auto_cc_ARLOCK = S_AXI_arlock[0]; + assign m01_couplers_to_auto_cc_ARPROT = S_AXI_arprot[2:0]; + assign m01_couplers_to_auto_cc_ARQOS = S_AXI_arqos[3:0]; + assign m01_couplers_to_auto_cc_ARREGION = S_AXI_arregion[3:0]; + assign m01_couplers_to_auto_cc_ARSIZE = S_AXI_arsize[2:0]; + assign m01_couplers_to_auto_cc_ARVALID = S_AXI_arvalid; + assign m01_couplers_to_auto_cc_AWADDR = S_AXI_awaddr[63:0]; + assign m01_couplers_to_auto_cc_AWBURST = S_AXI_awburst[1:0]; + assign m01_couplers_to_auto_cc_AWCACHE = S_AXI_awcache[3:0]; + assign m01_couplers_to_auto_cc_AWID = S_AXI_awid[3:0]; + assign m01_couplers_to_auto_cc_AWLEN = S_AXI_awlen[7:0]; + assign m01_couplers_to_auto_cc_AWLOCK = S_AXI_awlock[0]; + assign m01_couplers_to_auto_cc_AWPROT = S_AXI_awprot[2:0]; + assign m01_couplers_to_auto_cc_AWQOS = S_AXI_awqos[3:0]; + assign m01_couplers_to_auto_cc_AWREGION = S_AXI_awregion[3:0]; + assign m01_couplers_to_auto_cc_AWSIZE = S_AXI_awsize[2:0]; + assign m01_couplers_to_auto_cc_AWVALID = S_AXI_awvalid; + assign m01_couplers_to_auto_cc_BREADY = S_AXI_bready; + assign m01_couplers_to_auto_cc_RREADY = S_AXI_rready; + assign m01_couplers_to_auto_cc_WDATA = S_AXI_wdata[63:0]; + assign m01_couplers_to_auto_cc_WLAST = S_AXI_wlast; + assign m01_couplers_to_auto_cc_WSTRB = S_AXI_wstrb[7:0]; + assign m01_couplers_to_auto_cc_WVALID = S_AXI_wvalid; + Top_auto_cc_1 auto_cc + (.m_axi_aclk(M_ACLK_1), + .m_axi_araddr(auto_cc_to_m01_couplers_ARADDR), + .m_axi_arburst(auto_cc_to_m01_couplers_ARBURST), + .m_axi_arcache(auto_cc_to_m01_couplers_ARCACHE), + .m_axi_aresetn(M_ARESETN_1[0]), + .m_axi_arid(auto_cc_to_m01_couplers_ARID), + .m_axi_arlen(auto_cc_to_m01_couplers_ARLEN), + .m_axi_arlock(auto_cc_to_m01_couplers_ARLOCK), + .m_axi_arprot(auto_cc_to_m01_couplers_ARPROT), + .m_axi_arqos(auto_cc_to_m01_couplers_ARQOS), + .m_axi_arready(auto_cc_to_m01_couplers_ARREADY), + .m_axi_arsize(auto_cc_to_m01_couplers_ARSIZE), + .m_axi_arvalid(auto_cc_to_m01_couplers_ARVALID), + .m_axi_awaddr(auto_cc_to_m01_couplers_AWADDR), + .m_axi_awburst(auto_cc_to_m01_couplers_AWBURST), + .m_axi_awcache(auto_cc_to_m01_couplers_AWCACHE), + .m_axi_awid(auto_cc_to_m01_couplers_AWID), + .m_axi_awlen(auto_cc_to_m01_couplers_AWLEN), + .m_axi_awlock(auto_cc_to_m01_couplers_AWLOCK), + .m_axi_awprot(auto_cc_to_m01_couplers_AWPROT), + .m_axi_awqos(auto_cc_to_m01_couplers_AWQOS), + .m_axi_awready(auto_cc_to_m01_couplers_AWREADY), + .m_axi_awsize(auto_cc_to_m01_couplers_AWSIZE), + .m_axi_awvalid(auto_cc_to_m01_couplers_AWVALID), + .m_axi_bid(auto_cc_to_m01_couplers_BID), + .m_axi_bready(auto_cc_to_m01_couplers_BREADY), + .m_axi_bresp(auto_cc_to_m01_couplers_BRESP), + .m_axi_bvalid(auto_cc_to_m01_couplers_BVALID), + .m_axi_rdata(auto_cc_to_m01_couplers_RDATA), + .m_axi_rid(auto_cc_to_m01_couplers_RID), + .m_axi_rlast(auto_cc_to_m01_couplers_RLAST), + .m_axi_rready(auto_cc_to_m01_couplers_RREADY), + .m_axi_rresp(auto_cc_to_m01_couplers_RRESP), + .m_axi_rvalid(auto_cc_to_m01_couplers_RVALID), + .m_axi_wdata(auto_cc_to_m01_couplers_WDATA), + .m_axi_wlast(auto_cc_to_m01_couplers_WLAST), + .m_axi_wready(auto_cc_to_m01_couplers_WREADY), + .m_axi_wstrb(auto_cc_to_m01_couplers_WSTRB), + .m_axi_wvalid(auto_cc_to_m01_couplers_WVALID), + .s_axi_aclk(S_ACLK_1), + .s_axi_araddr(m01_couplers_to_auto_cc_ARADDR[30:0]), + .s_axi_arburst(m01_couplers_to_auto_cc_ARBURST), + .s_axi_arcache(m01_couplers_to_auto_cc_ARCACHE), + .s_axi_aresetn(S_ARESETN_1), + .s_axi_arid(m01_couplers_to_auto_cc_ARID), + .s_axi_arlen(m01_couplers_to_auto_cc_ARLEN), + .s_axi_arlock(m01_couplers_to_auto_cc_ARLOCK), + .s_axi_arprot(m01_couplers_to_auto_cc_ARPROT), + .s_axi_arqos(m01_couplers_to_auto_cc_ARQOS), + .s_axi_arready(m01_couplers_to_auto_cc_ARREADY), + .s_axi_arregion(m01_couplers_to_auto_cc_ARREGION), + .s_axi_arsize(m01_couplers_to_auto_cc_ARSIZE), + .s_axi_arvalid(m01_couplers_to_auto_cc_ARVALID), + .s_axi_awaddr(m01_couplers_to_auto_cc_AWADDR[30:0]), + .s_axi_awburst(m01_couplers_to_auto_cc_AWBURST), + .s_axi_awcache(m01_couplers_to_auto_cc_AWCACHE), + .s_axi_awid(m01_couplers_to_auto_cc_AWID), + .s_axi_awlen(m01_couplers_to_auto_cc_AWLEN), + .s_axi_awlock(m01_couplers_to_auto_cc_AWLOCK), + .s_axi_awprot(m01_couplers_to_auto_cc_AWPROT), + .s_axi_awqos(m01_couplers_to_auto_cc_AWQOS), + .s_axi_awready(m01_couplers_to_auto_cc_AWREADY), + .s_axi_awregion(m01_couplers_to_auto_cc_AWREGION), + .s_axi_awsize(m01_couplers_to_auto_cc_AWSIZE), + .s_axi_awvalid(m01_couplers_to_auto_cc_AWVALID), + .s_axi_bid(m01_couplers_to_auto_cc_BID), + .s_axi_bready(m01_couplers_to_auto_cc_BREADY), + .s_axi_bresp(m01_couplers_to_auto_cc_BRESP), + .s_axi_bvalid(m01_couplers_to_auto_cc_BVALID), + .s_axi_rdata(m01_couplers_to_auto_cc_RDATA), + .s_axi_rid(m01_couplers_to_auto_cc_RID), + .s_axi_rlast(m01_couplers_to_auto_cc_RLAST), + .s_axi_rready(m01_couplers_to_auto_cc_RREADY), + .s_axi_rresp(m01_couplers_to_auto_cc_RRESP), + .s_axi_rvalid(m01_couplers_to_auto_cc_RVALID), + .s_axi_wdata(m01_couplers_to_auto_cc_WDATA), + .s_axi_wlast(m01_couplers_to_auto_cc_WLAST), + .s_axi_wready(m01_couplers_to_auto_cc_WREADY), + .s_axi_wstrb(m01_couplers_to_auto_cc_WSTRB), + .s_axi_wvalid(m01_couplers_to_auto_cc_WVALID)); +endmodule + +module m02_couplers_imp_B0MBTH + (M_ACLK, + M_ARESETN, + M_AXI_araddr, + M_AXI_arburst, + M_AXI_arcache, + M_AXI_arid, + M_AXI_arlen, + M_AXI_arlock, + M_AXI_arprot, + M_AXI_arready, + M_AXI_arsize, + M_AXI_arvalid, + M_AXI_awaddr, + M_AXI_awburst, + M_AXI_awcache, + M_AXI_awid, + M_AXI_awlen, + M_AXI_awlock, + M_AXI_awprot, + M_AXI_awready, + M_AXI_awsize, + M_AXI_awvalid, + M_AXI_bid, + M_AXI_bready, + M_AXI_bresp, + M_AXI_bvalid, + M_AXI_rdata, + M_AXI_rid, + M_AXI_rlast, + M_AXI_rready, + M_AXI_rresp, + M_AXI_rvalid, + M_AXI_wdata, + M_AXI_wlast, + M_AXI_wready, + M_AXI_wstrb, + M_AXI_wvalid, + S_ACLK, + S_ARESETN, + S_AXI_araddr, + S_AXI_arburst, + S_AXI_arcache, + S_AXI_arid, + S_AXI_arlen, + S_AXI_arlock, + S_AXI_arprot, + S_AXI_arready, + S_AXI_arsize, + S_AXI_arvalid, + S_AXI_awaddr, + S_AXI_awburst, + S_AXI_awcache, + S_AXI_awid, + S_AXI_awlen, + S_AXI_awlock, + S_AXI_awprot, + S_AXI_awready, + S_AXI_awsize, + S_AXI_awvalid, + S_AXI_bid, + S_AXI_bready, + S_AXI_bresp, + S_AXI_bvalid, + S_AXI_rdata, + S_AXI_rid, + S_AXI_rlast, + S_AXI_rready, + S_AXI_rresp, + S_AXI_rvalid, + S_AXI_wdata, + S_AXI_wlast, + S_AXI_wready, + S_AXI_wstrb, + S_AXI_wvalid); + input M_ACLK; + input M_ARESETN; + output [63:0]M_AXI_araddr; + output [1:0]M_AXI_arburst; + output [3:0]M_AXI_arcache; + output [3:0]M_AXI_arid; + output [7:0]M_AXI_arlen; + output M_AXI_arlock; + output [2:0]M_AXI_arprot; + input M_AXI_arready; + output [2:0]M_AXI_arsize; + output M_AXI_arvalid; + output [63:0]M_AXI_awaddr; + output [1:0]M_AXI_awburst; + output [3:0]M_AXI_awcache; + output [3:0]M_AXI_awid; + output [7:0]M_AXI_awlen; + output M_AXI_awlock; + output [2:0]M_AXI_awprot; + input M_AXI_awready; + output [2:0]M_AXI_awsize; + output M_AXI_awvalid; + input [3:0]M_AXI_bid; + output M_AXI_bready; + input [1:0]M_AXI_bresp; + input M_AXI_bvalid; + input [63:0]M_AXI_rdata; + input [3:0]M_AXI_rid; + input M_AXI_rlast; + output M_AXI_rready; + input [1:0]M_AXI_rresp; + input M_AXI_rvalid; + output [63:0]M_AXI_wdata; + output M_AXI_wlast; + input M_AXI_wready; + output [7:0]M_AXI_wstrb; + output M_AXI_wvalid; + input S_ACLK; + input S_ARESETN; + input [63:0]S_AXI_araddr; + input [1:0]S_AXI_arburst; + input [3:0]S_AXI_arcache; + input [3:0]S_AXI_arid; + input [7:0]S_AXI_arlen; + input S_AXI_arlock; + input [2:0]S_AXI_arprot; + output S_AXI_arready; + input [2:0]S_AXI_arsize; + input S_AXI_arvalid; + input [63:0]S_AXI_awaddr; + input [1:0]S_AXI_awburst; + input [3:0]S_AXI_awcache; + input [3:0]S_AXI_awid; + input [7:0]S_AXI_awlen; + input S_AXI_awlock; + input [2:0]S_AXI_awprot; + output S_AXI_awready; + input [2:0]S_AXI_awsize; + input S_AXI_awvalid; + output [3:0]S_AXI_bid; + input S_AXI_bready; + output [1:0]S_AXI_bresp; + output S_AXI_bvalid; + output [63:0]S_AXI_rdata; + output [3:0]S_AXI_rid; + output S_AXI_rlast; + input S_AXI_rready; + output [1:0]S_AXI_rresp; + output S_AXI_rvalid; + input [63:0]S_AXI_wdata; + input S_AXI_wlast; + output S_AXI_wready; + input [7:0]S_AXI_wstrb; + input S_AXI_wvalid; + + wire [63:0]m02_couplers_to_m02_couplers_ARADDR; + wire [1:0]m02_couplers_to_m02_couplers_ARBURST; + wire [3:0]m02_couplers_to_m02_couplers_ARCACHE; + wire [3:0]m02_couplers_to_m02_couplers_ARID; + wire [7:0]m02_couplers_to_m02_couplers_ARLEN; + wire m02_couplers_to_m02_couplers_ARLOCK; + wire [2:0]m02_couplers_to_m02_couplers_ARPROT; + wire m02_couplers_to_m02_couplers_ARREADY; + wire [2:0]m02_couplers_to_m02_couplers_ARSIZE; + wire m02_couplers_to_m02_couplers_ARVALID; + wire [63:0]m02_couplers_to_m02_couplers_AWADDR; + wire [1:0]m02_couplers_to_m02_couplers_AWBURST; + wire [3:0]m02_couplers_to_m02_couplers_AWCACHE; + wire [3:0]m02_couplers_to_m02_couplers_AWID; + wire [7:0]m02_couplers_to_m02_couplers_AWLEN; + wire m02_couplers_to_m02_couplers_AWLOCK; + wire [2:0]m02_couplers_to_m02_couplers_AWPROT; + wire m02_couplers_to_m02_couplers_AWREADY; + wire [2:0]m02_couplers_to_m02_couplers_AWSIZE; + wire m02_couplers_to_m02_couplers_AWVALID; + wire [3:0]m02_couplers_to_m02_couplers_BID; + wire m02_couplers_to_m02_couplers_BREADY; + wire [1:0]m02_couplers_to_m02_couplers_BRESP; + wire m02_couplers_to_m02_couplers_BVALID; + wire [63:0]m02_couplers_to_m02_couplers_RDATA; + wire [3:0]m02_couplers_to_m02_couplers_RID; + wire m02_couplers_to_m02_couplers_RLAST; + wire m02_couplers_to_m02_couplers_RREADY; + wire [1:0]m02_couplers_to_m02_couplers_RRESP; + wire m02_couplers_to_m02_couplers_RVALID; + wire [63:0]m02_couplers_to_m02_couplers_WDATA; + wire m02_couplers_to_m02_couplers_WLAST; + wire m02_couplers_to_m02_couplers_WREADY; + wire [7:0]m02_couplers_to_m02_couplers_WSTRB; + wire m02_couplers_to_m02_couplers_WVALID; + + assign M_AXI_araddr[63:0] = m02_couplers_to_m02_couplers_ARADDR; + assign M_AXI_arburst[1:0] = m02_couplers_to_m02_couplers_ARBURST; + assign M_AXI_arcache[3:0] = m02_couplers_to_m02_couplers_ARCACHE; + assign M_AXI_arid[3:0] = m02_couplers_to_m02_couplers_ARID; + assign M_AXI_arlen[7:0] = m02_couplers_to_m02_couplers_ARLEN; + assign M_AXI_arlock = m02_couplers_to_m02_couplers_ARLOCK; + assign M_AXI_arprot[2:0] = m02_couplers_to_m02_couplers_ARPROT; + assign M_AXI_arsize[2:0] = m02_couplers_to_m02_couplers_ARSIZE; + assign M_AXI_arvalid = m02_couplers_to_m02_couplers_ARVALID; + assign M_AXI_awaddr[63:0] = m02_couplers_to_m02_couplers_AWADDR; + assign M_AXI_awburst[1:0] = m02_couplers_to_m02_couplers_AWBURST; + assign M_AXI_awcache[3:0] = m02_couplers_to_m02_couplers_AWCACHE; + assign M_AXI_awid[3:0] = m02_couplers_to_m02_couplers_AWID; + assign M_AXI_awlen[7:0] = m02_couplers_to_m02_couplers_AWLEN; + assign M_AXI_awlock = m02_couplers_to_m02_couplers_AWLOCK; + assign M_AXI_awprot[2:0] = m02_couplers_to_m02_couplers_AWPROT; + assign M_AXI_awsize[2:0] = m02_couplers_to_m02_couplers_AWSIZE; + assign M_AXI_awvalid = m02_couplers_to_m02_couplers_AWVALID; + assign M_AXI_bready = m02_couplers_to_m02_couplers_BREADY; + assign M_AXI_rready = m02_couplers_to_m02_couplers_RREADY; + assign M_AXI_wdata[63:0] = m02_couplers_to_m02_couplers_WDATA; + assign M_AXI_wlast = m02_couplers_to_m02_couplers_WLAST; + assign M_AXI_wstrb[7:0] = m02_couplers_to_m02_couplers_WSTRB; + assign M_AXI_wvalid = m02_couplers_to_m02_couplers_WVALID; + assign S_AXI_arready = m02_couplers_to_m02_couplers_ARREADY; + assign S_AXI_awready = m02_couplers_to_m02_couplers_AWREADY; + assign S_AXI_bid[3:0] = m02_couplers_to_m02_couplers_BID; + assign S_AXI_bresp[1:0] = m02_couplers_to_m02_couplers_BRESP; + assign S_AXI_bvalid = m02_couplers_to_m02_couplers_BVALID; + assign S_AXI_rdata[63:0] = m02_couplers_to_m02_couplers_RDATA; + assign S_AXI_rid[3:0] = m02_couplers_to_m02_couplers_RID; + assign S_AXI_rlast = m02_couplers_to_m02_couplers_RLAST; + assign S_AXI_rresp[1:0] = m02_couplers_to_m02_couplers_RRESP; + assign S_AXI_rvalid = m02_couplers_to_m02_couplers_RVALID; + assign S_AXI_wready = m02_couplers_to_m02_couplers_WREADY; + assign m02_couplers_to_m02_couplers_ARADDR = S_AXI_araddr[63:0]; + assign m02_couplers_to_m02_couplers_ARBURST = S_AXI_arburst[1:0]; + assign m02_couplers_to_m02_couplers_ARCACHE = S_AXI_arcache[3:0]; + assign m02_couplers_to_m02_couplers_ARID = S_AXI_arid[3:0]; + assign m02_couplers_to_m02_couplers_ARLEN = S_AXI_arlen[7:0]; + assign m02_couplers_to_m02_couplers_ARLOCK = S_AXI_arlock; + assign m02_couplers_to_m02_couplers_ARPROT = S_AXI_arprot[2:0]; + assign m02_couplers_to_m02_couplers_ARREADY = M_AXI_arready; + assign m02_couplers_to_m02_couplers_ARSIZE = S_AXI_arsize[2:0]; + assign m02_couplers_to_m02_couplers_ARVALID = S_AXI_arvalid; + assign m02_couplers_to_m02_couplers_AWADDR = S_AXI_awaddr[63:0]; + assign m02_couplers_to_m02_couplers_AWBURST = S_AXI_awburst[1:0]; + assign m02_couplers_to_m02_couplers_AWCACHE = S_AXI_awcache[3:0]; + assign m02_couplers_to_m02_couplers_AWID = S_AXI_awid[3:0]; + assign m02_couplers_to_m02_couplers_AWLEN = S_AXI_awlen[7:0]; + assign m02_couplers_to_m02_couplers_AWLOCK = S_AXI_awlock; + assign m02_couplers_to_m02_couplers_AWPROT = S_AXI_awprot[2:0]; + assign m02_couplers_to_m02_couplers_AWREADY = M_AXI_awready; + assign m02_couplers_to_m02_couplers_AWSIZE = S_AXI_awsize[2:0]; + assign m02_couplers_to_m02_couplers_AWVALID = S_AXI_awvalid; + assign m02_couplers_to_m02_couplers_BID = M_AXI_bid[3:0]; + assign m02_couplers_to_m02_couplers_BREADY = S_AXI_bready; + assign m02_couplers_to_m02_couplers_BRESP = M_AXI_bresp[1:0]; + assign m02_couplers_to_m02_couplers_BVALID = M_AXI_bvalid; + assign m02_couplers_to_m02_couplers_RDATA = M_AXI_rdata[63:0]; + assign m02_couplers_to_m02_couplers_RID = M_AXI_rid[3:0]; + assign m02_couplers_to_m02_couplers_RLAST = M_AXI_rlast; + assign m02_couplers_to_m02_couplers_RREADY = S_AXI_rready; + assign m02_couplers_to_m02_couplers_RRESP = M_AXI_rresp[1:0]; + assign m02_couplers_to_m02_couplers_RVALID = M_AXI_rvalid; + assign m02_couplers_to_m02_couplers_WDATA = S_AXI_wdata[63:0]; + assign m02_couplers_to_m02_couplers_WLAST = S_AXI_wlast; + assign m02_couplers_to_m02_couplers_WREADY = M_AXI_wready; + assign m02_couplers_to_m02_couplers_WSTRB = S_AXI_wstrb[7:0]; + assign m02_couplers_to_m02_couplers_WVALID = S_AXI_wvalid; +endmodule + +module s00_couplers_imp_1UB271G + (M_ACLK, + M_ARESETN, + M_AXI_araddr, + M_AXI_arburst, + M_AXI_arcache, + M_AXI_arid, + M_AXI_arlen, + M_AXI_arlock, + M_AXI_arprot, + M_AXI_arready, + M_AXI_arsize, + M_AXI_arvalid, + M_AXI_awaddr, + M_AXI_awburst, + M_AXI_awcache, + M_AXI_awid, + M_AXI_awlen, + M_AXI_awlock, + M_AXI_awprot, + M_AXI_awready, + M_AXI_awsize, + M_AXI_awvalid, + M_AXI_bid, + M_AXI_bready, + M_AXI_bresp, + M_AXI_bvalid, + M_AXI_rdata, + M_AXI_rid, + M_AXI_rlast, + M_AXI_rready, + M_AXI_rresp, + M_AXI_rvalid, + M_AXI_wdata, + M_AXI_wlast, + M_AXI_wready, + M_AXI_wstrb, + M_AXI_wvalid, + S_ACLK, + S_ARESETN, + S_AXI_araddr, + S_AXI_arburst, + S_AXI_arcache, + S_AXI_arid, + S_AXI_arlen, + S_AXI_arlock, + S_AXI_arprot, + S_AXI_arready, + S_AXI_arsize, + S_AXI_arvalid, + S_AXI_awaddr, + S_AXI_awburst, + S_AXI_awcache, + S_AXI_awid, + S_AXI_awlen, + S_AXI_awlock, + S_AXI_awprot, + S_AXI_awready, + S_AXI_awsize, + S_AXI_awvalid, + S_AXI_bid, + S_AXI_bready, + S_AXI_bresp, + S_AXI_bvalid, + S_AXI_rdata, + S_AXI_rid, + S_AXI_rlast, + S_AXI_rready, + S_AXI_rresp, + S_AXI_rvalid, + S_AXI_wdata, + S_AXI_wlast, + S_AXI_wready, + S_AXI_wstrb, + S_AXI_wvalid); + input M_ACLK; + input M_ARESETN; + output [63:0]M_AXI_araddr; + output [1:0]M_AXI_arburst; + output [3:0]M_AXI_arcache; + output [3:0]M_AXI_arid; + output [7:0]M_AXI_arlen; + output [0:0]M_AXI_arlock; + output [2:0]M_AXI_arprot; + input [0:0]M_AXI_arready; + output [2:0]M_AXI_arsize; + output [0:0]M_AXI_arvalid; + output [63:0]M_AXI_awaddr; + output [1:0]M_AXI_awburst; + output [3:0]M_AXI_awcache; + output [3:0]M_AXI_awid; + output [7:0]M_AXI_awlen; + output [0:0]M_AXI_awlock; + output [2:0]M_AXI_awprot; + input [0:0]M_AXI_awready; + output [2:0]M_AXI_awsize; + output [0:0]M_AXI_awvalid; + input [3:0]M_AXI_bid; + output [0:0]M_AXI_bready; + input [1:0]M_AXI_bresp; + input [0:0]M_AXI_bvalid; + input [63:0]M_AXI_rdata; + input [3:0]M_AXI_rid; + input [0:0]M_AXI_rlast; + output [0:0]M_AXI_rready; + input [1:0]M_AXI_rresp; + input [0:0]M_AXI_rvalid; + output [63:0]M_AXI_wdata; + output [0:0]M_AXI_wlast; + input [0:0]M_AXI_wready; + output [7:0]M_AXI_wstrb; + output [0:0]M_AXI_wvalid; + input S_ACLK; + input S_ARESETN; + input [63:0]S_AXI_araddr; + input [1:0]S_AXI_arburst; + input [3:0]S_AXI_arcache; + input [3:0]S_AXI_arid; + input [7:0]S_AXI_arlen; + input [0:0]S_AXI_arlock; + input [2:0]S_AXI_arprot; + output [0:0]S_AXI_arready; + input [2:0]S_AXI_arsize; + input [0:0]S_AXI_arvalid; + input [63:0]S_AXI_awaddr; + input [1:0]S_AXI_awburst; + input [3:0]S_AXI_awcache; + input [3:0]S_AXI_awid; + input [7:0]S_AXI_awlen; + input [0:0]S_AXI_awlock; + input [2:0]S_AXI_awprot; + output [0:0]S_AXI_awready; + input [2:0]S_AXI_awsize; + input [0:0]S_AXI_awvalid; + output [3:0]S_AXI_bid; + input [0:0]S_AXI_bready; + output [1:0]S_AXI_bresp; + output [0:0]S_AXI_bvalid; + output [63:0]S_AXI_rdata; + output [3:0]S_AXI_rid; + output [0:0]S_AXI_rlast; + input [0:0]S_AXI_rready; + output [1:0]S_AXI_rresp; + output [0:0]S_AXI_rvalid; + input [63:0]S_AXI_wdata; + input [0:0]S_AXI_wlast; + output [0:0]S_AXI_wready; + input [7:0]S_AXI_wstrb; + input [0:0]S_AXI_wvalid; + + wire [63:0]s00_couplers_to_s00_couplers_ARADDR; + wire [1:0]s00_couplers_to_s00_couplers_ARBURST; + wire [3:0]s00_couplers_to_s00_couplers_ARCACHE; + wire [3:0]s00_couplers_to_s00_couplers_ARID; + wire [7:0]s00_couplers_to_s00_couplers_ARLEN; + wire [0:0]s00_couplers_to_s00_couplers_ARLOCK; + wire [2:0]s00_couplers_to_s00_couplers_ARPROT; + wire [0:0]s00_couplers_to_s00_couplers_ARREADY; + wire [2:0]s00_couplers_to_s00_couplers_ARSIZE; + wire [0:0]s00_couplers_to_s00_couplers_ARVALID; + wire [63:0]s00_couplers_to_s00_couplers_AWADDR; + wire [1:0]s00_couplers_to_s00_couplers_AWBURST; + wire [3:0]s00_couplers_to_s00_couplers_AWCACHE; + wire [3:0]s00_couplers_to_s00_couplers_AWID; + wire [7:0]s00_couplers_to_s00_couplers_AWLEN; + wire [0:0]s00_couplers_to_s00_couplers_AWLOCK; + wire [2:0]s00_couplers_to_s00_couplers_AWPROT; + wire [0:0]s00_couplers_to_s00_couplers_AWREADY; + wire [2:0]s00_couplers_to_s00_couplers_AWSIZE; + wire [0:0]s00_couplers_to_s00_couplers_AWVALID; + wire [3:0]s00_couplers_to_s00_couplers_BID; + wire [0:0]s00_couplers_to_s00_couplers_BREADY; + wire [1:0]s00_couplers_to_s00_couplers_BRESP; + wire [0:0]s00_couplers_to_s00_couplers_BVALID; + wire [63:0]s00_couplers_to_s00_couplers_RDATA; + wire [3:0]s00_couplers_to_s00_couplers_RID; + wire [0:0]s00_couplers_to_s00_couplers_RLAST; + wire [0:0]s00_couplers_to_s00_couplers_RREADY; + wire [1:0]s00_couplers_to_s00_couplers_RRESP; + wire [0:0]s00_couplers_to_s00_couplers_RVALID; + wire [63:0]s00_couplers_to_s00_couplers_WDATA; + wire [0:0]s00_couplers_to_s00_couplers_WLAST; + wire [0:0]s00_couplers_to_s00_couplers_WREADY; + wire [7:0]s00_couplers_to_s00_couplers_WSTRB; + wire [0:0]s00_couplers_to_s00_couplers_WVALID; + + assign M_AXI_araddr[63:0] = s00_couplers_to_s00_couplers_ARADDR; + assign M_AXI_arburst[1:0] = s00_couplers_to_s00_couplers_ARBURST; + assign M_AXI_arcache[3:0] = s00_couplers_to_s00_couplers_ARCACHE; + assign M_AXI_arid[3:0] = s00_couplers_to_s00_couplers_ARID; + assign M_AXI_arlen[7:0] = s00_couplers_to_s00_couplers_ARLEN; + assign M_AXI_arlock[0] = s00_couplers_to_s00_couplers_ARLOCK; + assign M_AXI_arprot[2:0] = s00_couplers_to_s00_couplers_ARPROT; + assign M_AXI_arsize[2:0] = s00_couplers_to_s00_couplers_ARSIZE; + assign M_AXI_arvalid[0] = s00_couplers_to_s00_couplers_ARVALID; + assign M_AXI_awaddr[63:0] = s00_couplers_to_s00_couplers_AWADDR; + assign M_AXI_awburst[1:0] = s00_couplers_to_s00_couplers_AWBURST; + assign M_AXI_awcache[3:0] = s00_couplers_to_s00_couplers_AWCACHE; + assign M_AXI_awid[3:0] = s00_couplers_to_s00_couplers_AWID; + assign M_AXI_awlen[7:0] = s00_couplers_to_s00_couplers_AWLEN; + assign M_AXI_awlock[0] = s00_couplers_to_s00_couplers_AWLOCK; + assign M_AXI_awprot[2:0] = s00_couplers_to_s00_couplers_AWPROT; + assign M_AXI_awsize[2:0] = s00_couplers_to_s00_couplers_AWSIZE; + assign M_AXI_awvalid[0] = s00_couplers_to_s00_couplers_AWVALID; + assign M_AXI_bready[0] = s00_couplers_to_s00_couplers_BREADY; + assign M_AXI_rready[0] = s00_couplers_to_s00_couplers_RREADY; + assign M_AXI_wdata[63:0] = s00_couplers_to_s00_couplers_WDATA; + assign M_AXI_wlast[0] = s00_couplers_to_s00_couplers_WLAST; + assign M_AXI_wstrb[7:0] = s00_couplers_to_s00_couplers_WSTRB; + assign M_AXI_wvalid[0] = s00_couplers_to_s00_couplers_WVALID; + assign S_AXI_arready[0] = s00_couplers_to_s00_couplers_ARREADY; + assign S_AXI_awready[0] = s00_couplers_to_s00_couplers_AWREADY; + assign S_AXI_bid[3:0] = s00_couplers_to_s00_couplers_BID; + assign S_AXI_bresp[1:0] = s00_couplers_to_s00_couplers_BRESP; + assign S_AXI_bvalid[0] = s00_couplers_to_s00_couplers_BVALID; + assign S_AXI_rdata[63:0] = s00_couplers_to_s00_couplers_RDATA; + assign S_AXI_rid[3:0] = s00_couplers_to_s00_couplers_RID; + assign S_AXI_rlast[0] = s00_couplers_to_s00_couplers_RLAST; + assign S_AXI_rresp[1:0] = s00_couplers_to_s00_couplers_RRESP; + assign S_AXI_rvalid[0] = s00_couplers_to_s00_couplers_RVALID; + assign S_AXI_wready[0] = s00_couplers_to_s00_couplers_WREADY; + assign s00_couplers_to_s00_couplers_ARADDR = S_AXI_araddr[63:0]; + assign s00_couplers_to_s00_couplers_ARBURST = S_AXI_arburst[1:0]; + assign s00_couplers_to_s00_couplers_ARCACHE = S_AXI_arcache[3:0]; + assign s00_couplers_to_s00_couplers_ARID = S_AXI_arid[3:0]; + assign s00_couplers_to_s00_couplers_ARLEN = S_AXI_arlen[7:0]; + assign s00_couplers_to_s00_couplers_ARLOCK = S_AXI_arlock[0]; + assign s00_couplers_to_s00_couplers_ARPROT = S_AXI_arprot[2:0]; + assign s00_couplers_to_s00_couplers_ARREADY = M_AXI_arready[0]; + assign s00_couplers_to_s00_couplers_ARSIZE = S_AXI_arsize[2:0]; + assign s00_couplers_to_s00_couplers_ARVALID = S_AXI_arvalid[0]; + assign s00_couplers_to_s00_couplers_AWADDR = S_AXI_awaddr[63:0]; + assign s00_couplers_to_s00_couplers_AWBURST = S_AXI_awburst[1:0]; + assign s00_couplers_to_s00_couplers_AWCACHE = S_AXI_awcache[3:0]; + assign s00_couplers_to_s00_couplers_AWID = S_AXI_awid[3:0]; + assign s00_couplers_to_s00_couplers_AWLEN = S_AXI_awlen[7:0]; + assign s00_couplers_to_s00_couplers_AWLOCK = S_AXI_awlock[0]; + assign s00_couplers_to_s00_couplers_AWPROT = S_AXI_awprot[2:0]; + assign s00_couplers_to_s00_couplers_AWREADY = M_AXI_awready[0]; + assign s00_couplers_to_s00_couplers_AWSIZE = S_AXI_awsize[2:0]; + assign s00_couplers_to_s00_couplers_AWVALID = S_AXI_awvalid[0]; + assign s00_couplers_to_s00_couplers_BID = M_AXI_bid[3:0]; + assign s00_couplers_to_s00_couplers_BREADY = S_AXI_bready[0]; + assign s00_couplers_to_s00_couplers_BRESP = M_AXI_bresp[1:0]; + assign s00_couplers_to_s00_couplers_BVALID = M_AXI_bvalid[0]; + assign s00_couplers_to_s00_couplers_RDATA = M_AXI_rdata[63:0]; + assign s00_couplers_to_s00_couplers_RID = M_AXI_rid[3:0]; + assign s00_couplers_to_s00_couplers_RLAST = M_AXI_rlast[0]; + assign s00_couplers_to_s00_couplers_RREADY = S_AXI_rready[0]; + assign s00_couplers_to_s00_couplers_RRESP = M_AXI_rresp[1:0]; + assign s00_couplers_to_s00_couplers_RVALID = M_AXI_rvalid[0]; + assign s00_couplers_to_s00_couplers_WDATA = S_AXI_wdata[63:0]; + assign s00_couplers_to_s00_couplers_WLAST = S_AXI_wlast[0]; + assign s00_couplers_to_s00_couplers_WREADY = M_AXI_wready[0]; + assign s00_couplers_to_s00_couplers_WSTRB = S_AXI_wstrb[7:0]; + assign s00_couplers_to_s00_couplers_WVALID = S_AXI_wvalid[0]; endmodule diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_0/Top_auto_cc_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_0/Top_auto_cc_0.xci new file mode 100644 index 0000000..3f28b4f --- /dev/null +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_0/Top_auto_cc_0.xci @@ -0,0 +1,380 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "Top_auto_cc_0", + "cell_name": "axi_interconnect_0/m00_couplers/auto_cc", + "component_reference": "xilinx.com:ip:axi_clock_converter:2.1", + "ip_revision": "26", + "gen_directory": "../../../build/xdma_ddr.gen/sources_1/ip/Top_auto_cc_0", + "parameters": { + "component_parameters": { + "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "ADDR_WIDTH": [ { "value": "31", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "64", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ID_WIDTH": [ { "value": "4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RUSER_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "WUSER_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "BUSER_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ACLK_ASYNC": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SYNCHRONIZATION_STAGES": [ { "value": "3", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ACLK_RATIO": [ { "value": "1:2", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], + "Component_Name": [ { "value": "Top_auto_cc_0", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "C_FAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ], + "C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_ADDR_WIDTH": [ { "value": "31", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_ACLK_RATIO": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_M_AXI_ACLK_RATIO": [ { "value": "2", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_IS_ACLK_ASYNC": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_SUPPORTS_WRITE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_SUPPORTS_READ": [ { "value": "1", "resolve_type": "generated", "format": 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"is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_mig_7series_1_0_c1_ui_clk", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "AWID": [ { "physical_name": "m_axi_awid" } ], + "AWADDR": [ { "physical_name": "m_axi_awaddr" } ], + "AWLEN": [ { "physical_name": "m_axi_awlen" } ], + "AWSIZE": [ { "physical_name": "m_axi_awsize" } ], + "AWBURST": [ { "physical_name": "m_axi_awburst" } ], + "AWLOCK": [ { "physical_name": "m_axi_awlock" } ], + "AWCACHE": [ { "physical_name": "m_axi_awcache" } ], + "AWPROT": [ { "physical_name": "m_axi_awprot" } ], + "AWREGION": [ { "physical_name": "m_axi_awregion" } ], + "AWQOS": [ { "physical_name": "m_axi_awqos" } ], + "AWVALID": [ { "physical_name": "m_axi_awvalid" } ], + "AWREADY": [ { "physical_name": "m_axi_awready" } ], + "WDATA": [ { "physical_name": "m_axi_wdata" } ], + "WSTRB": [ { "physical_name": "m_axi_wstrb" } ], + "WLAST": [ { "physical_name": "m_axi_wlast" } ], + "WVALID": [ { "physical_name": "m_axi_wvalid" } ], + "WREADY": [ { "physical_name": "m_axi_wready" } ], + "BID": [ { "physical_name": "m_axi_bid" } ], + "BRESP": [ { "physical_name": "m_axi_bresp" } ], + "BVALID": [ { "physical_name": "m_axi_bvalid" } ], + "BREADY": [ { "physical_name": "m_axi_bready" } ], + "ARID": [ { "physical_name": "m_axi_arid" } ], + "ARADDR": [ { "physical_name": "m_axi_araddr" } ], + "ARLEN": [ { "physical_name": "m_axi_arlen" } ], + "ARSIZE": [ { "physical_name": "m_axi_arsize" } ], + "ARBURST": [ { "physical_name": "m_axi_arburst" } ], + "ARLOCK": [ { "physical_name": "m_axi_arlock" } ], + "ARCACHE": [ { "physical_name": "m_axi_arcache" } ], + "ARPROT": [ { "physical_name": "m_axi_arprot" } ], + "ARREGION": [ { "physical_name": "m_axi_arregion" } ], + "ARQOS": [ { "physical_name": "m_axi_arqos" } ], + "ARVALID": [ { "physical_name": "m_axi_arvalid" } ], + "ARREADY": [ { "physical_name": "m_axi_arready" } ], + "RID": [ { "physical_name": "m_axi_rid" } ], + "RDATA": [ { "physical_name": "m_axi_rdata" } ], + "RRESP": [ { "physical_name": "m_axi_rresp" } ], + "RLAST": [ { "physical_name": "m_axi_rlast" } ], + "RVALID": [ { "physical_name": "m_axi_rvalid" } ], + "RREADY": [ { "physical_name": "m_axi_rready" } ] + } + }, + "SI_CLK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "FREQ_HZ": [ { "value": "62500000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "S_AXI_ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "s_axi_aclk" } ] + } + }, + "MI_CLK": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "FREQ_HZ": [ { "value": "133333333", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_mig_7series_1_0_c1_ui_clk", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "M_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "M_AXI_ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "m_axi_aclk" } ] + } + }, + "SI_RST": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], + "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "s_axi_aresetn" } ] + } + }, + "MI_RST": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ], + "TYPE": [ { "value": "INTERCONNECT", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "m_axi_aresetn" } ] + } + } + } + } + } +} \ No newline at end of file diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci index 14b3595..ab3665f 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci @@ -8,8 +8,8 @@ "gen_directory": "../../../build/xdma_ddr.gen/sources_1/ip/Top_axi_bram_ctrl_0_0", "parameters": { "component_parameters": { - "DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], - "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ID_WIDTH": [ { "value": "4", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], "PROTOCOL": [ { "value": "AXI4", "resolve_type": "user", "usage": "all" } ], "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "SINGLE_PORT_BRAM": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -19,17 +19,17 @@ "ECC_ONOFF_RESET_VALUE": [ { "value": "0", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], "Component_Name": [ { "value": "Top_axi_bram_ctrl_0_0", "resolve_type": "user", "usage": "all" } ], "BMG_INSTANCE": [ { "value": "EXTERNAL", "value_permission": "bd", "resolve_type": "user", "usage": "all" } ], - "MEM_DEPTH": [ { "value": "2048", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], + "MEM_DEPTH": [ { "value": "1024", "value_src": "propagated", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], "READ_LATENCY": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], "RD_CMD_OPTIMIZATION": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ] }, "model_parameters": { "C_BRAM_INST_MODE": [ { "value": "EXTERNAL", "resolve_type": "generated", "usage": "all" } ], - "C_MEMORY_DEPTH": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_BRAM_ADDR_WIDTH": [ { "value": "11", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_MEMORY_DEPTH": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_BRAM_ADDR_WIDTH": [ { "value": "10", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_S_AXI_ADDR_WIDTH": [ { "value": "13", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_S_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_S_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_S_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_S_AXI_PROTOCOL": [ { "value": "AXI4", "resolve_type": "generated", "usage": "all" } ], "C_S_AXI_SUPPORTS_NARROW_BURST": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_SINGLE_PORT_BRAM": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -54,7 +54,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "E" } ], + "TEMPERATURE_GRADE": [ { "value": "I" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, @@ -73,6 +73,7 @@ "ports": { "s_axi_aclk": [ { "direction": "in" } ], "s_axi_aresetn": [ { "direction": "in" } ], + "s_axi_awid": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], "s_axi_awaddr": [ { "direction": "in", "size_left": "12", "size_right": "0", "driver_value": "0" } ], "s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ], "s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ], @@ -82,14 +83,16 @@ "s_axi_awprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ], "s_axi_awvalid": [ { "direction": "in", "driver_value": "0" } ], "s_axi_awready": [ { "direction": "out" } ], - "s_axi_wdata": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ], - "s_axi_wstrb": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], + "s_axi_wdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ], + "s_axi_wstrb": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ], "s_axi_wlast": [ { "direction": "in", "driver_value": "0" } ], "s_axi_wvalid": [ { "direction": "in", "driver_value": "0" } ], "s_axi_wready": [ { "direction": "out" } ], + "s_axi_bid": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], "s_axi_bvalid": [ { "direction": "out" } ], "s_axi_bready": [ { "direction": "in", "driver_value": "0" } ], + "s_axi_arid": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], "s_axi_araddr": [ { "direction": "in", "size_left": "12", "size_right": "0", "driver_value": "0" } ], "s_axi_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ], "s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ], @@ -99,7 +102,8 @@ "s_axi_arprot": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0" } ], "s_axi_arvalid": [ { "direction": "in", "driver_value": "0" } ], "s_axi_arready": [ { "direction": "out" } ], - "s_axi_rdata": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "s_axi_rid": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], + "s_axi_rdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ], "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], "s_axi_rlast": [ { "direction": "out", "driver_value": "0" } ], "s_axi_rvalid": [ { "direction": "out" } ], @@ -107,10 +111,10 @@ "bram_rst_a": [ { "direction": "out" } ], "bram_clk_a": [ { "direction": "out" } ], "bram_en_a": [ { "direction": "out" } ], - "bram_we_a": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], + "bram_we_a": [ { "direction": "out", "size_left": "7", "size_right": "0" } ], "bram_addr_a": [ { "direction": "out", "size_left": "12", "size_right": "0" } ], - "bram_wrdata_a": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], - "bram_rddata_a": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ] + "bram_wrdata_a": [ { "direction": "out", "size_left": "63", "size_right": "0" } ], + "bram_rddata_a": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ] }, "interfaces": { "S_AXI": { @@ -119,10 +123,10 @@ "mode": "slave", "memory_map_ref": "S_AXI", "parameters": { - "DATA_WIDTH": [ { "value": "32", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_HZ": [ { "value": "62500000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "ID_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "4", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "13", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -142,9 +146,9 @@ "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_OUTSTANDING": [ { "value": "32", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "32", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -155,6 +159,7 @@ "ARADDR": [ { "physical_name": "s_axi_araddr" } ], "ARBURST": [ { "physical_name": "s_axi_arburst" } ], "ARCACHE": [ { "physical_name": "s_axi_arcache" } ], + "ARID": [ { "physical_name": "s_axi_arid" } ], "ARLEN": [ { "physical_name": "s_axi_arlen" } ], "ARLOCK": [ { "physical_name": "s_axi_arlock" } ], "ARPROT": [ { "physical_name": "s_axi_arprot" } ], @@ -164,16 +169,19 @@ "AWADDR": [ { "physical_name": "s_axi_awaddr" } ], "AWBURST": [ { "physical_name": "s_axi_awburst" } ], "AWCACHE": [ { "physical_name": "s_axi_awcache" } ], + "AWID": [ { "physical_name": "s_axi_awid" } ], "AWLEN": [ { "physical_name": "s_axi_awlen" } ], "AWLOCK": [ { "physical_name": "s_axi_awlock" } ], "AWPROT": [ { "physical_name": "s_axi_awprot" } ], "AWREADY": [ { "physical_name": "s_axi_awready" } ], "AWSIZE": [ { "physical_name": "s_axi_awsize" } ], "AWVALID": [ { "physical_name": "s_axi_awvalid" } ], + "BID": [ { "physical_name": "s_axi_bid" } ], "BREADY": [ { "physical_name": "s_axi_bready" } ], "BRESP": [ { "physical_name": "s_axi_bresp" } ], "BVALID": [ { "physical_name": "s_axi_bvalid" } ], "RDATA": [ { "physical_name": "s_axi_rdata" } ], + "RID": [ { "physical_name": "s_axi_rid" } ], "RLAST": [ { "physical_name": "s_axi_rlast" } ], "RREADY": [ { "physical_name": "s_axi_rready" } ], "RRESP": [ { "physical_name": "s_axi_rresp" } ], @@ -192,7 +200,7 @@ "parameters": { "MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], "MEM_SIZE": [ { "value": "8192", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "MEM_WIDTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "MEM_WIDTH": [ { "value": "64", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "MEM_ECC": [ { "value": "NONE", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "READ_LATENCY": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ] @@ -229,7 +237,7 @@ "FREQ_HZ": [ { "value": "62500000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, @@ -244,7 +252,7 @@ "description": "Memory Map for S_AXI", "address_blocks": { "Mem0": { - "base_address": "4294967296", + "base_address": "0x0000000100000000", "range": "4096", "display_name": "Mem0", "description": "Register Block", diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci index f5f615f..7aa56bd 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci @@ -14,7 +14,7 @@ "AXI_Slave_Type": [ { "value": "Memory_Slave", "resolve_type": "user", "usage": "all" } ], "Use_AXI_ID": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], "AXI_ID_Width": [ { "value": "4", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], - "Memory_Type": [ { "value": "Single_Port_RAM", "resolve_type": "user", "usage": "all" } ], + "Memory_Type": [ { "value": "Single_Port_RAM", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "PRIM_type_to_Implement": [ { "value": "BRAM", "resolve_type": "user", "usage": "all" } ], "Enable_32bit_Address": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], "ecctype": [ { "value": "No_ECC", "resolve_type": "user", "enabled": false, "usage": "all" } ], @@ -33,13 +33,13 @@ "Algorithm": [ { "value": "Minimum_Area", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Primitive": [ { "value": "8kx2", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Assume_Synchronous_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], - "Write_Width_A": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ], - "Write_Depth_A": [ { "value": "2048", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ], - "Read_Width_A": [ { "value": "32", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ], + "Write_Width_A": [ { "value": "64", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Write_Depth_A": [ { "value": "1024", "value_src": "propagated", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Read_Width_A": [ { "value": "64", "value_src": "propagated", "resolve_type": "user", "usage": "all" } ], "Operating_Mode_A": [ { "value": "WRITE_FIRST", "resolve_type": "user", "usage": "all" } ], "Enable_A": [ { "value": "Use_ENA_Pin", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "Write_Width_B": [ { "value": "32", "resolve_type": "user", "enabled": false, "usage": "all" } ], - "Read_Width_B": [ { "value": "32", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Write_Width_B": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "Read_Width_B": [ { "value": "64", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Operating_Mode_B": [ { "value": "WRITE_FIRST", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Enable_B": [ { "value": "Always_Enabled", "resolve_type": "user", "enabled": false, "usage": "all" } ], "Register_PortA_Output_of_Memory_Primitives": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], @@ -109,12 +109,12 @@ "C_HAS_ENA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_HAS_REGCEA": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_USE_BYTE_WEA": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_WEA_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_WEA_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_WRITE_MODE_A": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ], - "C_WRITE_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_READ_WIDTH_A": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_WRITE_DEPTH_A": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_READ_DEPTH_A": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_WRITE_WIDTH_A": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_READ_WIDTH_A": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_WRITE_DEPTH_A": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_READ_DEPTH_A": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_ADDRA_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_HAS_RSTB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_RST_PRIORITY_B": [ { "value": "CE", "resolve_type": "generated", "usage": "all" } ], @@ -123,12 +123,12 @@ "C_HAS_ENB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_HAS_REGCEB": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_USE_BYTE_WEB": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_WEB_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_WEB_WIDTH": [ { "value": "8", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_WRITE_MODE_B": [ { "value": "WRITE_FIRST", "resolve_type": "generated", "usage": "all" } ], - "C_WRITE_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_READ_WIDTH_B": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_WRITE_DEPTH_B": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_READ_DEPTH_B": [ { "value": "2048", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_WRITE_WIDTH_B": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_READ_WIDTH_B": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_WRITE_DEPTH_B": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_READ_DEPTH_B": [ { "value": "1024", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_ADDRB_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_HAS_MEM_OUTPUT_REGS_A": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_HAS_MEM_OUTPUT_REGS_B": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -156,7 +156,7 @@ "C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_COUNT_36K_BRAM": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ], "C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ], - "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 5.3746 mW", "resolve_type": "generated", "usage": "all" } ] + "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 5.633405 mW", "resolve_type": "generated", "usage": "all" } ] }, "project_parameters": { "ARCHITECTURE": [ { "value": "kintex7" } ], @@ -169,7 +169,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "E" } ], + "TEMPERATURE_GRADE": [ { "value": "I" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, @@ -189,10 +189,10 @@ "clka": [ { "direction": "in", "driver_value": "0" } ], "rsta": [ { "direction": "in", "driver_value": "0" } ], "ena": [ { "direction": "in", "driver_value": "0" } ], - "wea": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], + "wea": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0" } ], "addra": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ], - "dina": [ { "direction": "in", "size_left": "31", "size_right": "0", "driver_value": "0" } ], - "douta": [ { "direction": "out", "size_left": "31", "size_right": "0" } ], + "dina": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0" } ], + "douta": [ { "direction": "out", "size_left": "63", "size_right": "0" } ], "rsta_busy": [ { "direction": "out" } ] }, "interfaces": { @@ -226,7 +226,7 @@ "mode": "slave", "parameters": { "MEM_SIZE": [ { "value": "8192", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "MEM_WIDTH": [ { "value": "32", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "MEM_WIDTH": [ { "value": "64", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "MEM_ECC": [ { "value": "NONE", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "MASTER_TYPE": [ { "value": "BRAM_CTRL", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], @@ -247,7 +247,7 @@ "S_1": { "address_blocks": { "Mem0": { - "base_address": "4294967296", + "base_address": "0x0000000100000000", "range": "4096", "usage": "memory", "access": "read-write", diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_jtag_axi_0_0/Top_jtag_axi_0_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_jtag_axi_0_0/Top_jtag_axi_0_0.xci new file mode 100644 index 0000000..ad99471 --- /dev/null +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_jtag_axi_0_0/Top_jtag_axi_0_0.xci @@ -0,0 +1,180 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "Top_jtag_axi_0_0", + "cell_name": "jtag_axi_0", + "component_reference": "xilinx.com:ip:jtag_axi:1.2", + "ip_revision": "16", + "gen_directory": "../../../build/xdma_ddr.gen/sources_1/ip/Top_jtag_axi_0_0", + "parameters": { + "component_parameters": { + "RD_TXN_QUEUE_LENGTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "WR_TXN_QUEUE_LENGTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M_HAS_BURST": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "PROTOCOL": [ { "value": "2", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M_AXI_DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M_AXI_ADDR_WIDTH": [ { "value": "64", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "Component_Name": [ { "value": "Top_jtag_axi_0_0", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "RD_TXN_QUEUE_LENGTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "WR_TXN_QUEUE_LENGTH": [ { "value": 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"is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_mig_7series_1_0_c1_ui_clk", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "ARADDR": [ { "physical_name": "m_axi_araddr" } ], + "ARPROT": [ { "physical_name": "m_axi_arprot" } ], + "ARREADY": [ { "physical_name": "m_axi_arready" } ], + "ARVALID": [ { "physical_name": "m_axi_arvalid" } ], + "AWADDR": [ { "physical_name": "m_axi_awaddr" } ], + "AWPROT": [ { "physical_name": "m_axi_awprot" } ], + "AWREADY": [ { "physical_name": "m_axi_awready" } ], + "AWVALID": [ { "physical_name": "m_axi_awvalid" } ], + "BREADY": [ { "physical_name": "m_axi_bready" } ], + "BRESP": [ { "physical_name": "m_axi_bresp" } ], + "BVALID": [ { "physical_name": "m_axi_bvalid" } ], + "RDATA": [ { "physical_name": "m_axi_rdata" } ], + "RREADY": [ { "physical_name": "m_axi_rready" } ], + "RRESP": [ { "physical_name": "m_axi_rresp" } ], + "RVALID": [ { "physical_name": "m_axi_rvalid" } ], + "WDATA": [ { "physical_name": "m_axi_wdata" } ], + "WREADY": [ { "physical_name": "m_axi_wready" } ], + "WSTRB": [ { "physical_name": "m_axi_wstrb" } ], + "WVALID": [ { "physical_name": "m_axi_wvalid" } ] + } + }, + "signal_reset": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "aresetn" } ] + } + }, + "signal_clock": { + "vlnv": "xilinx.com:signal:clock:1.0", + "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", + "mode": "slave", + "parameters": { + "ASSOCIATED_BUSIF": [ { "value": "M_AXI", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "ASSOCIATED_RESET": [ { "value": "aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "FREQ_HZ": [ { "value": "133333333", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_mig_7series_1_0_c1_ui_clk", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "aclk" } ] + } + } + }, + "address_spaces": { + "Data": { + "range": "16777216T", + "display_name": "Data", + "width": "64" + } + } + } + } +} \ No newline at end of file diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci index 392e499..789a6f7 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci @@ -8,9 +8,9 @@ "gen_directory": "../../../build/xdma_ddr.gen/sources_1/ip/Top_mig_7series_1_0", "parameters": { "component_parameters": { - "XML_INPUT_FILE": [ { "value": "mig_b.prj", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "XML_INPUT_FILE": [ { "value": "mig_a.prj", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "RESET_BOARD_INTERFACE": [ { "value": "Custom", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "MIG_DONT_TOUCH_PARAM": [ { "value": "Custom", "value_src": "user_prop", "resolve_type": "user", "usage": "all" } ], + "MIG_DONT_TOUCH_PARAM": [ { "value": "Custom", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "BOARD_MIG_PARAM": [ { "value": "Custom", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "Component_Name": [ { "value": "Top_mig_7series_1_0", "resolve_type": "user", "usage": "all" } ] }, @@ -231,7 +231,7 @@ "C0_C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C0_C_S_AXI_CTRL_MEM_SIZE": [ { "value": "1048576", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C0_C_S_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C0_C_S_AXI_DATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C0_C_S_AXI_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C0_C_S_AXI_ADDR_WIDTH": [ { "value": "31", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C0_C_S_AXI_MEM_SIZE": [ { "value": "2147483648", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C0_QDRIIP_NUM_DEVICES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -358,7 +358,7 @@ "C1_C_S_AXI_CTRL_ADDR_WIDTH": [ { "value": "32", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C1_C_S_AXI_CTRL_MEM_SIZE": [ { "value": "1048576", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C1_C_S_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C1_C_S_AXI_DATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C1_C_S_AXI_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C1_C_S_AXI_ADDR_WIDTH": [ { "value": "31", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C1_C_S_AXI_MEM_SIZE": [ { "value": "2147483648", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C1_QDRIIP_NUM_DEVICES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], @@ -1174,7 +1174,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "E" } ], + "TEMPERATURE_GRADE": [ { "value": "I" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, @@ -1235,8 +1235,8 @@ "c0_s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], "c0_s_axi_awvalid": [ { "direction": "in" } ], "c0_s_axi_awready": [ { "direction": "out" } ], - "c0_s_axi_wdata": [ { "direction": "in", "size_left": "511", "size_right": "0" } ], - "c0_s_axi_wstrb": [ { "direction": "in", "size_left": "63", "size_right": "0" } ], + "c0_s_axi_wdata": [ { "direction": "in", "size_left": "63", "size_right": "0" } ], + "c0_s_axi_wstrb": [ { "direction": "in", "size_left": "7", "size_right": "0" } ], "c0_s_axi_wlast": [ { "direction": "in" } ], "c0_s_axi_wvalid": [ { "direction": "in" } ], "c0_s_axi_wready": [ { "direction": "out" } ], @@ -1257,7 +1257,7 @@ "c0_s_axi_arready": [ { "direction": "out" } ], "c0_s_axi_rready": [ { "direction": "in" } ], "c0_s_axi_rid": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], - "c0_s_axi_rdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ], + "c0_s_axi_rdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ], "c0_s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], "c0_s_axi_rlast": [ { "direction": "out" } ], "c0_s_axi_rvalid": [ { "direction": "out" } ], @@ -1310,8 +1310,8 @@ "c1_s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0" } ], "c1_s_axi_awvalid": [ { "direction": "in" } ], "c1_s_axi_awready": [ { "direction": "out" } ], - "c1_s_axi_wdata": [ { "direction": "in", "size_left": "511", "size_right": "0" } ], - "c1_s_axi_wstrb": [ { "direction": "in", "size_left": "63", "size_right": "0" } ], + "c1_s_axi_wdata": [ { "direction": "in", "size_left": "63", "size_right": "0" } ], + "c1_s_axi_wstrb": [ { "direction": "in", "size_left": "7", "size_right": "0" } ], "c1_s_axi_wlast": [ { "direction": "in" } ], "c1_s_axi_wvalid": [ { "direction": "in" } ], "c1_s_axi_wready": [ { "direction": "out" } ], @@ -1332,7 +1332,7 @@ "c1_s_axi_arready": [ { "direction": "out" } ], "c1_s_axi_rready": [ { "direction": "in" } ], "c1_s_axi_rid": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], - "c1_s_axi_rdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ], + "c1_s_axi_rdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ], "c1_s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], "c1_s_axi_rlast": [ { "direction": "out" } ], "c1_s_axi_rvalid": [ { "direction": "out" } ], @@ -1583,7 +1583,7 @@ "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], @@ -1592,11 +1592,11 @@ "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "HAS_WSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "NUM_READ_OUTSTANDING": [ { "value": "32", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "PHASE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "Top_mig_7series_1_0_c0_ui_clk", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], @@ -1631,7 +1631,7 @@ "memory_map_ref": "c0_memmap", "parameters": { "FREQ_HZ": [ { "value": "133333333", "value_permission": "bd", "resolve_type": "dependent", "format": "float", "usage": "all" } ], - "DATA_WIDTH": [ { "value": "512", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], "ID_WIDTH": [ { "value": "4", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "31", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], @@ -1944,7 +1944,7 @@ "WUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "RUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "HAS_LOCK": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "HAS_PROT": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], @@ -1953,11 +1953,11 @@ "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "HAS_WSTRB": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "HAS_BRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "HAS_RRESP": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "NUM_READ_OUTSTANDING": [ { "value": "32", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], - "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "1", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "PHASE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_static_object": false } ], "CLK_DOMAIN": [ { "value": "Top_mig_7series_1_0_c1_ui_clk", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], @@ -1992,7 +1992,7 @@ "memory_map_ref": "c1_memmap", "parameters": { "FREQ_HZ": [ { "value": "133333333", "value_permission": "bd", "resolve_type": "dependent", "format": "float", "usage": "all" } ], - "DATA_WIDTH": [ { "value": "512", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_static_object": false } ], "ID_WIDTH": [ { "value": "4", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "31", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_static_object": false } ], @@ -2147,7 +2147,7 @@ "c0_s_axi_ctrl_memmap": { "address_blocks": { "c0_s_axi_ctrl_memaddr": { - "base_address": "4295229440", + "base_address": "0x0000000200000000", "range": "1048576", "usage": "register", "access": "read-write" @@ -2157,7 +2157,7 @@ "c0_memmap": { "address_blocks": { "c0_memaddr": { - "base_address": "0", + "base_address": "0x0000000000000000", "range": "2147483648", "usage": "memory", "access": "read-write" @@ -2167,7 +2167,7 @@ "c1_s_axi_ctrl_memmap": { "address_blocks": { "c1_s_axi_ctrl_memaddr": { - "base_address": "4295491584", + "base_address": "0x0000000200100000", "range": "1048576", "usage": "register", "access": "read-write" @@ -2177,7 +2177,7 @@ "c1_memmap": { "address_blocks": { "c1_memaddr": { - "base_address": "2147483648", + "base_address": "0x0000000080000000", "range": "2147483648", "usage": "memory", "access": "read-write" diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/mig_a.prj b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/mig_a.prj index 796d3d5..a65f67c 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/mig_a.prj +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/mig_a.prj @@ -1,5 +1,5 @@  - + @@ -11,7 +11,7 @@ 1 - OFF + Disable 1024 @@ -188,7 +188,7 @@ - + @@ -205,7 +205,7 @@ No Slow Exit Enable - RZQ/6 + RZQ/7 Disable Enable RZQ/4 @@ -222,11 +222,193 @@ RD_PRI_REG 31 - 512 + 64 4 0 + + DDR3_SDRAM/Components/MT41K256M8XX-125 + 1875 + 1.8V + 4:1 + 200 + 0 + 1066 + 1.000 + 1 + 1 + 1 + 1 + 72 + 1 + 0 + Enabled + Normal + 4 + FALSE + + 15 + 10 + 3 + 1.5V + 2147483648 + BANK_ROW_COLUMN + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 8 - Fixed + Sequential + 7 + Normal + No + Slow Exit + Enable + RZQ/7 + Disable + Enable + RZQ/4 + 0 + Disabled + Enabled + Output Buffer Enabled + Full Array + 6 + Enabled + Normal + Dynamic ODT off + AXI + + RD_PRI_REG + 31 + 64 + 4 + 0 + + + diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci index 091b26a..dd8e504 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci @@ -40,7 +40,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "E" } ], + "TEMPERATURE_GRADE": [ { "value": "I" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_0_0/Top_util_vector_logic_0_0.xci similarity index 87% rename from nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci rename to nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_0_0/Top_util_vector_logic_0_0.xci index 30f84d5..68f8bb3 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_0_0/Top_util_vector_logic_0_0.xci @@ -1,14 +1,14 @@ { "schema": "xilinx.com:schema:json_instance:1.0", "ip_inst": { - "xci_name": "Top_util_vector_logic_1_4", - "cell_name": "util_vector_logic_2", + "xci_name": "Top_util_vector_logic_0_0", + "cell_name": "util_vector_logic_0", "component_reference": "xilinx.com:ip:util_vector_logic:2.0", "ip_revision": "2", - "gen_directory": "../../../build/xdma_ddr.gen/sources_1/ip/Top_util_vector_logic_1_4", + "gen_directory": "../../../build/xdma_ddr.gen/sources_1/ip/Top_util_vector_logic_0_0", "parameters": { "component_parameters": { - "Component_Name": [ { "value": "Top_util_vector_logic_1_4", "resolve_type": "user", "usage": "all" } ], + "Component_Name": [ { "value": "Top_util_vector_logic_0_0", "resolve_type": "user", "usage": "all" } ], "C_SIZE": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_OPERATION": [ { "value": "not", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "LOGO_FILE": [ { "value": "data/sym_notgate.png", "resolve_type": "user", "enabled": false, "usage": "all" } ] @@ -28,7 +28,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "E" } ], + "TEMPERATURE_GRADE": [ { "value": "I" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, @@ -36,7 +36,7 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "2" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/xdma_ddr.gen/sources_1/ip/Top_util_vector_logic_1_4" } ], + "OUTPUTDIR": [ { "value": "../../../build/xdma_ddr.gen/sources_1/ip/Top_util_vector_logic_0_0" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "../../ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_0_1/Top_util_vector_logic_0_1.xci similarity index 88% rename from nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci rename to nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_0_1/Top_util_vector_logic_0_1.xci index 54e0354..c71aa0c 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_0_1/Top_util_vector_logic_0_1.xci @@ -1,14 +1,14 @@ { "schema": "xilinx.com:schema:json_instance:1.0", "ip_inst": { - "xci_name": "Top_util_vector_logic_1_3", + "xci_name": "Top_util_vector_logic_0_1", "cell_name": "util_vector_logic_1", "component_reference": "xilinx.com:ip:util_vector_logic:2.0", "ip_revision": "2", - "gen_directory": "../../../build/xdma_ddr.gen/sources_1/ip/Top_util_vector_logic_1_3", + "gen_directory": "../../../build/xdma_ddr.gen/sources_1/ip/Top_util_vector_logic_0_1", "parameters": { "component_parameters": { - "Component_Name": [ { "value": "Top_util_vector_logic_1_3", "resolve_type": "user", "usage": "all" } ], + "Component_Name": [ { "value": "Top_util_vector_logic_0_1", "resolve_type": "user", "usage": "all" } ], "C_SIZE": [ { "value": "8", "resolve_type": "user", "format": "long", "usage": "all" } ], "C_OPERATION": [ { "value": "not", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "LOGO_FILE": [ { "value": "data/sym_notgate.png", "resolve_type": "user", "enabled": false, "usage": "all" } ] @@ -28,7 +28,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "E" } ], + "TEMPERATURE_GRADE": [ { "value": "I" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, @@ -36,7 +36,7 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "2" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/xdma_ddr.gen/sources_1/ip/Top_util_vector_logic_1_3" } ], + "OUTPUTDIR": [ { "value": "../../../build/xdma_ddr.gen/sources_1/ip/Top_util_vector_logic_0_1" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "../../ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci index 51f86bf..3558fe0 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci @@ -10,13 +10,13 @@ "component_parameters": { "ADDR_RANGES": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "NUM_SI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "NUM_MI": [ { "value": "5", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "NUM_MI": [ { "value": "3", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "ADDR_WIDTH": [ { "value": "64", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "STRATEGY": [ { "value": "0", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], - "DATA_WIDTH": [ { "value": "512", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "64", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "CONNECTIVITY_MODE": [ { "value": "SAMD", "resolve_type": "user", "usage": "all" } ], - "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "ID_WIDTH": [ { "value": "4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "AWUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "ARUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "WUSER_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -71,7 +71,7 @@ "M02_S13_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M02_S14_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M02_S15_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M03_S00_READ_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M03_S00_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M03_S01_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M03_S02_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M03_S03_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -87,7 +87,7 @@ "M03_S13_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M03_S14_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M03_S15_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M04_S00_READ_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M04_S00_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M04_S01_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M04_S02_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M04_S03_READ_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -327,7 +327,7 @@ "M02_S13_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M02_S14_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M02_S15_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M03_S00_WRITE_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M03_S00_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M03_S01_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M03_S02_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M03_S03_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -343,7 +343,7 @@ "M03_S13_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M03_S14_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M03_S15_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M04_S00_WRITE_CONNECTIVITY": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M04_S00_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M04_S01_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M04_S02_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M04_S03_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -535,22 +535,22 @@ "M15_S13_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M15_S14_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M15_S15_WRITE_CONNECTIVITY": [ { "value": "1", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S00_THREAD_ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S01_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S02_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S03_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S04_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S05_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S06_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S07_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S08_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S09_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S10_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S11_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S12_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S13_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S14_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], - "S15_THREAD_ID_WIDTH": [ { "value": "0", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S00_THREAD_ID_WIDTH": [ { "value": "4", "value_src": "propagated", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S01_THREAD_ID_WIDTH": [ { "value": "4", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S02_THREAD_ID_WIDTH": [ { "value": "4", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S03_THREAD_ID_WIDTH": [ { "value": "4", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S04_THREAD_ID_WIDTH": [ { "value": "4", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S05_THREAD_ID_WIDTH": [ { "value": "4", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S06_THREAD_ID_WIDTH": [ { "value": "4", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S07_THREAD_ID_WIDTH": [ { "value": "4", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S08_THREAD_ID_WIDTH": [ { "value": "4", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S09_THREAD_ID_WIDTH": [ { "value": "4", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S10_THREAD_ID_WIDTH": [ { "value": "4", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S11_THREAD_ID_WIDTH": [ { "value": "4", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S12_THREAD_ID_WIDTH": [ { "value": "4", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S13_THREAD_ID_WIDTH": [ { "value": "4", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S14_THREAD_ID_WIDTH": [ { "value": "4", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], + "S15_THREAD_ID_WIDTH": [ { "value": "4", "value_permission": "none", "resolve_type": "user", "format": "long", "usage": "all" } ], "S00_WRITE_ACCEPTANCE": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "S01_WRITE_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "S02_WRITE_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -583,11 +583,11 @@ "S13_READ_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "S14_READ_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "S15_READ_ACCEPTANCE": [ { "value": "2", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M00_WRITE_ISSUING": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_WRITE_ISSUING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M01_WRITE_ISSUING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M02_WRITE_ISSUING": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M03_WRITE_ISSUING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M04_WRITE_ISSUING": [ { "value": "16", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M03_WRITE_ISSUING": [ { "value": "4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M04_WRITE_ISSUING": [ { "value": "4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M05_WRITE_ISSUING": [ { "value": "4", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M06_WRITE_ISSUING": [ { "value": "4", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M07_WRITE_ISSUING": [ { "value": "4", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -599,11 +599,11 @@ "M13_WRITE_ISSUING": [ { "value": "4", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M14_WRITE_ISSUING": [ { "value": "4", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M15_WRITE_ISSUING": [ { "value": "4", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M00_READ_ISSUING": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_READ_ISSUING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M01_READ_ISSUING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M02_READ_ISSUING": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M03_READ_ISSUING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M04_READ_ISSUING": [ { "value": "32", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M03_READ_ISSUING": [ { "value": "4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M04_READ_ISSUING": [ { "value": "4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M05_READ_ISSUING": [ { "value": "4", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M06_READ_ISSUING": [ { "value": "4", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M07_READ_ISSUING": [ { "value": "4", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -680,22 +680,22 @@ "M14_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "M15_SECURE": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], "S00_BASE_ID": [ { "value": "0x00000000", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "S01_BASE_ID": [ { "value": "0x00000001", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "S02_BASE_ID": [ { "value": "0x00000002", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "S03_BASE_ID": [ { "value": "0x00000003", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "S04_BASE_ID": [ { "value": "0x00000004", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "S05_BASE_ID": [ { "value": "0x00000005", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "S06_BASE_ID": [ { "value": "0x00000006", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "S07_BASE_ID": [ { "value": "0x00000007", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "S08_BASE_ID": [ { "value": "0x00000008", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "S09_BASE_ID": [ { "value": "0x00000009", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "S10_BASE_ID": [ { "value": "0x0000000a", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "S11_BASE_ID": [ { "value": "0x0000000b", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "S12_BASE_ID": [ { "value": "0x0000000c", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "S13_BASE_ID": [ { "value": "0x0000000d", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "S14_BASE_ID": [ { "value": "0x0000000e", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "S15_BASE_ID": [ { "value": "0x0000000f", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "M00_A00_BASE_ADDR": [ { "value": "0x0000000100000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "S01_BASE_ID": [ { "value": "0x00000010", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "S02_BASE_ID": [ { "value": "0x00000020", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "S03_BASE_ID": [ { "value": "0x00000030", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "S04_BASE_ID": [ { "value": "0x00000040", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "S05_BASE_ID": [ { "value": "0x00000050", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "S06_BASE_ID": [ { "value": "0x00000060", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "S07_BASE_ID": [ { "value": "0x00000070", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "S08_BASE_ID": [ { "value": "0x00000080", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "S09_BASE_ID": [ { "value": "0x00000090", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "S10_BASE_ID": [ { "value": "0x000000a0", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "S11_BASE_ID": [ { "value": "0x000000b0", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "S12_BASE_ID": [ { "value": "0x000000c0", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "S13_BASE_ID": [ { "value": "0x000000d0", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "S14_BASE_ID": [ { "value": "0x000000e0", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "S15_BASE_ID": [ { "value": "0x000000f0", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M00_A00_BASE_ADDR": [ { "value": "0x0000000000000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M00_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M00_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M00_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], @@ -711,7 +711,7 @@ "M00_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M00_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M00_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "M01_A00_BASE_ADDR": [ { "value": "0x0000000080000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M01_A00_BASE_ADDR": [ { "value": "0x0000000100000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M01_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M01_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M01_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], @@ -727,7 +727,7 @@ "M01_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M01_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M01_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "M02_A00_BASE_ADDR": [ { "value": "0x0000000100100000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M02_A00_BASE_ADDR": [ { "value": "0x00000000C0000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M02_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M02_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M02_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], @@ -743,7 +743,7 @@ "M02_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M02_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M02_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "M03_A00_BASE_ADDR": [ { "value": "0x0000000000000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M03_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M03_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M03_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M03_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], @@ -759,7 +759,7 @@ "M03_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M03_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M03_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "M04_A00_BASE_ADDR": [ { "value": "0x0000000200000000", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], + "M04_A00_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M04_A01_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M04_A02_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M04_A03_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], @@ -951,7 +951,7 @@ "M15_A13_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M15_A14_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], "M15_A15_BASE_ADDR": [ { "value": "0xffffffffffffffff", "value_permission": "bd_and_user", "resolve_type": "user", "format": "bitString", "usage": "all" } ], - "M00_A00_ADDR_WIDTH": [ { "value": "20", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M00_A00_ADDR_WIDTH": [ { "value": "31", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M00_A01_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M00_A02_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M00_A03_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -983,7 +983,7 @@ "M01_A13_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M01_A14_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M01_A15_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M02_A00_ADDR_WIDTH": [ { "value": "20", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M02_A00_ADDR_WIDTH": [ { "value": "13", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M02_A01_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M02_A02_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M02_A03_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -999,7 +999,7 @@ "M02_A13_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M02_A14_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M02_A15_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M03_A00_ADDR_WIDTH": [ { "value": "31", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M03_A00_ADDR_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M03_A01_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M03_A02_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M03_A03_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -1015,7 +1015,7 @@ "M03_A13_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M03_A14_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M03_A15_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], - "M04_A00_ADDR_WIDTH": [ { "value": "13", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], + "M04_A00_ADDR_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M04_A01_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M04_A02_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], "M04_A03_ADDR_WIDTH": [ { "value": "0", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -1212,32 +1212,32 @@ "model_parameters": { "C_FAMILY": [ { "value": "kintex7", "resolve_type": "generated", "usage": "all" } ], "C_NUM_SLAVE_SLOTS": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_NUM_MASTER_SLOTS": [ { "value": "5", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_AXI_ID_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_NUM_MASTER_SLOTS": [ { "value": "3", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_ID_WIDTH": [ { "value": "4", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_ADDR_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_AXI_DATA_WIDTH": [ { "value": "512", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "C_AXI_DATA_WIDTH": [ { "value": "64", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_PROTOCOL": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_NUM_ADDR_RANGES": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_M_AXI_BASE_ADDR": [ { "value": "0x00000002000000000000000000000000000000010010000000000000800000000000000100000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], - "C_M_AXI_ADDR_WIDTH": [ { "value": "0x0000000d0000001f000000140000001f00000014", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_M_AXI_BASE_ADDR": [ { "value": "0x00000000c000000000000001000000000000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_M_AXI_ADDR_WIDTH": [ { "value": "0x0000000d0000001f0000001f", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_S_AXI_BASE_ID": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], - "C_S_AXI_THREAD_ID_WIDTH": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_S_AXI_THREAD_ID_WIDTH": [ { "value": "0x00000004", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_AXI_SUPPORTS_USER_SIGNALS": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_AWUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_ARUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_WUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_RUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_AXI_BUSER_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], - "C_M_AXI_WRITE_CONNECTIVITY": [ { "value": "0x0000000100000001000000010000000100000001", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], - "C_M_AXI_READ_CONNECTIVITY": [ { "value": "0x0000000100000001000000010000000100000001", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_M_AXI_WRITE_CONNECTIVITY": [ { "value": "0x000000010000000100000001", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_M_AXI_READ_CONNECTIVITY": [ { "value": "0x000000010000000100000001", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_R_REGISTER": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_S_AXI_SINGLE_THREAD": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_S_AXI_WRITE_ACCEPTANCE": [ { "value": "0x00000010", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_S_AXI_READ_ACCEPTANCE": [ { "value": "0x00000020", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], - "C_M_AXI_WRITE_ISSUING": [ { "value": "0x0000001000000008000000100000000800000010", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], - "C_M_AXI_READ_ISSUING": [ { "value": "0x0000002000000008000000200000000800000020", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_M_AXI_WRITE_ISSUING": [ { "value": "0x000000100000000800000008", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_M_AXI_READ_ISSUING": [ { "value": "0x000000200000000800000008", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_S_AXI_ARB_PRIORITY": [ { "value": "0x00000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], - "C_M_AXI_SECURE": [ { "value": "0x0000000000000000000000000000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], + "C_M_AXI_SECURE": [ { "value": "0x000000000000000000000000", "resolve_type": "generated", "format": "bitString", "usage": "all" } ], "C_CONNECTIVITY_MODE": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ] }, "project_parameters": { @@ -1251,7 +1251,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "E" } ], + "TEMPERATURE_GRADE": [ { "value": "I" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, @@ -1270,6 +1270,7 @@ "ports": { "aclk": [ { "direction": "in" } ], "aresetn": [ { "direction": "in" } ], + "s_axi_awid": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], "s_axi_awaddr": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0x0000000000000000" } ], "s_axi_awlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ], "s_axi_awsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], @@ -1280,14 +1281,16 @@ "s_axi_awqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], "s_axi_awvalid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], "s_axi_awready": [ { "direction": "out", "size_left": "0", "size_right": "0" } ], - "s_axi_wdata": [ { "direction": "in", "size_left": "511", "size_right": "0", "driver_value": "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ], - "s_axi_wstrb": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0xFFFFFFFFFFFFFFFF" } ], + "s_axi_wdata": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0x0000000000000000" } ], + "s_axi_wstrb": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0xFF" } ], "s_axi_wlast": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x1" } ], "s_axi_wvalid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], "s_axi_wready": [ { "direction": "out", "size_left": "0", "size_right": "0" } ], + "s_axi_bid": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], "s_axi_bresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], "s_axi_bvalid": [ { "direction": "out", "size_left": "0", "size_right": "0" } ], "s_axi_bready": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], + "s_axi_arid": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], "s_axi_araddr": [ { "direction": "in", "size_left": "63", "size_right": "0", "driver_value": "0x0000000000000000" } ], "s_axi_arlen": [ { "direction": "in", "size_left": "7", "size_right": "0", "driver_value": "0x00" } ], "s_axi_arsize": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], @@ -1298,46 +1301,51 @@ "s_axi_arqos": [ { "direction": "in", "size_left": "3", "size_right": "0", "driver_value": "0x0" } ], "s_axi_arvalid": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], "s_axi_arready": [ { "direction": "out", "size_left": "0", "size_right": "0" } ], - "s_axi_rdata": [ { "direction": "out", "size_left": "511", "size_right": "0" } ], + "s_axi_rid": [ { "direction": "out", "size_left": "3", "size_right": "0" } ], + "s_axi_rdata": [ { "direction": "out", "size_left": "63", "size_right": "0" } ], "s_axi_rresp": [ { "direction": "out", "size_left": "1", "size_right": "0" } ], "s_axi_rlast": [ { "direction": "out", "size_left": "0", "size_right": "0" } ], "s_axi_rvalid": [ { "direction": "out", "size_left": "0", "size_right": "0" } ], "s_axi_rready": [ { "direction": "in", "size_left": "0", "size_right": "0", "driver_value": "0x0" } ], - "m_axi_awaddr": [ { "direction": "out", "size_left": "319", "size_right": "0" } ], - "m_axi_awlen": [ { "direction": "out", "size_left": "39", "size_right": "0" } ], - "m_axi_awsize": [ { "direction": "out", "size_left": "14", "size_right": "0" } ], - "m_axi_awburst": [ { "direction": "out", "size_left": "9", "size_right": "0" } ], - "m_axi_awlock": [ { "direction": "out", "size_left": "4", "size_right": "0" } ], - "m_axi_awcache": [ { "direction": "out", "size_left": "19", "size_right": "0" } ], - "m_axi_awprot": [ { "direction": "out", "size_left": "14", "size_right": "0" } ], - "m_axi_awregion": [ { "direction": "out", "size_left": "19", "size_right": "0" } ], - "m_axi_awqos": [ { "direction": "out", "size_left": "19", "size_right": "0" } ], - "m_axi_awvalid": [ { "direction": "out", "size_left": "4", "size_right": "0" } ], - "m_axi_awready": [ { "direction": "in", "size_left": "4", "size_right": "0", "driver_value": "0x00" } ], - "m_axi_wdata": [ { "direction": "out", "size_left": "2559", "size_right": "0" } ], - "m_axi_wstrb": [ { "direction": "out", "size_left": "319", "size_right": "0" } ], - "m_axi_wlast": [ { "direction": "out", "size_left": "4", "size_right": "0" } ], - "m_axi_wvalid": [ { "direction": "out", "size_left": "4", "size_right": "0" } ], - "m_axi_wready": [ { "direction": "in", "size_left": "4", "size_right": "0", "driver_value": "0x00" } ], - "m_axi_bresp": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0x000" } ], - "m_axi_bvalid": [ { "direction": "in", "size_left": "4", "size_right": "0", "driver_value": "0x00" } ], - "m_axi_bready": [ { "direction": "out", "size_left": "4", "size_right": "0" } ], - "m_axi_araddr": [ { "direction": "out", "size_left": "319", "size_right": "0" } ], - "m_axi_arlen": [ { "direction": "out", "size_left": "39", "size_right": "0" } ], - "m_axi_arsize": [ { "direction": "out", "size_left": "14", "size_right": "0" } ], - "m_axi_arburst": [ { "direction": "out", "size_left": "9", "size_right": "0" } ], - "m_axi_arlock": [ { "direction": "out", "size_left": "4", "size_right": "0" } ], - "m_axi_arcache": [ { "direction": "out", "size_left": "19", "size_right": "0" } ], - "m_axi_arprot": [ { "direction": "out", "size_left": "14", "size_right": "0" } ], - "m_axi_arregion": [ { "direction": "out", "size_left": "19", "size_right": "0" } ], - "m_axi_arqos": [ { "direction": "out", "size_left": "19", "size_right": "0" } ], - "m_axi_arvalid": [ { "direction": "out", "size_left": "4", "size_right": "0" } ], - "m_axi_arready": [ { "direction": "in", "size_left": "4", "size_right": "0", "driver_value": "0x00" } ], - "m_axi_rdata": [ { "direction": "in", "size_left": "2559", "size_right": "0", "driver_value": "0x0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" } ], - "m_axi_rresp": [ { "direction": "in", "size_left": "9", "size_right": "0", "driver_value": "0x000" } ], - "m_axi_rlast": [ { "direction": "in", "size_left": "4", "size_right": "0", "driver_value": "0x1F" } ], - "m_axi_rvalid": [ { "direction": "in", "size_left": "4", "size_right": "0", "driver_value": "0x00" } ], - "m_axi_rready": [ { "direction": "out", "size_left": "4", "size_right": "0" } ] + "m_axi_awid": [ { "direction": "out", "size_left": "11", "size_right": "0" } ], + "m_axi_awaddr": [ { "direction": "out", "size_left": "191", "size_right": "0" } ], + "m_axi_awlen": [ { "direction": "out", "size_left": "23", "size_right": "0" } ], + "m_axi_awsize": [ { "direction": "out", "size_left": "8", "size_right": "0" } ], + "m_axi_awburst": [ { "direction": "out", "size_left": "5", "size_right": "0" } ], + "m_axi_awlock": [ { "direction": "out", "size_left": "2", "size_right": "0" } ], + "m_axi_awcache": [ { "direction": "out", "size_left": "11", "size_right": "0" } ], + "m_axi_awprot": [ { "direction": "out", "size_left": "8", "size_right": "0" } ], + "m_axi_awregion": [ { "direction": "out", "size_left": "11", "size_right": "0" } ], + "m_axi_awqos": [ { "direction": "out", "size_left": "11", "size_right": "0" } ], + "m_axi_awvalid": [ { "direction": "out", "size_left": "2", "size_right": "0" } ], + "m_axi_awready": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], + "m_axi_wdata": [ { "direction": "out", "size_left": "191", "size_right": "0" } ], + "m_axi_wstrb": [ { "direction": "out", "size_left": "23", "size_right": "0" } ], + "m_axi_wlast": [ { "direction": "out", "size_left": "2", "size_right": "0" } ], + "m_axi_wvalid": [ { "direction": "out", "size_left": "2", "size_right": "0" } ], + "m_axi_wready": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], + "m_axi_bid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ], + "m_axi_bresp": [ { "direction": "in", "size_left": "5", "size_right": "0", "driver_value": "0x00" } ], + "m_axi_bvalid": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], + "m_axi_bready": [ { "direction": "out", "size_left": "2", "size_right": "0" } ], + "m_axi_arid": [ { "direction": "out", "size_left": "11", "size_right": "0" } ], + "m_axi_araddr": [ { "direction": "out", "size_left": "191", "size_right": "0" } ], + "m_axi_arlen": [ { "direction": "out", "size_left": "23", "size_right": "0" } ], + "m_axi_arsize": [ { "direction": "out", "size_left": "8", "size_right": "0" } ], + "m_axi_arburst": [ { "direction": "out", "size_left": "5", "size_right": "0" } ], + "m_axi_arlock": [ { "direction": "out", "size_left": "2", "size_right": "0" } ], + "m_axi_arcache": [ { "direction": "out", "size_left": "11", "size_right": "0" } ], + "m_axi_arprot": [ { "direction": "out", "size_left": "8", "size_right": "0" } ], + "m_axi_arregion": [ { "direction": "out", "size_left": "11", "size_right": "0" } ], + "m_axi_arqos": [ { "direction": "out", "size_left": "11", "size_right": "0" } ], + "m_axi_arvalid": [ { "direction": "out", "size_left": "2", "size_right": "0" } ], + "m_axi_arready": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], + "m_axi_rid": [ { "direction": "in", "size_left": "11", "size_right": "0", "driver_value": "0x000" } ], + "m_axi_rdata": [ { "direction": "in", "size_left": "191", "size_right": "0", "driver_value": "0x000000000000000000000000000000000000000000000000" } ], + "m_axi_rresp": [ { "direction": "in", "size_left": "5", "size_right": "0", "driver_value": "0x00" } ], + "m_axi_rlast": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x7" } ], + "m_axi_rvalid": [ { "direction": "in", "size_left": "2", "size_right": "0", "driver_value": "0x0" } ], + "m_axi_rready": [ { "direction": "out", "size_left": "2", "size_right": "0" } ] }, "interfaces": { "RSTIF": { @@ -1361,7 +1369,7 @@ "FREQ_HZ": [ { "value": "62500000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_BUSIF": [ { "value": "M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_RESET": [ { "value": "ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], @@ -1376,15 +1384,15 @@ "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", "mode": "slave", "parameters": { - "DATA_WIDTH": [ { "value": "512", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "PROTOCOL": [ { "value": "AXI4", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "64", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_HZ": [ { "value": "62500000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "ADDR_WIDTH": [ { "value": "64", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "4", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "64", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "WUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "RUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "auto_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "BUSER_WIDTH": [ { "value": "0", "value_src": "constant_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "HAS_BURST": [ { "value": "1", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -1401,7 +1409,7 @@ "NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -1409,6 +1417,7 @@ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { + "AWID": [ { "physical_name": "s_axi_awid", "physical_left": "3", "physical_right": "0" } ], "AWADDR": [ { "physical_name": "s_axi_awaddr", "physical_left": "63", "physical_right": "0" } ], "AWLEN": [ { "physical_name": "s_axi_awlen", "physical_left": "7", "physical_right": "0" } ], "AWSIZE": [ { "physical_name": "s_axi_awsize", "physical_left": "2", "physical_right": "0" } ], @@ -1419,14 +1428,16 @@ "AWQOS": [ { "physical_name": "s_axi_awqos", "physical_left": "3", "physical_right": "0" } ], "AWVALID": [ { "physical_name": "s_axi_awvalid", "physical_left": "0", "physical_right": "0" } ], "AWREADY": [ { "physical_name": "s_axi_awready", "physical_left": "0", "physical_right": "0" } ], - "WDATA": [ { "physical_name": "s_axi_wdata", "physical_left": "511", "physical_right": "0" } ], - "WSTRB": [ { "physical_name": "s_axi_wstrb", "physical_left": "63", "physical_right": "0" } ], + "WDATA": [ { "physical_name": "s_axi_wdata", "physical_left": "63", "physical_right": "0" } ], + "WSTRB": [ { "physical_name": "s_axi_wstrb", "physical_left": "7", "physical_right": "0" } ], "WLAST": [ { "physical_name": "s_axi_wlast", "physical_left": "0", "physical_right": "0" } ], "WVALID": [ { "physical_name": "s_axi_wvalid", "physical_left": "0", "physical_right": "0" } ], "WREADY": [ { "physical_name": "s_axi_wready", "physical_left": "0", "physical_right": "0" } ], + "BID": [ { "physical_name": "s_axi_bid", "physical_left": "3", "physical_right": "0" } ], "BRESP": [ { "physical_name": "s_axi_bresp", "physical_left": "1", "physical_right": "0" } ], "BVALID": [ { "physical_name": "s_axi_bvalid", "physical_left": "0", "physical_right": "0" } ], "BREADY": [ { "physical_name": "s_axi_bready", "physical_left": "0", "physical_right": "0" } ], + "ARID": [ { "physical_name": "s_axi_arid", "physical_left": "3", "physical_right": "0" } ], "ARADDR": [ { "physical_name": "s_axi_araddr", "physical_left": "63", "physical_right": "0" } ], "ARLEN": [ { "physical_name": "s_axi_arlen", "physical_left": "7", "physical_right": "0" } ], "ARSIZE": [ { "physical_name": "s_axi_arsize", "physical_left": "2", "physical_right": "0" } ], @@ -1437,7 +1448,8 @@ "ARQOS": [ { "physical_name": "s_axi_arqos", "physical_left": "3", "physical_right": "0" } ], "ARVALID": [ { "physical_name": "s_axi_arvalid", "physical_left": "0", "physical_right": "0" } ], "ARREADY": [ { "physical_name": "s_axi_arready", "physical_left": "0", "physical_right": "0" } ], - "RDATA": [ { "physical_name": "s_axi_rdata", "physical_left": "511", "physical_right": "0" } ], + "RID": [ { "physical_name": "s_axi_rid", "physical_left": "3", "physical_right": "0" } ], + "RDATA": [ { "physical_name": "s_axi_rdata", "physical_left": "63", "physical_right": "0" } ], "RRESP": [ { "physical_name": "s_axi_rresp", "physical_left": "1", "physical_right": "0" } ], "RLAST": [ { "physical_name": "s_axi_rlast", "physical_left": "0", "physical_right": "0" } ], "RVALID": [ { "physical_name": "s_axi_rvalid", "physical_left": "0", "physical_right": "0" } ], @@ -1449,85 +1461,10 @@ "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", "mode": "master", "parameters": { - "DATA_WIDTH": [ { "value": "512", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "64", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "FREQ_HZ": [ { "value": "62500000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "ADDR_WIDTH": [ { "value": "64", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_LOCK": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "NUM_READ_OUTSTANDING": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "MAX_BURST_LENGTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] - }, - "port_maps": { - "AWADDR": [ { "physical_name": "m_axi_awaddr", "physical_left": "63", "physical_right": "0" } ], - "AWLEN": [ { "physical_name": "m_axi_awlen", "physical_left": "7", "physical_right": "0" } ], - "AWSIZE": [ { "physical_name": "m_axi_awsize", "physical_left": "2", "physical_right": "0" } ], - "AWBURST": [ { "physical_name": "m_axi_awburst", "physical_left": "1", "physical_right": "0" } ], - "AWLOCK": [ { "physical_name": "m_axi_awlock", "physical_left": "0", "physical_right": "0" } ], - "AWCACHE": [ { "physical_name": "m_axi_awcache", "physical_left": "3", "physical_right": "0" } ], - "AWPROT": [ { "physical_name": "m_axi_awprot", "physical_left": "2", "physical_right": "0" } ], - "AWREGION": [ { "physical_name": "m_axi_awregion", "physical_left": "3", "physical_right": "0" } ], - "AWQOS": [ { "physical_name": "m_axi_awqos", "physical_left": "3", "physical_right": "0" } ], - "AWVALID": [ { "physical_name": "m_axi_awvalid", "physical_left": "0", "physical_right": "0" } ], - "AWREADY": [ { "physical_name": "m_axi_awready", "physical_left": "0", "physical_right": "0" } ], - "WDATA": [ { "physical_name": "m_axi_wdata", "physical_left": "511", "physical_right": "0" } ], - "WSTRB": [ { "physical_name": "m_axi_wstrb", "physical_left": "63", "physical_right": "0" } ], - "WLAST": [ { "physical_name": "m_axi_wlast", "physical_left": "0", "physical_right": "0" } ], - "WVALID": [ { "physical_name": "m_axi_wvalid", "physical_left": "0", "physical_right": "0" } ], - "WREADY": [ { "physical_name": "m_axi_wready", "physical_left": "0", "physical_right": "0" } ], - "BRESP": [ { "physical_name": "m_axi_bresp", "physical_left": "1", "physical_right": "0" } ], - "BVALID": [ { "physical_name": "m_axi_bvalid", "physical_left": "0", "physical_right": "0" } ], - "BREADY": [ { "physical_name": "m_axi_bready", "physical_left": "0", "physical_right": "0" } ], - "ARADDR": [ { "physical_name": "m_axi_araddr", "physical_left": "63", "physical_right": "0" } ], - "ARLEN": [ { "physical_name": "m_axi_arlen", "physical_left": "7", "physical_right": "0" } ], - "ARSIZE": [ { "physical_name": "m_axi_arsize", "physical_left": "2", "physical_right": "0" } ], - "ARBURST": [ { "physical_name": "m_axi_arburst", "physical_left": "1", "physical_right": "0" } ], - "ARLOCK": [ { "physical_name": "m_axi_arlock", "physical_left": "0", "physical_right": "0" } ], - "ARCACHE": [ { "physical_name": "m_axi_arcache", "physical_left": "3", "physical_right": "0" } ], - "ARPROT": [ { "physical_name": "m_axi_arprot", "physical_left": "2", "physical_right": "0" } ], - "ARREGION": [ { "physical_name": "m_axi_arregion", "physical_left": "3", "physical_right": "0" } ], - "ARQOS": [ { "physical_name": "m_axi_arqos", "physical_left": "3", "physical_right": "0" } ], - "ARVALID": [ { "physical_name": "m_axi_arvalid", "physical_left": "0", "physical_right": "0" } ], - "ARREADY": [ { "physical_name": "m_axi_arready", "physical_left": "0", "physical_right": "0" } ], - "RDATA": [ { "physical_name": "m_axi_rdata", "physical_left": "511", "physical_right": "0" } ], - "RRESP": [ { "physical_name": "m_axi_rresp", "physical_left": "1", "physical_right": "0" } ], - "RLAST": [ { "physical_name": "m_axi_rlast", "physical_left": "0", "physical_right": "0" } ], - "RVALID": [ { "physical_name": "m_axi_rvalid", "physical_left": "0", "physical_right": "0" } ], - "RREADY": [ { "physical_name": "m_axi_rready", "physical_left": "0", "physical_right": "0" } ] - } - }, - "M01_AXI": { - "vlnv": "xilinx.com:interface:aximm:1.0", - "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "master", - "parameters": { - "DATA_WIDTH": [ { "value": "512", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_HZ": [ { "value": "62500000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "4", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "64", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -1549,7 +1486,7 @@ "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -1557,6 +1494,86 @@ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { + "AWID": [ { "physical_name": "m_axi_awid", "physical_left": "3", "physical_right": "0" } ], + "AWADDR": [ { "physical_name": "m_axi_awaddr", "physical_left": "63", "physical_right": "0" } ], + "AWLEN": [ { "physical_name": "m_axi_awlen", "physical_left": "7", "physical_right": "0" } ], + "AWSIZE": [ { "physical_name": "m_axi_awsize", "physical_left": "2", "physical_right": "0" } ], + "AWBURST": [ { "physical_name": "m_axi_awburst", "physical_left": "1", "physical_right": "0" } ], + "AWLOCK": [ { "physical_name": "m_axi_awlock", "physical_left": "0", "physical_right": "0" } ], + "AWCACHE": [ { "physical_name": "m_axi_awcache", "physical_left": "3", "physical_right": "0" } ], + "AWPROT": [ { "physical_name": "m_axi_awprot", "physical_left": "2", "physical_right": "0" } ], + "AWREGION": [ { "physical_name": "m_axi_awregion", "physical_left": "3", "physical_right": "0" } ], + "AWQOS": [ { "physical_name": "m_axi_awqos", "physical_left": "3", "physical_right": "0" } ], + "AWVALID": [ { "physical_name": "m_axi_awvalid", "physical_left": "0", "physical_right": "0" } ], + "AWREADY": [ { "physical_name": "m_axi_awready", "physical_left": "0", "physical_right": "0" } ], + "WDATA": [ { "physical_name": "m_axi_wdata", "physical_left": "63", "physical_right": "0" } ], + "WSTRB": [ { "physical_name": "m_axi_wstrb", "physical_left": "7", "physical_right": "0" } ], + "WLAST": [ { "physical_name": "m_axi_wlast", "physical_left": "0", "physical_right": "0" } ], + "WVALID": [ { "physical_name": "m_axi_wvalid", "physical_left": "0", "physical_right": "0" } ], + "WREADY": [ { "physical_name": "m_axi_wready", "physical_left": "0", "physical_right": "0" } ], + "BID": [ { "physical_name": "m_axi_bid", "physical_left": "3", "physical_right": "0" } ], + "BRESP": [ { "physical_name": "m_axi_bresp", "physical_left": "1", "physical_right": "0" } ], + "BVALID": [ { "physical_name": "m_axi_bvalid", "physical_left": "0", "physical_right": "0" } ], + "BREADY": [ { "physical_name": "m_axi_bready", "physical_left": "0", "physical_right": "0" } ], + "ARID": [ { "physical_name": "m_axi_arid", "physical_left": "3", "physical_right": "0" } ], + "ARADDR": [ { "physical_name": "m_axi_araddr", "physical_left": "63", "physical_right": "0" } ], + "ARLEN": [ { "physical_name": "m_axi_arlen", "physical_left": "7", "physical_right": "0" } ], + "ARSIZE": [ { "physical_name": "m_axi_arsize", "physical_left": "2", "physical_right": "0" } ], + "ARBURST": [ { "physical_name": "m_axi_arburst", "physical_left": "1", "physical_right": "0" } ], + "ARLOCK": [ { "physical_name": "m_axi_arlock", "physical_left": "0", "physical_right": "0" } ], + "ARCACHE": [ { "physical_name": "m_axi_arcache", "physical_left": "3", "physical_right": "0" } ], + "ARPROT": [ { "physical_name": "m_axi_arprot", "physical_left": "2", "physical_right": "0" } ], + "ARREGION": [ { "physical_name": "m_axi_arregion", "physical_left": "3", "physical_right": "0" } ], + "ARQOS": [ { "physical_name": "m_axi_arqos", "physical_left": "3", "physical_right": "0" } ], + "ARVALID": [ { "physical_name": "m_axi_arvalid", "physical_left": "0", "physical_right": "0" } ], + "ARREADY": [ { "physical_name": "m_axi_arready", "physical_left": "0", "physical_right": "0" } ], + "RID": [ { "physical_name": "m_axi_rid", "physical_left": "3", "physical_right": "0" } ], + "RDATA": [ { "physical_name": "m_axi_rdata", "physical_left": "63", "physical_right": "0" } ], + "RRESP": [ { "physical_name": "m_axi_rresp", "physical_left": "1", "physical_right": "0" } ], + "RLAST": [ { "physical_name": "m_axi_rlast", "physical_left": "0", "physical_right": "0" } ], + "RVALID": [ { "physical_name": "m_axi_rvalid", "physical_left": "0", "physical_right": "0" } ], + "RREADY": [ { "physical_name": "m_axi_rready", "physical_left": "0", "physical_right": "0" } ] + } + }, + "M01_AXI": { + "vlnv": "xilinx.com:interface:aximm:1.0", + "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "master", + "parameters": { + "DATA_WIDTH": [ { "value": "64", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "62500000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "4", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "64", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "AWID": [ { "physical_name": "m_axi_awid", "physical_left": "7", "physical_right": "4" } ], "AWADDR": [ { "physical_name": "m_axi_awaddr", "physical_left": "127", "physical_right": "64" } ], "AWLEN": [ { "physical_name": "m_axi_awlen", "physical_left": "15", "physical_right": "8" } ], "AWSIZE": [ { "physical_name": "m_axi_awsize", "physical_left": "5", "physical_right": "3" } ], @@ -1568,14 +1585,16 @@ "AWQOS": [ { "physical_name": "m_axi_awqos", "physical_left": "7", "physical_right": "4" } ], "AWVALID": [ { "physical_name": "m_axi_awvalid", "physical_left": "1", "physical_right": "1" } ], "AWREADY": [ { "physical_name": "m_axi_awready", "physical_left": "1", "physical_right": "1" } ], - "WDATA": [ { "physical_name": "m_axi_wdata", "physical_left": "1023", "physical_right": "512" } ], - "WSTRB": [ { "physical_name": "m_axi_wstrb", "physical_left": "127", "physical_right": "64" } ], + "WDATA": [ { "physical_name": "m_axi_wdata", "physical_left": "127", "physical_right": "64" } ], + "WSTRB": [ { "physical_name": "m_axi_wstrb", "physical_left": "15", "physical_right": "8" } ], "WLAST": [ { "physical_name": "m_axi_wlast", "physical_left": "1", "physical_right": "1" } ], "WVALID": [ { "physical_name": "m_axi_wvalid", "physical_left": "1", "physical_right": "1" } ], "WREADY": [ { "physical_name": "m_axi_wready", "physical_left": "1", "physical_right": "1" } ], + "BID": [ { "physical_name": "m_axi_bid", "physical_left": "7", "physical_right": "4" } ], "BRESP": [ { "physical_name": "m_axi_bresp", "physical_left": "3", "physical_right": "2" } ], "BVALID": [ { "physical_name": "m_axi_bvalid", "physical_left": "1", "physical_right": "1" } ], "BREADY": [ { "physical_name": "m_axi_bready", "physical_left": "1", "physical_right": "1" } ], + "ARID": [ { "physical_name": "m_axi_arid", "physical_left": "7", "physical_right": "4" } ], "ARADDR": [ { "physical_name": "m_axi_araddr", "physical_left": "127", "physical_right": "64" } ], "ARLEN": [ { "physical_name": "m_axi_arlen", "physical_left": "15", "physical_right": "8" } ], "ARSIZE": [ { "physical_name": "m_axi_arsize", "physical_left": "5", "physical_right": "3" } ], @@ -1587,7 +1606,8 @@ "ARQOS": [ { "physical_name": "m_axi_arqos", "physical_left": "7", "physical_right": "4" } ], "ARVALID": [ { "physical_name": "m_axi_arvalid", "physical_left": "1", "physical_right": "1" } ], "ARREADY": [ { "physical_name": "m_axi_arready", "physical_left": "1", "physical_right": "1" } ], - "RDATA": [ { "physical_name": "m_axi_rdata", "physical_left": "1023", "physical_right": "512" } ], + "RID": [ { "physical_name": "m_axi_rid", "physical_left": "7", "physical_right": "4" } ], + "RDATA": [ { "physical_name": "m_axi_rdata", "physical_left": "127", "physical_right": "64" } ], "RRESP": [ { "physical_name": "m_axi_rresp", "physical_left": "3", "physical_right": "2" } ], "RLAST": [ { "physical_name": "m_axi_rlast", "physical_left": "1", "physical_right": "1" } ], "RVALID": [ { "physical_name": "m_axi_rvalid", "physical_left": "1", "physical_right": "1" } ], @@ -1599,10 +1619,10 @@ "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", "mode": "master", "parameters": { - "DATA_WIDTH": [ { "value": "512", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "64", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], "PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], "FREQ_HZ": [ { "value": "62500000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], + "ID_WIDTH": [ { "value": "4", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], "ADDR_WIDTH": [ { "value": "64", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], "AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], "ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], @@ -1624,7 +1644,7 @@ "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], @@ -1632,6 +1652,7 @@ "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] }, "port_maps": { + "AWID": [ { "physical_name": "m_axi_awid", "physical_left": "11", "physical_right": "8" } ], "AWADDR": [ { "physical_name": "m_axi_awaddr", "physical_left": "191", "physical_right": "128" } ], "AWLEN": [ { "physical_name": "m_axi_awlen", "physical_left": "23", "physical_right": "16" } ], "AWSIZE": [ { "physical_name": "m_axi_awsize", "physical_left": "8", "physical_right": "6" } ], @@ -1643,14 +1664,16 @@ "AWQOS": [ { "physical_name": "m_axi_awqos", "physical_left": "11", "physical_right": "8" } ], "AWVALID": [ { "physical_name": "m_axi_awvalid", "physical_left": "2", "physical_right": "2" } ], "AWREADY": [ { "physical_name": "m_axi_awready", "physical_left": "2", "physical_right": "2" } ], - "WDATA": [ { "physical_name": "m_axi_wdata", "physical_left": "1535", "physical_right": "1024" } ], - "WSTRB": [ { "physical_name": "m_axi_wstrb", "physical_left": "191", "physical_right": "128" } ], + "WDATA": [ { "physical_name": "m_axi_wdata", "physical_left": "191", "physical_right": "128" } ], + "WSTRB": [ { "physical_name": "m_axi_wstrb", "physical_left": "23", "physical_right": "16" } ], "WLAST": [ { "physical_name": "m_axi_wlast", "physical_left": "2", "physical_right": "2" } ], "WVALID": [ { "physical_name": "m_axi_wvalid", "physical_left": "2", "physical_right": "2" } ], "WREADY": [ { "physical_name": "m_axi_wready", "physical_left": "2", "physical_right": "2" } ], + "BID": [ { "physical_name": "m_axi_bid", "physical_left": "11", "physical_right": "8" } ], "BRESP": [ { "physical_name": "m_axi_bresp", "physical_left": "5", "physical_right": "4" } ], "BVALID": [ { "physical_name": "m_axi_bvalid", "physical_left": "2", "physical_right": "2" } ], "BREADY": [ { "physical_name": "m_axi_bready", "physical_left": "2", "physical_right": "2" } ], + "ARID": [ { "physical_name": "m_axi_arid", "physical_left": "11", "physical_right": "8" } ], "ARADDR": [ { "physical_name": "m_axi_araddr", "physical_left": "191", "physical_right": "128" } ], "ARLEN": [ { "physical_name": "m_axi_arlen", "physical_left": "23", "physical_right": "16" } ], "ARSIZE": [ { "physical_name": "m_axi_arsize", "physical_left": "8", "physical_right": "6" } ], @@ -1662,162 +1685,13 @@ "ARQOS": [ { "physical_name": "m_axi_arqos", "physical_left": "11", "physical_right": "8" } ], "ARVALID": [ { "physical_name": "m_axi_arvalid", "physical_left": "2", "physical_right": "2" } ], "ARREADY": [ { "physical_name": "m_axi_arready", "physical_left": "2", "physical_right": "2" } ], - "RDATA": [ { "physical_name": "m_axi_rdata", "physical_left": "1535", "physical_right": "1024" } ], + "RID": [ { "physical_name": "m_axi_rid", "physical_left": "11", "physical_right": "8" } ], + "RDATA": [ { "physical_name": "m_axi_rdata", "physical_left": "191", "physical_right": "128" } ], "RRESP": [ { "physical_name": "m_axi_rresp", "physical_left": "5", "physical_right": "4" } ], "RLAST": [ { "physical_name": "m_axi_rlast", "physical_left": "2", "physical_right": "2" } ], "RVALID": [ { "physical_name": "m_axi_rvalid", "physical_left": "2", "physical_right": "2" } ], "RREADY": [ { "physical_name": "m_axi_rready", "physical_left": "2", "physical_right": "2" } ] } - }, - "M03_AXI": { - "vlnv": "xilinx.com:interface:aximm:1.0", - "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "master", - "parameters": { - "DATA_WIDTH": [ { "value": "512", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], - "FREQ_HZ": [ { "value": "62500000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "ADDR_WIDTH": [ { "value": "64", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], - "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "HAS_LOCK": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "NUM_READ_OUTSTANDING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "MAX_BURST_LENGTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], - "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] - }, - "port_maps": { - "AWADDR": [ { "physical_name": "m_axi_awaddr", "physical_left": "255", "physical_right": "192" } ], - "AWLEN": [ { "physical_name": "m_axi_awlen", "physical_left": "31", "physical_right": "24" } ], - "AWSIZE": [ { "physical_name": "m_axi_awsize", "physical_left": "11", "physical_right": "9" } ], - "AWBURST": [ { "physical_name": "m_axi_awburst", "physical_left": "7", "physical_right": "6" } ], - "AWLOCK": [ { "physical_name": "m_axi_awlock", "physical_left": "3", "physical_right": "3" } ], - "AWCACHE": [ { "physical_name": "m_axi_awcache", "physical_left": "15", "physical_right": "12" } ], - "AWPROT": [ { "physical_name": "m_axi_awprot", "physical_left": "11", "physical_right": "9" } ], - "AWREGION": [ { "physical_name": "m_axi_awregion", "physical_left": "15", "physical_right": "12" } ], - "AWQOS": [ { "physical_name": "m_axi_awqos", "physical_left": "15", "physical_right": "12" } ], - "AWVALID": [ { "physical_name": "m_axi_awvalid", "physical_left": "3", "physical_right": "3" } ], - "AWREADY": [ { "physical_name": "m_axi_awready", "physical_left": "3", "physical_right": "3" } ], - "WDATA": [ { "physical_name": "m_axi_wdata", "physical_left": "2047", "physical_right": "1536" } ], - "WSTRB": [ { "physical_name": "m_axi_wstrb", "physical_left": "255", "physical_right": "192" } ], - "WLAST": [ { "physical_name": "m_axi_wlast", "physical_left": "3", "physical_right": "3" } ], - "WVALID": [ { "physical_name": "m_axi_wvalid", "physical_left": "3", "physical_right": "3" } ], - "WREADY": [ { "physical_name": "m_axi_wready", "physical_left": "3", "physical_right": "3" } ], - "BRESP": [ { "physical_name": "m_axi_bresp", "physical_left": "7", "physical_right": "6" } ], - "BVALID": [ { "physical_name": "m_axi_bvalid", "physical_left": "3", "physical_right": "3" } ], - "BREADY": [ { "physical_name": "m_axi_bready", "physical_left": "3", "physical_right": "3" } ], - "ARADDR": [ { "physical_name": "m_axi_araddr", "physical_left": "255", "physical_right": "192" } ], - "ARLEN": [ { "physical_name": "m_axi_arlen", "physical_left": "31", "physical_right": "24" } ], - "ARSIZE": [ { "physical_name": "m_axi_arsize", "physical_left": "11", "physical_right": "9" } ], - "ARBURST": [ { "physical_name": "m_axi_arburst", "physical_left": "7", "physical_right": "6" } ], - "ARLOCK": [ { "physical_name": "m_axi_arlock", "physical_left": "3", "physical_right": "3" } ], - "ARCACHE": [ { "physical_name": "m_axi_arcache", "physical_left": "15", "physical_right": "12" } ], - "ARPROT": [ { "physical_name": "m_axi_arprot", "physical_left": "11", "physical_right": "9" } ], - "ARREGION": [ { "physical_name": "m_axi_arregion", "physical_left": "15", "physical_right": "12" } ], - "ARQOS": [ { "physical_name": "m_axi_arqos", "physical_left": "15", "physical_right": "12" } ], - "ARVALID": [ { "physical_name": "m_axi_arvalid", "physical_left": "3", "physical_right": "3" } ], - "ARREADY": [ { "physical_name": "m_axi_arready", "physical_left": "3", "physical_right": "3" } ], - "RDATA": [ { "physical_name": "m_axi_rdata", "physical_left": "2047", "physical_right": "1536" } ], - "RRESP": [ { "physical_name": "m_axi_rresp", "physical_left": "7", "physical_right": "6" } ], - "RLAST": [ { "physical_name": "m_axi_rlast", "physical_left": "3", "physical_right": "3" } ], - "RVALID": [ { "physical_name": "m_axi_rvalid", "physical_left": "3", "physical_right": "3" } ], - "RREADY": [ { "physical_name": "m_axi_rready", "physical_left": "3", "physical_right": "3" } ] - } - }, - "M04_AXI": { - "vlnv": "xilinx.com:interface:aximm:1.0", - "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", - "mode": "master", - "parameters": { - "DATA_WIDTH": [ { "value": "512", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "PROTOCOL": [ { "value": "AXI4", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], - "FREQ_HZ": [ { "value": "62500000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "ID_WIDTH": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "ADDR_WIDTH": [ { "value": "64", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "AWUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "ARUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "WUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "RUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "BUSER_WIDTH": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], - "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "HAS_LOCK": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "HAS_PROT": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "HAS_CACHE": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "HAS_WSTRB": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "HAS_BRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "HAS_RRESP": [ { "value": "1", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "NUM_READ_OUTSTANDING": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "MAX_BURST_LENGTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], - "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], - "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_static_object": false } ] - }, - "port_maps": { - "AWADDR": [ { "physical_name": "m_axi_awaddr", "physical_left": "319", "physical_right": "256" } ], - "AWLEN": [ { "physical_name": "m_axi_awlen", "physical_left": "39", "physical_right": "32" } ], - "AWSIZE": [ { "physical_name": "m_axi_awsize", "physical_left": "14", "physical_right": "12" } ], - "AWBURST": [ { "physical_name": "m_axi_awburst", "physical_left": "9", "physical_right": "8" } ], - "AWLOCK": [ { "physical_name": "m_axi_awlock", "physical_left": "4", "physical_right": "4" } ], - "AWCACHE": [ { "physical_name": "m_axi_awcache", "physical_left": "19", "physical_right": "16" } ], - "AWPROT": [ { "physical_name": "m_axi_awprot", "physical_left": "14", "physical_right": "12" } ], - "AWREGION": [ { "physical_name": "m_axi_awregion", "physical_left": "19", "physical_right": "16" } ], - "AWQOS": [ { "physical_name": "m_axi_awqos", "physical_left": "19", "physical_right": "16" } ], - "AWVALID": [ { "physical_name": "m_axi_awvalid", "physical_left": "4", "physical_right": "4" } ], - "AWREADY": [ { "physical_name": "m_axi_awready", "physical_left": "4", "physical_right": "4" } ], - "WDATA": [ { "physical_name": "m_axi_wdata", "physical_left": "2559", "physical_right": "2048" } ], - "WSTRB": [ { "physical_name": "m_axi_wstrb", "physical_left": "319", "physical_right": "256" } ], - "WLAST": [ { "physical_name": "m_axi_wlast", "physical_left": "4", "physical_right": "4" } ], - "WVALID": [ { "physical_name": "m_axi_wvalid", "physical_left": "4", "physical_right": "4" } ], - "WREADY": [ { "physical_name": "m_axi_wready", "physical_left": "4", "physical_right": "4" } ], - "BRESP": [ { "physical_name": "m_axi_bresp", "physical_left": "9", "physical_right": "8" } ], - "BVALID": [ { "physical_name": "m_axi_bvalid", "physical_left": "4", "physical_right": "4" } ], - "BREADY": [ { "physical_name": "m_axi_bready", "physical_left": "4", "physical_right": "4" } ], - "ARADDR": [ { "physical_name": "m_axi_araddr", "physical_left": "319", "physical_right": "256" } ], - "ARLEN": [ { "physical_name": "m_axi_arlen", "physical_left": "39", "physical_right": "32" } ], - "ARSIZE": [ { "physical_name": "m_axi_arsize", "physical_left": "14", "physical_right": "12" } ], - "ARBURST": [ { "physical_name": "m_axi_arburst", "physical_left": "9", "physical_right": "8" } ], - "ARLOCK": [ { "physical_name": "m_axi_arlock", "physical_left": "4", "physical_right": "4" } ], - "ARCACHE": [ { "physical_name": "m_axi_arcache", "physical_left": "19", "physical_right": "16" } ], - "ARPROT": [ { "physical_name": "m_axi_arprot", "physical_left": "14", "physical_right": "12" } ], - "ARREGION": [ { "physical_name": "m_axi_arregion", "physical_left": "19", "physical_right": "16" } ], - "ARQOS": [ { "physical_name": "m_axi_arqos", "physical_left": "19", "physical_right": "16" } ], - "ARVALID": [ { "physical_name": "m_axi_arvalid", "physical_left": "4", "physical_right": "4" } ], - "ARREADY": [ { "physical_name": "m_axi_arready", "physical_left": "4", "physical_right": "4" } ], - "RDATA": [ { "physical_name": "m_axi_rdata", "physical_left": "2559", "physical_right": "2048" } ], - "RRESP": [ { "physical_name": "m_axi_rresp", "physical_left": "9", "physical_right": "8" } ], - "RLAST": [ { "physical_name": "m_axi_rlast", "physical_left": "4", "physical_right": "4" } ], - "RVALID": [ { "physical_name": "m_axi_rvalid", "physical_left": "4", "physical_right": "4" } ], - "RREADY": [ { "physical_name": "m_axi_rready", "physical_left": "4", "physical_right": "4" } ] - } } } } diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci index 2d9e016..7b0a430 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci @@ -1286,7 +1286,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "E" } ], + "TEMPERATURE_GRADE": [ { "value": "I" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, @@ -1366,13 +1366,13 @@ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", "mode": "slave", "parameters": { - "FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_util_ds_buf_0_0_IBUF_OUT", "value_src": "default_prop", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_util_ds_buf_0_0_IBUF_OUT", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { @@ -1387,10 +1387,10 @@ "ASSOCIATED_BUSIF": [ { "value": "M_AXI:S_AXI_B:M_AXI_LITE:S_AXI_LITE:M_AXI_BYPASS:M_AXI_B:S_AXIS_C2H_0:S_AXIS_C2H_1:S_AXIS_C2H_2:S_AXIS_C2H_3:M_AXIS_H2C_0:M_AXIS_H2C_1:M_AXIS_H2C_2:M_AXIS_H2C_3:sc0_ats_m_axis_cq:sc0_ats_m_axis_rc:sc0_ats_s_axis_cc:sc0_ats_s_axis_rq:sc1_ats_m_axis_cq:sc1_ats_m_axis_rc:sc1_ats_s_axis_cc:sc1_ats_s_axis_rq:cxs_tx:cxs_rx", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], "ASSOCIATED_RESET": [ { "value": "axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], "FREQ_HZ": [ { "value": "62500000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ], - "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { @@ -1416,7 +1416,7 @@ "parameters": { "BOARD.ASSOCIATED_PARAM": [ { "value": "SYS_RST_N_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], "TYPE": [ { "value": "PCIE_PERST", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], - "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { @@ -1443,32 +1443,32 @@ "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ], "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ], "HAS_BURST.VALUE_SRC": [ { "value": "CONSTANT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], - "DATA_WIDTH": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_HZ": [ { "value": "62500000", "value_src": "user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ID_WIDTH": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ADDR_WIDTH": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "WUSER_WIDTH": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "RUSER_WIDTH": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_LOCK": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_PROT": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_CACHE": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_QOS": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_REGION": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_BRESP": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_RRESP": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "MAX_BURST_LENGTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "62500000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci index 8fee704..15f94a3 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci @@ -27,7 +27,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "E" } ], + "TEMPERATURE_GRADE": [ { "value": "I" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci index 8c6eaed..255f024 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci @@ -27,7 +27,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "E" } ], + "TEMPERATURE_GRADE": [ { "value": "I" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/nitefury_pcie_xdma_ddr/project/xdma_ddr.tcl b/nitefury_pcie_xdma_ddr/project/xdma_ddr.tcl index e328cb9..4650293 100644 --- a/nitefury_pcie_xdma_ddr/project/xdma_ddr.tcl +++ b/nitefury_pcie_xdma_ddr/project/xdma_ddr.tcl @@ -16,31 +16,57 @@ set_param general.maxThreads 16 +import_ip ../sources/ip/Top_auto_cc_0/Top_auto_cc_0.xci +import_ip ../sources/ip/Top_auto_cc_1/Top_auto_cc_1.xci import_ip ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci -import_ip ../sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci -import_ip ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci -import_ip ../sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci +# import_ip ../sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci import_ip ../sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci +import_ip ../sources/ip/Top_jtag_axi_0_0/Top_jtag_axi_0_0.xci +import_ip ../sources/ip/Top_jtag_axi_0_1/Top_jtag_axi_0_1.xci +import_ip ../sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci +import_ip ../sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci +import_ip ../sources/ip/Top_util_vector_logic_0_0/Top_util_vector_logic_0_0.xci +import_ip ../sources/ip/Top_util_vector_logic_0_1/Top_util_vector_logic_0_1.xci import_ip ../sources/ip/Top_xbar_0/Top_xbar_0.xci import_ip ../sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci -import_ip ../sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci import_ip ../sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci -import_ip ../sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci +import_ip ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci +generate_target all [get_ips Top_auto_cc_0] +generate_target all [get_ips Top_auto_cc_1] generate_target all [get_ips Top_axi_bram_ctrl_0_0] -generate_target all [get_ips Top_util_vector_logic_1_3] -generate_target all [get_ips Top_xlconstant_2_0] -generate_target all [get_ips Top_util_vector_logic_1_4] +# generate_target all [get_ips Top_axi_interconnect_0_0] generate_target all [get_ips Top_blk_mem_gen_0_0] +generate_target all [get_ips Top_jtag_axi_0_0] +generate_target all [get_ips Top_jtag_axi_0_1] +generate_target all [get_ips Top_mig_7series_1_0] +generate_target all [get_ips Top_util_ds_buf_0_0] +generate_target all [get_ips Top_util_vector_logic_0_0] +generate_target all [get_ips Top_util_vector_logic_0_1] generate_target all [get_ips Top_xbar_0] generate_target all [get_ips Top_xdma_1_0] -generate_target all [get_ips Top_util_ds_buf_0_0] generate_target all [get_ips Top_xlconstant_0_0] -generate_target all [get_ips Top_mig_7series_1_0] +generate_target all [get_ips Top_xlconstant_2_0] +# synth_ip [get_ips Top_auto_cc_0] +# synth_ip [get_ips Top_auto_cc_1] +# synth_ip [get_ips Top_axi_bram_ctrl_0_0] +# # synth_ip [get_ips Top_axi_interconnect_0_0] +# synth_ip [get_ips Top_blk_mem_gen_0_0] +# synth_ip [get_ips Top_jtag_axi_0_0] +# synth_ip [get_ips Top_jtag_axi_0_1] +# synth_ip [get_ips Top_mig_7series_1_0] +# synth_ip [get_ips Top_util_ds_buf_0_0] +# synth_ip [get_ips Top_util_vector_logic_0_0] +# synth_ip [get_ips Top_util_vector_logic_0_1] +# synth_ip [get_ips Top_xbar_0] +# synth_ip [get_ips Top_xdma_1_0] +# synth_ip [get_ips Top_xlconstant_0_0] +# synth_ip [get_ips Top_xlconstant_2_0] add_file ../sources/Top.v +# # add_file ../sources/Top.bd add_file -fileset constrs_1 ../normal.xdc