From ae5c8778ea34e24ea83ee28489804e5b772f7bd1 Mon Sep 17 00:00:00 2001 From: Colin Date: Mon, 12 May 2025 17:19:33 +0800 Subject: [PATCH] Pass nitefury_pcie_xdma_ddr tcl write bit stream. --- nitefury_pcie_xdma_ddr/project/o.tcl | 47 +- nitefury_pcie_xdma_ddr/project/sources/Top.v | 907 +++++++++++++++++- .../project/sources/Top_wrapper.v | 196 ---- 3 files changed, 877 insertions(+), 273 deletions(-) delete mode 100644 nitefury_pcie_xdma_ddr/project/sources/Top_wrapper.v diff --git a/nitefury_pcie_xdma_ddr/project/o.tcl b/nitefury_pcie_xdma_ddr/project/o.tcl index 3a9a8ab..efea8b8 100644 --- a/nitefury_pcie_xdma_ddr/project/o.tcl +++ b/nitefury_pcie_xdma_ddr/project/o.tcl @@ -1,5 +1,4 @@ - create_project -force my_project set_property SOURCE_MGMT_MODE None [current_project] set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1] @@ -8,21 +7,18 @@ set_property PART xc7k480tffg1156-2L [current_project] set_param general.maxThreads 16 - -create_ip -name axi_interconnect -vendor xilinx.com -library ip -version 1.7 -module_name axi_interconnect_0 -set_property -dict [list \ - CONFIG.NUM_SLAVE_PORTS {5} \ -] [get_ips axi_interconnect_0] -generate_target -force all [get_ips axi_interconnect_0] -synth_ip [get_ips axi_interconnect_0] - +# create_ip -name axi_interconnect -vendor xilinx.com -library ip -version 1.7 -module_name axi_interconnect_0 +# set_property -dict [list \ +# CONFIG.NUM_SLAVE_PORTS {5} \ +# ] [get_ips axi_interconnect_0] +# generate_target -force all [get_ips axi_interconnect_0] +# synth_ip [get_ips axi_interconnect_0] import_ip ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci import_ip ../sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci import_ip ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci -# import_ip ../sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci import_ip ../sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci import_ip ../sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci import_ip ../sources/ip/Top_xbar_0/Top_xbar_0.xci @@ -35,7 +31,6 @@ import_ip ../sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci generate_target all [get_ips Top_axi_bram_ctrl_0_0] generate_target all [get_ips Top_util_vector_logic_1_3] generate_target all [get_ips Top_xlconstant_2_0] -# generate_target all [get_ips Top_axi_interconnect_0_0] generate_target all [get_ips Top_util_vector_logic_1_4] generate_target all [get_ips Top_blk_mem_gen_0_0] generate_target all [get_ips Top_xbar_0] @@ -44,26 +39,12 @@ generate_target all [get_ips Top_util_ds_buf_0_0] generate_target all [get_ips Top_xlconstant_0_0] generate_target all [get_ips Top_mig_7series_1_0] -synth_ip [get_ips Top_axi_bram_ctrl_0_0] -synth_ip [get_ips Top_util_vector_logic_1_3] -synth_ip [get_ips Top_xlconstant_2_0] -# synth_ip [get_ips Top_axi_interconnect_0_0] -synth_ip [get_ips Top_util_vector_logic_1_4] -synth_ip [get_ips Top_blk_mem_gen_0_0] -synth_ip [get_ips Top_xbar_0] -synth_ip [get_ips Top_xdma_1_0] -synth_ip [get_ips Top_util_ds_buf_0_0] -synth_ip [get_ips Top_xlconstant_0_0] -synth_ip [get_ips Top_mig_7series_1_0] - -add_file ../sources/Top_wrapper.v add_file ../sources/Top.v -# add_file ../sources/Top.bd add_file -fileset constrs_1 ../normal.xdc -set_property TOP Top_wrapper [current_fileset] +set_property TOP Top [current_fileset] set_property GENERIC { FREQ=100000000 SECS=1 } -objects [get_filesets sources_1] @@ -71,9 +52,9 @@ close_project open_project my_project -# Synthesis +##### Synthesis -# PRESYNTH +##### PRESYNTH # set_property DESIGN_MODE GateLvl [current_fileset] reset_run synth_1 launch_runs synth_1 -jobs 16 @@ -81,19 +62,19 @@ wait_on_run synth_1 #report_property [get_runs synth_1] if { [get_property STATUS [get_runs synth_1]] ne "synth_design Complete!" } { exit 1 } -# Place and Route +##### Place and Route reset_run impl_1 launch_runs impl_1 -jobs 16 wait_on_run impl_1 #report_property [get_runs impl_1] -if { [get_property STATUS [get_runs impl_1]] ne "route_design Complete!" } { exit 1 } +# if { [get_property STATUS [get_runs impl_1]] ne "route_design Complete!" } { exit 1 } -# Bitstream generation +##### Bitstream generation open_run impl_1 -# write_bitstream -force xdma480t -# write_debug_probes -force -quiet xdma480t.ltx +write_bitstream -force my_project +write_debug_probes -force -quiet my_project.ltx close_project diff --git a/nitefury_pcie_xdma_ddr/project/sources/Top.v b/nitefury_pcie_xdma_ddr/project/sources/Top.v index 3fac69a..1a777e1 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/Top.v +++ b/nitefury_pcie_xdma_ddr/project/sources/Top.v @@ -1,7 +1,7 @@ //Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. //-------------------------------------------------------------------------------- //Tool Version: Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022 -//Date : Mon May 12 00:48:27 2025 +//Date : Mon May 12 00:32:06 2025 //Host : deve running 64-bit Ubuntu 22.04.5 LTS //Command : generate_target Top.bd //Design : Top @@ -9,7 +9,7 @@ //-------------------------------------------------------------------------------- `timescale 1 ps / 1 ps -(* CORE_GENERATION_INFO = "Top,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Top,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=27,numReposBlks=20,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "Top.hwdef" *) +(* HW_HANDOFF = "Top.hwdef" *) (* core_generation_info = "Top,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Top,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=27,numReposBlks=20,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) module Top (C0_DDR3_0_addr, C0_DDR3_0_ba, @@ -51,45 +51,45 @@ module Top pcie_mgt_0_txn, pcie_mgt_0_txp, user_lnk_up_0); - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME C0_DDR3_0, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) output [14:0]C0_DDR3_0_addr; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 BA" *) output [2:0]C0_DDR3_0_ba; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CAS_N" *) output C0_DDR3_0_cas_n; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CK_N" *) output [0:0]C0_DDR3_0_ck_n; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CK_P" *) output [0:0]C0_DDR3_0_ck_p; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CKE" *) output [0:0]C0_DDR3_0_cke; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CS_N" *) output [0:0]C0_DDR3_0_cs_n; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 DQ" *) inout [71:0]C0_DDR3_0_dq; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 DQS_N" *) inout [8:0]C0_DDR3_0_dqs_n; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 DQS_P" *) inout [8:0]C0_DDR3_0_dqs_p; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 ODT" *) output [0:0]C0_DDR3_0_odt; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 RAS_N" *) output C0_DDR3_0_ras_n; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 RESET_N" *) output C0_DDR3_0_reset_n; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 WE_N" *) output C0_DDR3_0_we_n; - (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 C0_SYS_CLK_0 CLK_N" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME C0_SYS_CLK_0, CAN_DEBUG false, FREQ_HZ 100000000" *) input C0_SYS_CLK_0_clk_n; - (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 C0_SYS_CLK_0 CLK_P" *) input C0_SYS_CLK_0_clk_p; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME C1_DDR3_0, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) output [14:0]C1_DDR3_0_addr; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 BA" *) output [2:0]C1_DDR3_0_ba; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CAS_N" *) output C1_DDR3_0_cas_n; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CK_N" *) output [0:0]C1_DDR3_0_ck_n; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CK_P" *) output [0:0]C1_DDR3_0_ck_p; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CKE" *) output [0:0]C1_DDR3_0_cke; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CS_N" *) output [0:0]C1_DDR3_0_cs_n; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 DQ" *) inout [71:0]C1_DDR3_0_dq; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 DQS_N" *) inout [8:0]C1_DDR3_0_dqs_n; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 DQS_P" *) inout [8:0]C1_DDR3_0_dqs_p; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 ODT" *) output [0:0]C1_DDR3_0_odt; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 RAS_N" *) output C1_DDR3_0_ras_n; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 RESET_N" *) output C1_DDR3_0_reset_n; - (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 WE_N" *) output C1_DDR3_0_we_n; - (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 C1_SYS_CLK_0 CLK_N" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME C1_SYS_CLK_0, CAN_DEBUG false, FREQ_HZ 100000000" *) input C1_SYS_CLK_0_clk_n; - (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 C1_SYS_CLK_0 CLK_P" *) input C1_SYS_CLK_0_clk_p; - (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.PCI_RESET RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.PCI_RESET, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input pci_reset; - (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 pcie_clkin CLK_N" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME pcie_clkin, CAN_DEBUG false, FREQ_HZ 100000000" *) input [0:0]pcie_clkin_clk_n; - (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 pcie_clkin CLK_P" *) input [0:0]pcie_clkin_clk_p; - (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 rxn" *) input [0:0]pcie_mgt_0_rxn; - (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 rxp" *) input [0:0]pcie_mgt_0_rxp; - (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 txn" *) output [0:0]pcie_mgt_0_txn; - (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 txp" *) output [0:0]pcie_mgt_0_txp; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 ADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME C0_DDR3_0, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) output [14:0]C0_DDR3_0_addr; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 BA" *) output [2:0]C0_DDR3_0_ba; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CAS_N" *) output C0_DDR3_0_cas_n; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CK_N" *) output [0:0]C0_DDR3_0_ck_n; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CK_P" *) output [0:0]C0_DDR3_0_ck_p; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CKE" *) output [0:0]C0_DDR3_0_cke; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CS_N" *) output [0:0]C0_DDR3_0_cs_n; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 DQ" *) inout [71:0]C0_DDR3_0_dq; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 DQS_N" *) inout [8:0]C0_DDR3_0_dqs_n; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 DQS_P" *) inout [8:0]C0_DDR3_0_dqs_p; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 ODT" *) output [0:0]C0_DDR3_0_odt; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 RAS_N" *) output C0_DDR3_0_ras_n; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 RESET_N" *) output C0_DDR3_0_reset_n; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 WE_N" *) output C0_DDR3_0_we_n; + (* x_interface_info = "xilinx.com:interface:diff_clock:1.0 C0_SYS_CLK_0 CLK_N" *) (* x_interface_parameter = "XIL_INTERFACENAME C0_SYS_CLK_0, CAN_DEBUG false, FREQ_HZ 100000000" *) input C0_SYS_CLK_0_clk_n; + (* x_interface_info = "xilinx.com:interface:diff_clock:1.0 C0_SYS_CLK_0 CLK_P" *) input C0_SYS_CLK_0_clk_p; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 ADDR" *) (* x_interface_parameter = "XIL_INTERFACENAME C1_DDR3_0, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) output [14:0]C1_DDR3_0_addr; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 BA" *) output [2:0]C1_DDR3_0_ba; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CAS_N" *) output C1_DDR3_0_cas_n; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CK_N" *) output [0:0]C1_DDR3_0_ck_n; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CK_P" *) output [0:0]C1_DDR3_0_ck_p; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CKE" *) output [0:0]C1_DDR3_0_cke; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CS_N" *) output [0:0]C1_DDR3_0_cs_n; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 DQ" *) inout [71:0]C1_DDR3_0_dq; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 DQS_N" *) inout [8:0]C1_DDR3_0_dqs_n; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 DQS_P" *) inout [8:0]C1_DDR3_0_dqs_p; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 ODT" *) output [0:0]C1_DDR3_0_odt; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 RAS_N" *) output C1_DDR3_0_ras_n; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 RESET_N" *) output C1_DDR3_0_reset_n; + (* x_interface_info = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 WE_N" *) output C1_DDR3_0_we_n; + (* x_interface_info = "xilinx.com:interface:diff_clock:1.0 C1_SYS_CLK_0 CLK_N" *) (* x_interface_parameter = "XIL_INTERFACENAME C1_SYS_CLK_0, CAN_DEBUG false, FREQ_HZ 100000000" *) input C1_SYS_CLK_0_clk_n; + (* x_interface_info = "xilinx.com:interface:diff_clock:1.0 C1_SYS_CLK_0 CLK_P" *) input C1_SYS_CLK_0_clk_p; + (* x_interface_info = "xilinx.com:signal:reset:1.0 RST.PCI_RESET RST" *) (* x_interface_parameter = "XIL_INTERFACENAME RST.PCI_RESET, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input pci_reset; + (* x_interface_info = "xilinx.com:interface:diff_clock:1.0 pcie_clkin CLK_N" *) (* x_interface_parameter = "XIL_INTERFACENAME pcie_clkin, CAN_DEBUG false, FREQ_HZ 100000000" *) input [0:0]pcie_clkin_clk_n; + (* x_interface_info = "xilinx.com:interface:diff_clock:1.0 pcie_clkin CLK_P" *) input [0:0]pcie_clkin_clk_p; + (* x_interface_info = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 rxn" *) input [0:0]pcie_mgt_0_rxn; + (* x_interface_info = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 rxp" *) input [0:0]pcie_mgt_0_rxp; + (* x_interface_info = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 txn" *) output [0:0]pcie_mgt_0_txn; + (* x_interface_info = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 txp" *) output [0:0]pcie_mgt_0_txp; output user_lnk_up_0; wire C0_SYS_CLK_0_1_CLK_N; @@ -390,7 +390,7 @@ module Top .s_axi_wready(axi_interconnect_0_M04_AXI_WREADY), .s_axi_wstrb(axi_interconnect_0_M04_AXI_WSTRB), .s_axi_wvalid(axi_interconnect_0_M04_AXI_WVALID)); - axi_interconnect_0 axi_interconnect_0 + Top_axi_interconnect_0_0 axi_interconnect_0 (.ACLK(xdma_1_axi_aclk), .ARESETN(xdma_1_axi_aresetn), .M00_ACLK(mig_7series_1_ui_clk), @@ -729,7 +729,7 @@ module Top Top_util_vector_logic_1_4 util_vector_logic_2 (.Op1({mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst}), .Res(util_vector_logic_2_Res)); - Top_xdma_1_1 xdma_1 + Top_xdma_1_0 xdma_1 (.axi_aclk(xdma_1_axi_aclk), .axi_aresetn(xdma_1_axi_aresetn), .cfg_mgmt_addr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), @@ -781,8 +781,827 @@ module Top .sys_rst_n(pci_reset_1), .user_lnk_up(xdma_1_user_lnk_up), .usr_irq_req(1'b0)); - Top_xlconstant_0_1 xlconstant_0 + Top_xlconstant_0_0 xlconstant_0 (.dout(xlconstant_0_dout)); Top_xlconstant_2_0 xlconstant_2 (.dout(xlconstant_2_dout)); endmodule + +module Top_axi_interconnect_0_0 + (ACLK, + ARESETN, + M00_ACLK, + M00_ARESETN, + M00_AXI_araddr, + M00_AXI_arready, + M00_AXI_arvalid, + M00_AXI_awaddr, + M00_AXI_awready, + M00_AXI_awvalid, + M00_AXI_bready, + M00_AXI_bresp, + M00_AXI_bvalid, + M00_AXI_rdata, + M00_AXI_rready, + M00_AXI_rresp, + M00_AXI_rvalid, + M00_AXI_wdata, + M00_AXI_wready, + M00_AXI_wvalid, + M01_ACLK, + M01_ARESETN, + M01_AXI_araddr, + M01_AXI_arburst, + M01_AXI_arcache, + M01_AXI_arlen, + M01_AXI_arlock, + M01_AXI_arprot, + M01_AXI_arqos, + M01_AXI_arready, + M01_AXI_arsize, + M01_AXI_arvalid, + M01_AXI_awaddr, + M01_AXI_awburst, + M01_AXI_awcache, + M01_AXI_awlen, + M01_AXI_awlock, + M01_AXI_awprot, + M01_AXI_awqos, + M01_AXI_awready, + M01_AXI_awsize, + M01_AXI_awvalid, + M01_AXI_bready, + M01_AXI_bresp, + M01_AXI_bvalid, + M01_AXI_rdata, + M01_AXI_rlast, + M01_AXI_rready, + M01_AXI_rresp, + M01_AXI_rvalid, + M01_AXI_wdata, + M01_AXI_wlast, + M01_AXI_wready, + M01_AXI_wstrb, + M01_AXI_wvalid, + M02_ACLK, + M02_ARESETN, + M02_AXI_araddr, + M02_AXI_arready, + M02_AXI_arvalid, + M02_AXI_awaddr, + M02_AXI_awready, + M02_AXI_awvalid, + M02_AXI_bready, + M02_AXI_bresp, + M02_AXI_bvalid, + M02_AXI_rdata, + M02_AXI_rready, + M02_AXI_rresp, + M02_AXI_rvalid, + M02_AXI_wdata, + M02_AXI_wready, + M02_AXI_wvalid, + M03_ACLK, + M03_ARESETN, + M03_AXI_araddr, + M03_AXI_arburst, + M03_AXI_arcache, + M03_AXI_arlen, + M03_AXI_arlock, + M03_AXI_arprot, + M03_AXI_arqos, + M03_AXI_arready, + M03_AXI_arsize, + M03_AXI_arvalid, + M03_AXI_awaddr, + M03_AXI_awburst, + M03_AXI_awcache, + M03_AXI_awlen, + M03_AXI_awlock, + M03_AXI_awprot, + M03_AXI_awqos, + M03_AXI_awready, + M03_AXI_awsize, + M03_AXI_awvalid, + M03_AXI_bready, + M03_AXI_bresp, + M03_AXI_bvalid, + M03_AXI_rdata, + M03_AXI_rlast, + M03_AXI_rready, + M03_AXI_rresp, + M03_AXI_rvalid, + M03_AXI_wdata, + M03_AXI_wlast, + M03_AXI_wready, + M03_AXI_wstrb, + M03_AXI_wvalid, + M04_ACLK, + M04_ARESETN, + M04_AXI_araddr, + M04_AXI_arburst, + M04_AXI_arcache, + M04_AXI_arlen, + M04_AXI_arlock, + M04_AXI_arprot, + M04_AXI_arready, + M04_AXI_arsize, + M04_AXI_arvalid, + M04_AXI_awaddr, + M04_AXI_awburst, + M04_AXI_awcache, + M04_AXI_awlen, + M04_AXI_awlock, + M04_AXI_awprot, + M04_AXI_awready, + M04_AXI_awsize, + M04_AXI_awvalid, + M04_AXI_bready, + M04_AXI_bresp, + M04_AXI_bvalid, + M04_AXI_rdata, + M04_AXI_rlast, + M04_AXI_rready, + M04_AXI_rresp, + M04_AXI_rvalid, + M04_AXI_wdata, + M04_AXI_wlast, + M04_AXI_wready, + M04_AXI_wstrb, + M04_AXI_wvalid, + S00_ACLK, + S00_ARESETN, + S00_AXI_araddr, + S00_AXI_arburst, + S00_AXI_arcache, + S00_AXI_arid, + S00_AXI_arlen, + S00_AXI_arlock, + S00_AXI_arprot, + S00_AXI_arready, + S00_AXI_arsize, + S00_AXI_arvalid, + S00_AXI_awaddr, + S00_AXI_awburst, + S00_AXI_awcache, + S00_AXI_awid, + S00_AXI_awlen, + S00_AXI_awlock, + S00_AXI_awprot, + S00_AXI_awready, + S00_AXI_awsize, + S00_AXI_awvalid, + S00_AXI_bid, + S00_AXI_bready, + S00_AXI_bresp, + S00_AXI_bvalid, + S00_AXI_rdata, + S00_AXI_rid, + S00_AXI_rlast, + S00_AXI_rready, + S00_AXI_rresp, + S00_AXI_rvalid, + S00_AXI_wdata, + S00_AXI_wlast, + S00_AXI_wready, + S00_AXI_wstrb, + S00_AXI_wvalid); + input ACLK; + input ARESETN; + input M00_ACLK; + input [7:0]M00_ARESETN; + output [31:0]M00_AXI_araddr; + input M00_AXI_arready; + output M00_AXI_arvalid; + output [31:0]M00_AXI_awaddr; + input M00_AXI_awready; + output M00_AXI_awvalid; + output M00_AXI_bready; + input [1:0]M00_AXI_bresp; + input M00_AXI_bvalid; + input [31:0]M00_AXI_rdata; + output M00_AXI_rready; + input [1:0]M00_AXI_rresp; + input M00_AXI_rvalid; + output [31:0]M00_AXI_wdata; + input M00_AXI_wready; + output M00_AXI_wvalid; + input M01_ACLK; + input [7:0]M01_ARESETN; + output [30:0]M01_AXI_araddr; + output [1:0]M01_AXI_arburst; + output [3:0]M01_AXI_arcache; + output [7:0]M01_AXI_arlen; + output M01_AXI_arlock; + output [2:0]M01_AXI_arprot; + output [3:0]M01_AXI_arqos; + input M01_AXI_arready; + output [2:0]M01_AXI_arsize; + output M01_AXI_arvalid; + output [30:0]M01_AXI_awaddr; + output [1:0]M01_AXI_awburst; + output [3:0]M01_AXI_awcache; + output [7:0]M01_AXI_awlen; + output M01_AXI_awlock; + output [2:0]M01_AXI_awprot; + output [3:0]M01_AXI_awqos; + input M01_AXI_awready; + output [2:0]M01_AXI_awsize; + output M01_AXI_awvalid; + output M01_AXI_bready; + input [1:0]M01_AXI_bresp; + input M01_AXI_bvalid; + input [511:0]M01_AXI_rdata; + input M01_AXI_rlast; + output M01_AXI_rready; + input [1:0]M01_AXI_rresp; + input M01_AXI_rvalid; + output [511:0]M01_AXI_wdata; + output M01_AXI_wlast; + input M01_AXI_wready; + output [63:0]M01_AXI_wstrb; + output M01_AXI_wvalid; + input M02_ACLK; + input [7:0]M02_ARESETN; + output [31:0]M02_AXI_araddr; + input M02_AXI_arready; + output M02_AXI_arvalid; + output [31:0]M02_AXI_awaddr; + input M02_AXI_awready; + output M02_AXI_awvalid; + output M02_AXI_bready; + input [1:0]M02_AXI_bresp; + input M02_AXI_bvalid; + input [31:0]M02_AXI_rdata; + output M02_AXI_rready; + input [1:0]M02_AXI_rresp; + input M02_AXI_rvalid; + output [31:0]M02_AXI_wdata; + input M02_AXI_wready; + output M02_AXI_wvalid; + input M03_ACLK; + input [7:0]M03_ARESETN; + output [30:0]M03_AXI_araddr; + output [1:0]M03_AXI_arburst; + output [3:0]M03_AXI_arcache; + output [7:0]M03_AXI_arlen; + output M03_AXI_arlock; + output [2:0]M03_AXI_arprot; + output [3:0]M03_AXI_arqos; + input M03_AXI_arready; + output [2:0]M03_AXI_arsize; + output M03_AXI_arvalid; + output [30:0]M03_AXI_awaddr; + output [1:0]M03_AXI_awburst; + output [3:0]M03_AXI_awcache; + output [7:0]M03_AXI_awlen; + output M03_AXI_awlock; + output [2:0]M03_AXI_awprot; + output [3:0]M03_AXI_awqos; + input M03_AXI_awready; + output [2:0]M03_AXI_awsize; + output M03_AXI_awvalid; + output M03_AXI_bready; + input [1:0]M03_AXI_bresp; + input M03_AXI_bvalid; + input [511:0]M03_AXI_rdata; + input M03_AXI_rlast; + output M03_AXI_rready; + input [1:0]M03_AXI_rresp; + input M03_AXI_rvalid; + output [511:0]M03_AXI_wdata; + output M03_AXI_wlast; + input M03_AXI_wready; + output [63:0]M03_AXI_wstrb; + output M03_AXI_wvalid; + input M04_ACLK; + input M04_ARESETN; + output [12:0]M04_AXI_araddr; + output [1:0]M04_AXI_arburst; + output [3:0]M04_AXI_arcache; + output [7:0]M04_AXI_arlen; + output M04_AXI_arlock; + output [2:0]M04_AXI_arprot; + input M04_AXI_arready; + output [2:0]M04_AXI_arsize; + output M04_AXI_arvalid; + output [12:0]M04_AXI_awaddr; + output [1:0]M04_AXI_awburst; + output [3:0]M04_AXI_awcache; + output [7:0]M04_AXI_awlen; + output M04_AXI_awlock; + output [2:0]M04_AXI_awprot; + input M04_AXI_awready; + output [2:0]M04_AXI_awsize; + output M04_AXI_awvalid; + output M04_AXI_bready; + input [1:0]M04_AXI_bresp; + input M04_AXI_bvalid; + input [31:0]M04_AXI_rdata; + input M04_AXI_rlast; + output M04_AXI_rready; + input [1:0]M04_AXI_rresp; + input M04_AXI_rvalid; + output [31:0]M04_AXI_wdata; + output M04_AXI_wlast; + input M04_AXI_wready; + output [3:0]M04_AXI_wstrb; + output M04_AXI_wvalid; + input S00_ACLK; + input S00_ARESETN; + input [63:0]S00_AXI_araddr; + input [1:0]S00_AXI_arburst; + input [3:0]S00_AXI_arcache; + input [3:0]S00_AXI_arid; + input [7:0]S00_AXI_arlen; + input [0:0]S00_AXI_arlock; + input [2:0]S00_AXI_arprot; + output S00_AXI_arready; + input [2:0]S00_AXI_arsize; + input S00_AXI_arvalid; + input [63:0]S00_AXI_awaddr; + input [1:0]S00_AXI_awburst; + input [3:0]S00_AXI_awcache; + input [3:0]S00_AXI_awid; + input [7:0]S00_AXI_awlen; + input [0:0]S00_AXI_awlock; + input [2:0]S00_AXI_awprot; + output S00_AXI_awready; + input [2:0]S00_AXI_awsize; + input S00_AXI_awvalid; + output [3:0]S00_AXI_bid; + input S00_AXI_bready; + output [1:0]S00_AXI_bresp; + output S00_AXI_bvalid; + output [63:0]S00_AXI_rdata; + output [3:0]S00_AXI_rid; + output S00_AXI_rlast; + input S00_AXI_rready; + output [1:0]S00_AXI_rresp; + output S00_AXI_rvalid; + input [63:0]S00_AXI_wdata; + input S00_AXI_wlast; + output S00_AXI_wready; + input [7:0]S00_AXI_wstrb; + input S00_AXI_wvalid; + + wire M00_ACLK_1; + wire [7:0]M00_ARESETN_1; + wire M01_ACLK_1; + wire [7:0]M01_ARESETN_1; + wire M02_ACLK_1; + wire [7:0]M02_ARESETN_1; + wire M03_ACLK_1; + wire [7:0]M03_ARESETN_1; + wire M04_ACLK_1; + wire M04_ARESETN_1; + wire S00_ACLK_1; + wire S00_ARESETN_1; + wire axi_interconnect_0_ACLK_net; + wire axi_interconnect_0_ARESETN_net; + wire [63:0]axi_interconnect_0_to_s00_couplers_ARADDR; + wire [1:0]axi_interconnect_0_to_s00_couplers_ARBURST; + wire [3:0]axi_interconnect_0_to_s00_couplers_ARCACHE; + wire [3:0]axi_interconnect_0_to_s00_couplers_ARID; + wire [7:0]axi_interconnect_0_to_s00_couplers_ARLEN; + wire [0:0]axi_interconnect_0_to_s00_couplers_ARLOCK; + wire [2:0]axi_interconnect_0_to_s00_couplers_ARPROT; + wire axi_interconnect_0_to_s00_couplers_ARREADY; + wire [2:0]axi_interconnect_0_to_s00_couplers_ARSIZE; + wire axi_interconnect_0_to_s00_couplers_ARVALID; + wire [63:0]axi_interconnect_0_to_s00_couplers_AWADDR; + wire [1:0]axi_interconnect_0_to_s00_couplers_AWBURST; + wire [3:0]axi_interconnect_0_to_s00_couplers_AWCACHE; + wire [3:0]axi_interconnect_0_to_s00_couplers_AWID; + wire [7:0]axi_interconnect_0_to_s00_couplers_AWLEN; + wire [0:0]axi_interconnect_0_to_s00_couplers_AWLOCK; + wire [2:0]axi_interconnect_0_to_s00_couplers_AWPROT; + wire axi_interconnect_0_to_s00_couplers_AWREADY; + wire [2:0]axi_interconnect_0_to_s00_couplers_AWSIZE; + wire axi_interconnect_0_to_s00_couplers_AWVALID; + wire [3:0]axi_interconnect_0_to_s00_couplers_BID; + wire axi_interconnect_0_to_s00_couplers_BREADY; + wire [1:0]axi_interconnect_0_to_s00_couplers_BRESP; + wire axi_interconnect_0_to_s00_couplers_BVALID; + wire [63:0]axi_interconnect_0_to_s00_couplers_RDATA; + wire [3:0]axi_interconnect_0_to_s00_couplers_RID; + wire axi_interconnect_0_to_s00_couplers_RLAST; + wire axi_interconnect_0_to_s00_couplers_RREADY; + wire [1:0]axi_interconnect_0_to_s00_couplers_RRESP; + wire axi_interconnect_0_to_s00_couplers_RVALID; + wire [63:0]axi_interconnect_0_to_s00_couplers_WDATA; + wire axi_interconnect_0_to_s00_couplers_WLAST; + wire axi_interconnect_0_to_s00_couplers_WREADY; + wire [7:0]axi_interconnect_0_to_s00_couplers_WSTRB; + wire axi_interconnect_0_to_s00_couplers_WVALID; + wire [31:0]m00_couplers_to_axi_interconnect_0_ARADDR; + wire m00_couplers_to_axi_interconnect_0_ARREADY; + wire m00_couplers_to_axi_interconnect_0_ARVALID; + wire [31:0]m00_couplers_to_axi_interconnect_0_AWADDR; + wire m00_couplers_to_axi_interconnect_0_AWREADY; + wire m00_couplers_to_axi_interconnect_0_AWVALID; + wire m00_couplers_to_axi_interconnect_0_BREADY; + wire [1:0]m00_couplers_to_axi_interconnect_0_BRESP; + wire m00_couplers_to_axi_interconnect_0_BVALID; + wire [31:0]m00_couplers_to_axi_interconnect_0_RDATA; + wire m00_couplers_to_axi_interconnect_0_RREADY; + wire [1:0]m00_couplers_to_axi_interconnect_0_RRESP; + wire m00_couplers_to_axi_interconnect_0_RVALID; + wire [31:0]m00_couplers_to_axi_interconnect_0_WDATA; + wire m00_couplers_to_axi_interconnect_0_WREADY; + wire m00_couplers_to_axi_interconnect_0_WVALID; + wire [30:0]m01_couplers_to_axi_interconnect_0_ARADDR; + wire [1:0]m01_couplers_to_axi_interconnect_0_ARBURST; + wire [3:0]m01_couplers_to_axi_interconnect_0_ARCACHE; + wire [7:0]m01_couplers_to_axi_interconnect_0_ARLEN; + wire m01_couplers_to_axi_interconnect_0_ARLOCK; + wire [2:0]m01_couplers_to_axi_interconnect_0_ARPROT; + wire [3:0]m01_couplers_to_axi_interconnect_0_ARQOS; + wire m01_couplers_to_axi_interconnect_0_ARREADY; + wire [2:0]m01_couplers_to_axi_interconnect_0_ARSIZE; + wire m01_couplers_to_axi_interconnect_0_ARVALID; + wire [30:0]m01_couplers_to_axi_interconnect_0_AWADDR; + wire [1:0]m01_couplers_to_axi_interconnect_0_AWBURST; + wire [3:0]m01_couplers_to_axi_interconnect_0_AWCACHE; + wire [7:0]m01_couplers_to_axi_interconnect_0_AWLEN; + wire m01_couplers_to_axi_interconnect_0_AWLOCK; + wire [2:0]m01_couplers_to_axi_interconnect_0_AWPROT; + wire [3:0]m01_couplers_to_axi_interconnect_0_AWQOS; + wire m01_couplers_to_axi_interconnect_0_AWREADY; + wire [2:0]m01_couplers_to_axi_interconnect_0_AWSIZE; + wire m01_couplers_to_axi_interconnect_0_AWVALID; + wire m01_couplers_to_axi_interconnect_0_BREADY; + wire [1:0]m01_couplers_to_axi_interconnect_0_BRESP; + wire m01_couplers_to_axi_interconnect_0_BVALID; + wire [511:0]m01_couplers_to_axi_interconnect_0_RDATA; + wire m01_couplers_to_axi_interconnect_0_RLAST; + wire m01_couplers_to_axi_interconnect_0_RREADY; + wire [1:0]m01_couplers_to_axi_interconnect_0_RRESP; + wire m01_couplers_to_axi_interconnect_0_RVALID; + wire [511:0]m01_couplers_to_axi_interconnect_0_WDATA; + wire m01_couplers_to_axi_interconnect_0_WLAST; + wire m01_couplers_to_axi_interconnect_0_WREADY; + wire [63:0]m01_couplers_to_axi_interconnect_0_WSTRB; + wire m01_couplers_to_axi_interconnect_0_WVALID; + wire [31:0]m02_couplers_to_axi_interconnect_0_ARADDR; + wire m02_couplers_to_axi_interconnect_0_ARREADY; + wire m02_couplers_to_axi_interconnect_0_ARVALID; + wire [31:0]m02_couplers_to_axi_interconnect_0_AWADDR; + wire m02_couplers_to_axi_interconnect_0_AWREADY; + wire m02_couplers_to_axi_interconnect_0_AWVALID; + wire m02_couplers_to_axi_interconnect_0_BREADY; + wire [1:0]m02_couplers_to_axi_interconnect_0_BRESP; + wire m02_couplers_to_axi_interconnect_0_BVALID; + wire [31:0]m02_couplers_to_axi_interconnect_0_RDATA; + wire m02_couplers_to_axi_interconnect_0_RREADY; + wire [1:0]m02_couplers_to_axi_interconnect_0_RRESP; + wire m02_couplers_to_axi_interconnect_0_RVALID; + wire [31:0]m02_couplers_to_axi_interconnect_0_WDATA; + wire m02_couplers_to_axi_interconnect_0_WREADY; + wire m02_couplers_to_axi_interconnect_0_WVALID; + wire [30:0]m03_couplers_to_axi_interconnect_0_ARADDR; + wire [1:0]m03_couplers_to_axi_interconnect_0_ARBURST; + wire [3:0]m03_couplers_to_axi_interconnect_0_ARCACHE; + wire [7:0]m03_couplers_to_axi_interconnect_0_ARLEN; + wire m03_couplers_to_axi_interconnect_0_ARLOCK; + wire [2:0]m03_couplers_to_axi_interconnect_0_ARPROT; + wire [3:0]m03_couplers_to_axi_interconnect_0_ARQOS; + wire m03_couplers_to_axi_interconnect_0_ARREADY; + wire [2:0]m03_couplers_to_axi_interconnect_0_ARSIZE; + wire m03_couplers_to_axi_interconnect_0_ARVALID; + wire [30:0]m03_couplers_to_axi_interconnect_0_AWADDR; + wire [1:0]m03_couplers_to_axi_interconnect_0_AWBURST; + wire [3:0]m03_couplers_to_axi_interconnect_0_AWCACHE; + wire [7:0]m03_couplers_to_axi_interconnect_0_AWLEN; + wire m03_couplers_to_axi_interconnect_0_AWLOCK; + wire [2:0]m03_couplers_to_axi_interconnect_0_AWPROT; + wire [3:0]m03_couplers_to_axi_interconnect_0_AWQOS; + wire m03_couplers_to_axi_interconnect_0_AWREADY; + wire [2:0]m03_couplers_to_axi_interconnect_0_AWSIZE; + wire m03_couplers_to_axi_interconnect_0_AWVALID; + wire m03_couplers_to_axi_interconnect_0_BREADY; + wire [1:0]m03_couplers_to_axi_interconnect_0_BRESP; + wire m03_couplers_to_axi_interconnect_0_BVALID; + wire [511:0]m03_couplers_to_axi_interconnect_0_RDATA; + wire m03_couplers_to_axi_interconnect_0_RLAST; + wire m03_couplers_to_axi_interconnect_0_RREADY; + wire [1:0]m03_couplers_to_axi_interconnect_0_RRESP; + wire m03_couplers_to_axi_interconnect_0_RVALID; + wire [511:0]m03_couplers_to_axi_interconnect_0_WDATA; + wire m03_couplers_to_axi_interconnect_0_WLAST; + wire m03_couplers_to_axi_interconnect_0_WREADY; + wire [63:0]m03_couplers_to_axi_interconnect_0_WSTRB; + wire m03_couplers_to_axi_interconnect_0_WVALID; + wire [12:0]m04_couplers_to_axi_interconnect_0_ARADDR; + wire [1:0]m04_couplers_to_axi_interconnect_0_ARBURST; + wire [3:0]m04_couplers_to_axi_interconnect_0_ARCACHE; + wire [7:0]m04_couplers_to_axi_interconnect_0_ARLEN; + wire m04_couplers_to_axi_interconnect_0_ARLOCK; + wire [2:0]m04_couplers_to_axi_interconnect_0_ARPROT; + wire m04_couplers_to_axi_interconnect_0_ARREADY; + wire [2:0]m04_couplers_to_axi_interconnect_0_ARSIZE; + wire m04_couplers_to_axi_interconnect_0_ARVALID; + wire [12:0]m04_couplers_to_axi_interconnect_0_AWADDR; + wire [1:0]m04_couplers_to_axi_interconnect_0_AWBURST; + wire [3:0]m04_couplers_to_axi_interconnect_0_AWCACHE; + wire [7:0]m04_couplers_to_axi_interconnect_0_AWLEN; + wire m04_couplers_to_axi_interconnect_0_AWLOCK; + wire [2:0]m04_couplers_to_axi_interconnect_0_AWPROT; + wire m04_couplers_to_axi_interconnect_0_AWREADY; + wire [2:0]m04_couplers_to_axi_interconnect_0_AWSIZE; + wire m04_couplers_to_axi_interconnect_0_AWVALID; + wire m04_couplers_to_axi_interconnect_0_BREADY; + wire [1:0]m04_couplers_to_axi_interconnect_0_BRESP; + wire m04_couplers_to_axi_interconnect_0_BVALID; + wire [31:0]m04_couplers_to_axi_interconnect_0_RDATA; + wire m04_couplers_to_axi_interconnect_0_RLAST; + wire m04_couplers_to_axi_interconnect_0_RREADY; + wire [1:0]m04_couplers_to_axi_interconnect_0_RRESP; + wire m04_couplers_to_axi_interconnect_0_RVALID; + wire [31:0]m04_couplers_to_axi_interconnect_0_WDATA; + wire m04_couplers_to_axi_interconnect_0_WLAST; + wire m04_couplers_to_axi_interconnect_0_WREADY; + wire [3:0]m04_couplers_to_axi_interconnect_0_WSTRB; + wire m04_couplers_to_axi_interconnect_0_WVALID; + wire [63:0]s00_couplers_to_xbar_ARADDR; + wire [1:0]s00_couplers_to_xbar_ARBURST; + wire [3:0]s00_couplers_to_xbar_ARCACHE; + wire [7:0]s00_couplers_to_xbar_ARLEN; + wire [0:0]s00_couplers_to_xbar_ARLOCK; + wire [2:0]s00_couplers_to_xbar_ARPROT; + wire [3:0]s00_couplers_to_xbar_ARQOS; + wire [0:0]s00_couplers_to_xbar_ARREADY; + wire [2:0]s00_couplers_to_xbar_ARSIZE; + wire s00_couplers_to_xbar_ARVALID; + wire [63:0]s00_couplers_to_xbar_AWADDR; + wire [1:0]s00_couplers_to_xbar_AWBURST; + wire [3:0]s00_couplers_to_xbar_AWCACHE; + wire [7:0]s00_couplers_to_xbar_AWLEN; + wire [0:0]s00_couplers_to_xbar_AWLOCK; + wire [2:0]s00_couplers_to_xbar_AWPROT; + wire [3:0]s00_couplers_to_xbar_AWQOS; + wire [0:0]s00_couplers_to_xbar_AWREADY; + wire [2:0]s00_couplers_to_xbar_AWSIZE; + wire s00_couplers_to_xbar_AWVALID; + wire s00_couplers_to_xbar_BREADY; + wire [1:0]s00_couplers_to_xbar_BRESP; + wire [0:0]s00_couplers_to_xbar_BVALID; + wire [511:0]s00_couplers_to_xbar_RDATA; + wire [0:0]s00_couplers_to_xbar_RLAST; + wire s00_couplers_to_xbar_RREADY; + wire [1:0]s00_couplers_to_xbar_RRESP; + wire [0:0]s00_couplers_to_xbar_RVALID; + wire [511:0]s00_couplers_to_xbar_WDATA; + wire s00_couplers_to_xbar_WLAST; + wire [0:0]s00_couplers_to_xbar_WREADY; + wire [63:0]s00_couplers_to_xbar_WSTRB; + wire s00_couplers_to_xbar_WVALID; + wire [63:0]xbar_to_m00_couplers_ARADDR; + wire [1:0]xbar_to_m00_couplers_ARBURST; + wire [3:0]xbar_to_m00_couplers_ARCACHE; + wire [7:0]xbar_to_m00_couplers_ARLEN; + wire [0:0]xbar_to_m00_couplers_ARLOCK; + wire [2:0]xbar_to_m00_couplers_ARPROT; + wire [3:0]xbar_to_m00_couplers_ARQOS; + wire xbar_to_m00_couplers_ARREADY; + wire [3:0]xbar_to_m00_couplers_ARREGION; + wire [2:0]xbar_to_m00_couplers_ARSIZE; + wire [0:0]xbar_to_m00_couplers_ARVALID; + wire [63:0]xbar_to_m00_couplers_AWADDR; + wire [1:0]xbar_to_m00_couplers_AWBURST; + wire [3:0]xbar_to_m00_couplers_AWCACHE; + wire [7:0]xbar_to_m00_couplers_AWLEN; + wire [0:0]xbar_to_m00_couplers_AWLOCK; + wire [2:0]xbar_to_m00_couplers_AWPROT; + wire [3:0]xbar_to_m00_couplers_AWQOS; + wire xbar_to_m00_couplers_AWREADY; + wire [3:0]xbar_to_m00_couplers_AWREGION; + wire [2:0]xbar_to_m00_couplers_AWSIZE; + wire [0:0]xbar_to_m00_couplers_AWVALID; + wire [0:0]xbar_to_m00_couplers_BREADY; + wire [1:0]xbar_to_m00_couplers_BRESP; + wire xbar_to_m00_couplers_BVALID; + wire [511:0]xbar_to_m00_couplers_RDATA; + wire xbar_to_m00_couplers_RLAST; + wire [0:0]xbar_to_m00_couplers_RREADY; + wire [1:0]xbar_to_m00_couplers_RRESP; + wire xbar_to_m00_couplers_RVALID; + wire [511:0]xbar_to_m00_couplers_WDATA; + wire [0:0]xbar_to_m00_couplers_WLAST; + wire xbar_to_m00_couplers_WREADY; + wire [63:0]xbar_to_m00_couplers_WSTRB; + wire [0:0]xbar_to_m00_couplers_WVALID; + wire [127:64]xbar_to_m01_couplers_ARADDR; + wire [3:2]xbar_to_m01_couplers_ARBURST; + wire [7:4]xbar_to_m01_couplers_ARCACHE; + wire [15:8]xbar_to_m01_couplers_ARLEN; + wire [1:1]xbar_to_m01_couplers_ARLOCK; + wire [5:3]xbar_to_m01_couplers_ARPROT; + wire [7:4]xbar_to_m01_couplers_ARQOS; + wire xbar_to_m01_couplers_ARREADY; + wire [7:4]xbar_to_m01_couplers_ARREGION; + wire [5:3]xbar_to_m01_couplers_ARSIZE; + wire [1:1]xbar_to_m01_couplers_ARVALID; + wire [127:64]xbar_to_m01_couplers_AWADDR; + wire [3:2]xbar_to_m01_couplers_AWBURST; + wire [7:4]xbar_to_m01_couplers_AWCACHE; + wire [15:8]xbar_to_m01_couplers_AWLEN; + wire [1:1]xbar_to_m01_couplers_AWLOCK; + wire [5:3]xbar_to_m01_couplers_AWPROT; + wire [7:4]xbar_to_m01_couplers_AWQOS; + wire xbar_to_m01_couplers_AWREADY; + wire [7:4]xbar_to_m01_couplers_AWREGION; + wire [5:3]xbar_to_m01_couplers_AWSIZE; + wire [1:1]xbar_to_m01_couplers_AWVALID; + wire [1:1]xbar_to_m01_couplers_BREADY; + wire [1:0]xbar_to_m01_couplers_BRESP; + wire xbar_to_m01_couplers_BVALID; + wire [511:0]xbar_to_m01_couplers_RDATA; + wire xbar_to_m01_couplers_RLAST; + wire [1:1]xbar_to_m01_couplers_RREADY; + wire [1:0]xbar_to_m01_couplers_RRESP; + wire xbar_to_m01_couplers_RVALID; + wire [1023:512]xbar_to_m01_couplers_WDATA; + wire [1:1]xbar_to_m01_couplers_WLAST; + wire xbar_to_m01_couplers_WREADY; + wire [127:64]xbar_to_m01_couplers_WSTRB; + wire [1:1]xbar_to_m01_couplers_WVALID; + wire [191:128]xbar_to_m02_couplers_ARADDR; + wire [5:4]xbar_to_m02_couplers_ARBURST; + wire [11:8]xbar_to_m02_couplers_ARCACHE; + wire [23:16]xbar_to_m02_couplers_ARLEN; + wire [2:2]xbar_to_m02_couplers_ARLOCK; + wire [8:6]xbar_to_m02_couplers_ARPROT; + wire [11:8]xbar_to_m02_couplers_ARQOS; + wire xbar_to_m02_couplers_ARREADY; + wire [11:8]xbar_to_m02_couplers_ARREGION; + wire [8:6]xbar_to_m02_couplers_ARSIZE; + wire [2:2]xbar_to_m02_couplers_ARVALID; + wire [191:128]xbar_to_m02_couplers_AWADDR; + wire [5:4]xbar_to_m02_couplers_AWBURST; + wire [11:8]xbar_to_m02_couplers_AWCACHE; + wire [23:16]xbar_to_m02_couplers_AWLEN; + wire [2:2]xbar_to_m02_couplers_AWLOCK; + wire [8:6]xbar_to_m02_couplers_AWPROT; + wire [11:8]xbar_to_m02_couplers_AWQOS; + wire xbar_to_m02_couplers_AWREADY; + wire [11:8]xbar_to_m02_couplers_AWREGION; + wire [8:6]xbar_to_m02_couplers_AWSIZE; + wire [2:2]xbar_to_m02_couplers_AWVALID; + wire [2:2]xbar_to_m02_couplers_BREADY; + wire [1:0]xbar_to_m02_couplers_BRESP; + wire xbar_to_m02_couplers_BVALID; + wire [511:0]xbar_to_m02_couplers_RDATA; + wire xbar_to_m02_couplers_RLAST; + wire [2:2]xbar_to_m02_couplers_RREADY; + wire [1:0]xbar_to_m02_couplers_RRESP; + wire xbar_to_m02_couplers_RVALID; + wire [1535:1024]xbar_to_m02_couplers_WDATA; + wire [2:2]xbar_to_m02_couplers_WLAST; + wire xbar_to_m02_couplers_WREADY; + wire [191:128]xbar_to_m02_couplers_WSTRB; + wire [2:2]xbar_to_m02_couplers_WVALID; + wire [255:192]xbar_to_m03_couplers_ARADDR; + wire [7:6]xbar_to_m03_couplers_ARBURST; + wire [15:12]xbar_to_m03_couplers_ARCACHE; + wire [31:24]xbar_to_m03_couplers_ARLEN; + wire [3:3]xbar_to_m03_couplers_ARLOCK; + wire [11:9]xbar_to_m03_couplers_ARPROT; + wire [15:12]xbar_to_m03_couplers_ARQOS; + wire xbar_to_m03_couplers_ARREADY; + wire [15:12]xbar_to_m03_couplers_ARREGION; + wire [11:9]xbar_to_m03_couplers_ARSIZE; + wire [3:3]xbar_to_m03_couplers_ARVALID; + wire [255:192]xbar_to_m03_couplers_AWADDR; + wire [7:6]xbar_to_m03_couplers_AWBURST; + wire [15:12]xbar_to_m03_couplers_AWCACHE; + wire [31:24]xbar_to_m03_couplers_AWLEN; + wire [3:3]xbar_to_m03_couplers_AWLOCK; + wire [11:9]xbar_to_m03_couplers_AWPROT; + wire [15:12]xbar_to_m03_couplers_AWQOS; + wire xbar_to_m03_couplers_AWREADY; + wire [15:12]xbar_to_m03_couplers_AWREGION; + wire [11:9]xbar_to_m03_couplers_AWSIZE; + wire [3:3]xbar_to_m03_couplers_AWVALID; + wire [3:3]xbar_to_m03_couplers_BREADY; + wire [1:0]xbar_to_m03_couplers_BRESP; + wire xbar_to_m03_couplers_BVALID; + wire [511:0]xbar_to_m03_couplers_RDATA; + wire xbar_to_m03_couplers_RLAST; + wire [3:3]xbar_to_m03_couplers_RREADY; + wire [1:0]xbar_to_m03_couplers_RRESP; + wire xbar_to_m03_couplers_RVALID; + wire [2047:1536]xbar_to_m03_couplers_WDATA; + wire [3:3]xbar_to_m03_couplers_WLAST; + wire xbar_to_m03_couplers_WREADY; + wire [255:192]xbar_to_m03_couplers_WSTRB; + wire [3:3]xbar_to_m03_couplers_WVALID; + wire [319:256]xbar_to_m04_couplers_ARADDR; + wire [9:8]xbar_to_m04_couplers_ARBURST; + wire [19:16]xbar_to_m04_couplers_ARCACHE; + wire [39:32]xbar_to_m04_couplers_ARLEN; + wire [4:4]xbar_to_m04_couplers_ARLOCK; + wire [14:12]xbar_to_m04_couplers_ARPROT; + wire [19:16]xbar_to_m04_couplers_ARQOS; + wire xbar_to_m04_couplers_ARREADY; + wire [19:16]xbar_to_m04_couplers_ARREGION; + wire [14:12]xbar_to_m04_couplers_ARSIZE; + wire [4:4]xbar_to_m04_couplers_ARVALID; + wire [319:256]xbar_to_m04_couplers_AWADDR; + wire [9:8]xbar_to_m04_couplers_AWBURST; + wire [19:16]xbar_to_m04_couplers_AWCACHE; + wire [39:32]xbar_to_m04_couplers_AWLEN; + wire [4:4]xbar_to_m04_couplers_AWLOCK; + wire [14:12]xbar_to_m04_couplers_AWPROT; + wire [19:16]xbar_to_m04_couplers_AWQOS; + wire xbar_to_m04_couplers_AWREADY; + wire [19:16]xbar_to_m04_couplers_AWREGION; + wire [14:12]xbar_to_m04_couplers_AWSIZE; + wire [4:4]xbar_to_m04_couplers_AWVALID; + wire [4:4]xbar_to_m04_couplers_BREADY; + wire [1:0]xbar_to_m04_couplers_BRESP; + wire xbar_to_m04_couplers_BVALID; + wire [511:0]xbar_to_m04_couplers_RDATA; + wire xbar_to_m04_couplers_RLAST; + wire [4:4]xbar_to_m04_couplers_RREADY; + wire [1:0]xbar_to_m04_couplers_RRESP; + wire xbar_to_m04_couplers_RVALID; + wire [2559:2048]xbar_to_m04_couplers_WDATA; + wire [4:4]xbar_to_m04_couplers_WLAST; + wire xbar_to_m04_couplers_WREADY; + wire [319:256]xbar_to_m04_couplers_WSTRB; + wire [4:4]xbar_to_m04_couplers_WVALID; + + Top_xbar_0 xbar + (.aclk(axi_interconnect_0_ACLK_net), + .aresetn(axi_interconnect_0_ARESETN_net), + .m_axi_araddr({M04_AXI_araddr,M03_AXI_araddr,M02_AXI_araddr,M01_AXI_araddr,M00_AXI_araddr}), + .m_axi_arburst({M04_AXI_arburst,M03_AXI_arburst,M02_AXI_arburst,M01_AXI_arburst,M00_AXI_arburst}), + .m_axi_arcache({M04_AXI_arcache,M03_AXI_arcache,M02_AXI_arcache,M01_AXI_arcache,M00_AXI_arcache}), + .m_axi_arlen({M04_AXI_arlen,M03_AXI_arlen,M02_AXI_arlen,M01_AXI_arlen,M00_AXI_arlen}), + .m_axi_arlock({M04_AXI_arlock,M03_AXI_arlock,M02_AXI_arlock,M01_AXI_arlock,M00_AXI_arlock}), + .m_axi_arprot({M04_AXI_arprot,M03_AXI_arprot,M02_AXI_arprot,M01_AXI_arprot,M00_AXI_arprot}), + .m_axi_arqos({M04_AXI_arqos,M03_AXI_arqos,M02_AXI_arqos,M01_AXI_arqos,M00_AXI_arqos}), + .m_axi_arready({M04_AXI_arready,M03_AXI_arready,M02_AXI_arready,M01_AXI_arready,M00_AXI_arready}), + .m_axi_arregion({M04_AXI_arregion,M03_AXI_arregion,M02_AXI_arregion,M01_AXI_arregion,M00_AXI_arregion}), + .m_axi_arsize({M04_AXI_arsize,M03_AXI_arsize,M02_AXI_arsize,M01_AXI_arsize,M00_AXI_arsize}), + .m_axi_arvalid({M04_AXI_arvalid,M03_AXI_arvalid,M02_AXI_arvalid,M01_AXI_arvalid,M00_AXI_arvalid}), + .m_axi_awaddr({M04_AXI_awaddr,M03_AXI_awaddr,M02_AXI_awaddr,M01_AXI_awaddr,M00_AXI_awaddr}), + .m_axi_awburst({M04_AXI_awburst,M03_AXI_awburst,M02_AXI_awburst,M01_AXI_awburst,M00_AXI_awburst}), + .m_axi_awcache({M04_AXI_awcache,M03_AXI_awcache,M02_AXI_awcache,M01_AXI_awcache,M00_AXI_awcache}), + .m_axi_awlen({M04_AXI_awlen,M03_AXI_awlen,M02_AXI_awlen,M01_AXI_awlen,M00_AXI_awlen}), + .m_axi_awlock({M04_AXI_awlock,M03_AXI_awlock,M02_AXI_awlock,M01_AXI_awlock,M00_AXI_awlock}), + .m_axi_awprot({M04_AXI_awprot,M03_AXI_awprot,M02_AXI_awprot,M01_AXI_awprot,M00_AXI_awprot}), + .m_axi_awqos({M04_AXI_awqos,M03_AXI_awqos,M02_AXI_awqos,M01_AXI_awqos,M00_AXI_awqos}), + .m_axi_awready({M04_AXI_awready,M03_AXI_awready,M02_AXI_awready,M01_AXI_awready,M00_AXI_awready}), + .m_axi_awregion({M04_AXI_awregion,M03_AXI_awregion,M02_AXI_awregion,M01_AXI_awregion,M00_AXI_awregion}), + .m_axi_awsize({M04_AXI_awsize,M03_AXI_awsize,M02_AXI_awsize,M01_AXI_awsize,M00_AXI_awsize}), + .m_axi_awvalid({M04_AXI_awvalid,M03_AXI_awvalid,M02_AXI_awvalid,M01_AXI_awvalid,M00_AXI_awvalid}), + .m_axi_bready({M04_AXI_bready,M03_AXI_bready,M02_AXI_bready,M01_AXI_bready,M00_AXI_bready}), + .m_axi_bresp({M04_AXI_bresp,M03_AXI_bresp,M02_AXI_bresp,M01_AXI_bresp,M00_AXI_bresp}), + .m_axi_bvalid({M04_AXI_bvalid,M03_AXI_bvalid,M02_AXI_bvalid,M01_AXI_bvalid,M00_AXI_bvalid}), + .m_axi_rdata({M04_AXI_rdata,M03_AXI_rdata,M02_AXI_rdata,M01_AXI_rdata,M00_AXI_rdata}), + .m_axi_rlast({M04_AXI_rlast,M03_AXI_rlast,M02_AXI_rlast,M01_AXI_rlast,M00_AXI_rlast}), + .m_axi_rready({M04_AXI_rready,M03_AXI_rready,M02_AXI_rready,M01_AXI_rready,M00_AXI_rready}), + .m_axi_rresp({M04_AXI_rresp,M03_AXI_rresp,M02_AXI_rresp,M01_AXI_rresp,M00_AXI_rresp}), + .m_axi_rvalid({M04_AXI_rvalid,M03_AXI_rvalid,M02_AXI_rvalid,M01_AXI_rvalid,M00_AXI_rvalid}), + .m_axi_wdata({M04_AXI_wdata,M03_AXI_wdata,M02_AXI_wdata,M01_AXI_wdata,M00_AXI_wdata}), + .m_axi_wlast({M04_AXI_wlast,M03_AXI_wlast,M02_AXI_wlast,M01_AXI_wlast,M00_AXI_wlast}), + .m_axi_wready({M04_AXI_wready,M03_AXI_wready,M02_AXI_wready,M01_AXI_wready,M00_AXI_wready}), + .m_axi_wstrb({M04_AXI_wstrb,M03_AXI_wstrb,M02_AXI_wstrb,M01_AXI_wstrb,M00_AXI_wstrb}), + .m_axi_wvalid({M04_AXI_wvalid,M03_AXI_wvalid,M02_AXI_wvalid,M01_AXI_wvalid,M00_AXI_wvalid}), + .s_axi_araddr(S00_AXI_araddr), + .s_axi_arburst(S00_AXI_arburst), + .s_axi_arcache(S00_AXI_arcache), + .s_axi_arlen(S00_AXI_arlen), + .s_axi_arlock(S00_AXI_arlock), + .s_axi_arprot(S00_AXI_arprot), + .s_axi_arqos(S00_AXI_arqos), + .s_axi_arready(S00_AXI_arready), + .s_axi_arsize(S00_AXI_arsize), + .s_axi_arvalid(S00_AXI_arvalid), + .s_axi_awaddr(S00_AXI_awaddr), + .s_axi_awburst(S00_AXI_awburst), + .s_axi_awcache(S00_AXI_awcache), + .s_axi_awlen(S00_AXI_awlen), + .s_axi_awlock(S00_AXI_awlock), + .s_axi_awprot(S00_AXI_awprot), + .s_axi_awqos(S00_AXI_awqos), + .s_axi_awready(S00_AXI_awready), + .s_axi_awsize(S00_AXI_awsize), + .s_axi_awvalid(S00_AXI_awvalid), + .s_axi_bready(S00_AXI_bready), + .s_axi_bresp(S00_AXI_bresp), + .s_axi_bvalid(S00_AXI_bvalid), + .s_axi_rdata(S00_AXI_rdata), + .s_axi_rlast(S00_AXI_rlast), + .s_axi_rready(S00_AXI_rready), + .s_axi_rresp(S00_AXI_rresp), + .s_axi_rvalid(S00_AXI_rvalid), + .s_axi_wdata(S00_AXI_wdata), + .s_axi_wlast(S00_AXI_wlast), + .s_axi_wready(S00_AXI_wready), + .s_axi_wstrb(S00_AXI_wstrb), + .s_axi_wvalid(S00_AXI_wvalid)); + +endmodule diff --git a/nitefury_pcie_xdma_ddr/project/sources/Top_wrapper.v b/nitefury_pcie_xdma_ddr/project/sources/Top_wrapper.v deleted file mode 100644 index b318c09..0000000 --- a/nitefury_pcie_xdma_ddr/project/sources/Top_wrapper.v +++ /dev/null @@ -1,196 +0,0 @@ -//Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. -//-------------------------------------------------------------------------------- -//Tool Version: Vivado v.2018.3 (win64) Build 2405991 Thu Dec 6 23:38:27 MST 2018 -//Date : Wed Apr 24 10:52:27 2019 -//Host : dr-lt2 running 64-bit major release (build 9200) -//Command : generate_target Top_wrapper.bd -//Design : Top_wrapper -//Purpose : IP block netlist -//-------------------------------------------------------------------------------- -`timescale 1 ps / 1 ps - -module Top_wrapper - (DDR3_addr, - DDR3_ba, - DDR3_cas_n, - DDR3_ck_n, - DDR3_ck_p, - DDR3_cke, - DDR3_dm, - DDR3_dq, - DDR3_dqs_n, - DDR3_dqs_p, - DDR3_odt, - DDR3_ras_n, - DDR3_reset_n, - DDR3_we_n, - LED_A1, - LED_A2, - LED_A3, - LED_A4, - SPI_0_io0_io, - SPI_0_io1_io, - SPI_0_io2_io, - SPI_0_io3_io, - SPI_0_ss_i, - SPI_0_ss_t, - pci_reset, - pcie_clkin_clk_n, - pcie_clkin_clk_p, - pcie_clkreq_l, - pcie_mgt_rxn, - pcie_mgt_rxp, - pcie_mgt_txn, - pcie_mgt_txp, - real_spi_ss, - sys_clk_clk_n, - sys_clk_clk_p); - output [14:0]DDR3_addr; - output [2:0]DDR3_ba; - output DDR3_cas_n; - output [0:0]DDR3_ck_n; - output [0:0]DDR3_ck_p; - output [0:0]DDR3_cke; - output [1:0]DDR3_dm; - inout [15:0]DDR3_dq; - inout [1:0]DDR3_dqs_n; - inout [1:0]DDR3_dqs_p; - output [0:0]DDR3_odt; - output DDR3_ras_n; - output DDR3_reset_n; - output DDR3_we_n; - output [0:0]LED_A1; - output [0:0]LED_A2; - output [0:0]LED_A3; - output [0:0]LED_A4; - inout SPI_0_io0_io; - inout SPI_0_io1_io; - inout SPI_0_io2_io; - inout SPI_0_io3_io; - input [0:0]SPI_0_ss_i; - output SPI_0_ss_t; - input pci_reset; - input [0:0]pcie_clkin_clk_n; - input [0:0]pcie_clkin_clk_p; - output [0:0]pcie_clkreq_l; - input [3:0]pcie_mgt_rxn; - input [3:0]pcie_mgt_rxp; - output [3:0]pcie_mgt_txn; - output [3:0]pcie_mgt_txp; - output [0:0]real_spi_ss; - input sys_clk_clk_n; - input sys_clk_clk_p; - - wire [14:0]DDR3_addr; - wire [2:0]DDR3_ba; - wire DDR3_cas_n; - wire [0:0]DDR3_ck_n; - wire [0:0]DDR3_ck_p; - wire [0:0]DDR3_cke; - wire [1:0]DDR3_dm; - wire [15:0]DDR3_dq; - wire [1:0]DDR3_dqs_n; - wire [1:0]DDR3_dqs_p; - wire [0:0]DDR3_odt; - wire DDR3_ras_n; - wire DDR3_reset_n; - wire DDR3_we_n; - wire [0:0]LED_A1; - wire [0:0]LED_A2; - wire [0:0]LED_A3; - wire [0:0]LED_A4; - wire SPI_0_io0_i; - wire SPI_0_io0_io; - wire SPI_0_io0_o; - wire SPI_0_io0_t; - wire SPI_0_io1_i; - wire SPI_0_io1_io; - wire SPI_0_io1_o; - wire SPI_0_io1_t; - wire SPI_0_io2_i; - wire SPI_0_io2_io; - wire SPI_0_io2_o; - wire SPI_0_io2_t; - wire SPI_0_io3_i; - wire SPI_0_io3_io; - wire SPI_0_io3_o; - wire SPI_0_io3_t; - wire [0:0]SPI_0_ss_i; - wire SPI_0_ss_t; - wire pci_reset; - wire [0:0]pcie_clkin_clk_n; - wire [0:0]pcie_clkin_clk_p; - wire [0:0]pcie_clkreq_l; - wire [3:0]pcie_mgt_rxn; - wire [3:0]pcie_mgt_rxp; - wire [3:0]pcie_mgt_txn; - wire [3:0]pcie_mgt_txp; - wire [0:0]real_spi_ss; - wire sys_clk_clk_n; - wire sys_clk_clk_p; - - IOBUF SPI_0_io0_iobuf - (.I(SPI_0_io0_o), - .IO(SPI_0_io0_io), - .O(SPI_0_io0_i), - .T(SPI_0_io0_t)); - IOBUF SPI_0_io1_iobuf - (.I(SPI_0_io1_o), - .IO(SPI_0_io1_io), - .O(SPI_0_io1_i), - .T(SPI_0_io1_t)); - IOBUF SPI_0_io2_iobuf - (.I(SPI_0_io2_o), - .IO(SPI_0_io2_io), - .O(SPI_0_io2_i), - .T(SPI_0_io2_t)); - IOBUF SPI_0_io3_iobuf - (.I(SPI_0_io3_o), - .IO(SPI_0_io3_io), - .O(SPI_0_io3_i), - .T(SPI_0_io3_t)); - Top Top_i - (.DDR3_addr(DDR3_addr), - .DDR3_ba(DDR3_ba), - .DDR3_cas_n(DDR3_cas_n), - .DDR3_ck_n(DDR3_ck_n), - .DDR3_ck_p(DDR3_ck_p), - .DDR3_cke(DDR3_cke), - .DDR3_dm(DDR3_dm), - .DDR3_dq(DDR3_dq), - .DDR3_dqs_n(DDR3_dqs_n), - .DDR3_dqs_p(DDR3_dqs_p), - .DDR3_odt(DDR3_odt), - .DDR3_ras_n(DDR3_ras_n), - .DDR3_reset_n(DDR3_reset_n), - .DDR3_we_n(DDR3_we_n), - .LED_A1(LED_A1), - .LED_A2(LED_A2), - .LED_A3(LED_A3), - .LED_A4(LED_A4), - .SPI_0_io0_i(SPI_0_io0_i), - .SPI_0_io0_o(SPI_0_io0_o), - .SPI_0_io0_t(SPI_0_io0_t), - .SPI_0_io1_i(SPI_0_io1_i), - .SPI_0_io1_o(SPI_0_io1_o), - .SPI_0_io1_t(SPI_0_io1_t), - .SPI_0_io2_i(SPI_0_io2_i), - .SPI_0_io2_o(SPI_0_io2_o), - .SPI_0_io2_t(SPI_0_io2_t), - .SPI_0_io3_i(SPI_0_io3_i), - .SPI_0_io3_o(SPI_0_io3_o), - .SPI_0_io3_t(SPI_0_io3_t), - .SPI_0_ss_i(SPI_0_ss_i), - .SPI_0_ss_t(SPI_0_ss_t), - .pci_reset(pci_reset), - .pcie_clkin_clk_n(pcie_clkin_clk_n), - .pcie_clkin_clk_p(pcie_clkin_clk_p), - .pcie_clkreq_l(pcie_clkreq_l), - .pcie_mgt_rxn(pcie_mgt_rxn), - .pcie_mgt_rxp(pcie_mgt_rxp), - .pcie_mgt_txn(pcie_mgt_txn), - .pcie_mgt_txp(pcie_mgt_txp), - .real_spi_ss(real_spi_ss), - .sys_clk_clk_n(sys_clk_clk_n), - .sys_clk_clk_p(sys_clk_clk_p)); -endmodule