diff --git a/nitefury_pcie_xdma_ddr/project/o.tcl b/nitefury_pcie_xdma_ddr/project/o.tcl index e5deaf9..3a9a8ab 100644 --- a/nitefury_pcie_xdma_ddr/project/o.tcl +++ b/nitefury_pcie_xdma_ddr/project/o.tcl @@ -5,107 +5,96 @@ set_property SOURCE_MGMT_MODE None [current_project] set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1] set_property PART xc7k480tffg1156-2L [current_project] +set_param general.maxThreads 16 -# # 生成IP核（以AXI UART Lite为例） -# create_ip -name axi_uartlite -vendor xilinx.com -library ip -version 2.0 -module_name uart_inst -# # 配置IP参数 -# set_property -dict [list \ -# CONFIG.C_BAUDRATE {115200} \ -# CONFIG.C_S_AXI_ACLK_FREQ_HZ {100000000} \ -# CONFIG.C_DATA_BITS {8} \ -# CONFIG.C_USE_PARITY {0} \ -# ] [get_ips uart_inst] create_ip -name axi_interconnect -vendor xilinx.com -library ip -version 1.7 -module_name axi_interconnect_0 +set_property -dict [list \ + CONFIG.NUM_SLAVE_PORTS {5} \ +] [get_ips axi_interconnect_0] generate_target -force all [get_ips axi_interconnect_0] synth_ip [get_ips axi_interconnect_0] -# add_file ../uart_inst.xci -# import_ip ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci -# import_ip ../sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci -# import_ip ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci -import_ip ../sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci - -# upgrade_ip [get_ips Top_axi_interconnect_0_0] -# # set_property GENERATE_SYNTH_CHECKPOINT true Top_axi_interconnect_0_0 -# generate_target -force all [get_ips Top_axi_interconnect_0_0] -# synth_ip [get_ips Top_axi_interconnect_0_0] +import_ip ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci +import_ip ../sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci +import_ip ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci +# import_ip ../sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci +import_ip ../sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci +import_ip ../sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci +import_ip ../sources/ip/Top_xbar_0/Top_xbar_0.xci +import_ip ../sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci +import_ip ../sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci +import_ip ../sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci +import_ip ../sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci -# import_ip ../sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci -# import_ip ../sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci -# import_ip ../sources/ip/Top_xbar_0/Top_xbar_0.xci -# import_ip ../sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci -# import_ip ../sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci -# import_ip ../sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci -# import_ip ../sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci - -# generate_target all [get_ips Top_axi_bram_ctrl_0_0] -# generate_target all [get_ips Top_util_vector_logic_1_3] -# generate_target all [get_ips Top_xlconstant_2_0] +generate_target all [get_ips Top_axi_bram_ctrl_0_0] +generate_target all [get_ips Top_util_vector_logic_1_3] +generate_target all [get_ips Top_xlconstant_2_0] # generate_target all [get_ips Top_axi_interconnect_0_0] -# generate_target all [get_ips Top_util_vector_logic_1_4] -# generate_target all [get_ips Top_blk_mem_gen_0_0] -# generate_target all [get_ips Top_xbar_0] -# generate_target all [get_ips Top_mig_7series_1_0] -# generate_target all [get_ips Top_xdma_1_0] -# generate_target all [get_ips Top_util_ds_buf_0_0] -# generate_target all [get_ips Top_xlconstant_0_0] +generate_target all [get_ips Top_util_vector_logic_1_4] +generate_target all [get_ips Top_blk_mem_gen_0_0] +generate_target all [get_ips Top_xbar_0] +generate_target all [get_ips Top_xdma_1_0] +generate_target all [get_ips Top_util_ds_buf_0_0] +generate_target all [get_ips Top_xlconstant_0_0] +generate_target all [get_ips Top_mig_7series_1_0] -# synth_ip [get_ips Top_axi_bram_ctrl_0_0] -# synth_ip [get_ips Top_util_vector_logic_1_3] -# synth_ip [get_ips Top_xlconstant_2_0] +synth_ip [get_ips Top_axi_bram_ctrl_0_0] +synth_ip [get_ips Top_util_vector_logic_1_3] +synth_ip [get_ips Top_xlconstant_2_0] # synth_ip [get_ips Top_axi_interconnect_0_0] -# synth_ip [get_ips Top_util_vector_logic_1_4] -# synth_ip [get_ips Top_blk_mem_gen_0_0] -# synth_ip [get_ips Top_xbar_0] -# synth_ip [get_ips Top_mig_7series_1_0] -# synth_ip [get_ips Top_xdma_1_0] -# synth_ip [get_ips Top_util_ds_buf_0_0] -# synth_ip [get_ips Top_xlconstant_0_0] +synth_ip [get_ips Top_util_vector_logic_1_4] +synth_ip [get_ips Top_blk_mem_gen_0_0] +synth_ip [get_ips Top_xbar_0] +synth_ip [get_ips Top_xdma_1_0] +synth_ip [get_ips Top_util_ds_buf_0_0] +synth_ip [get_ips Top_xlconstant_0_0] +synth_ip [get_ips Top_mig_7series_1_0] -# add_file ../sources/Top_wrapper.v +add_file ../sources/Top_wrapper.v +add_file ../sources/Top.v # add_file ../sources/Top.bd -# add_file -fileset constrs_1 ../normal.xdc +add_file -fileset constrs_1 ../normal.xdc -# set_property TOP Top_wrapper [current_fileset] +set_property TOP Top_wrapper [current_fileset] -# set_property GENERIC { FREQ=100000000 SECS=1 } -objects [get_filesets sources_1] +set_property GENERIC { FREQ=100000000 SECS=1 } -objects [get_filesets sources_1] -# close_project +close_project -# open_project my_project +open_project my_project -# # Synthesis +# Synthesis -# # PRESYNTH -# # set_property DESIGN_MODE GateLvl [current_fileset] -# reset_run synth_1 -# launch_runs synth_1 -# wait_on_run synth_1 -# #report_property [get_runs synth_1] -# if { [get_property STATUS [get_runs synth_1]] ne "synth_design Complete!" } { exit 1 } +# PRESYNTH +# set_property DESIGN_MODE GateLvl [current_fileset] +reset_run synth_1 +launch_runs synth_1 -jobs 16 +wait_on_run synth_1 +#report_property [get_runs synth_1] +if { [get_property STATUS [get_runs synth_1]] ne "synth_design Complete!" } { exit 1 } -# # Place and Route +# Place and Route -# reset_run impl_1 -# launch_runs impl_1 -# wait_on_run impl_1 -# #report_property [get_runs impl_1] -# if { [get_property STATUS [get_runs impl_1]] ne "route_design Complete!" } { exit 1 } +reset_run impl_1 +launch_runs impl_1 -jobs 16 +wait_on_run impl_1 +#report_property [get_runs impl_1] +if { [get_property STATUS [get_runs impl_1]] ne "route_design Complete!" } { exit 1 } -# # Bitstream generation +# Bitstream generation -# open_run impl_1 -# # write_bitstream -force xdma480t -# # write_debug_probes -force -quiet xdma480t.ltx +open_run impl_1 +# write_bitstream -force xdma480t +# write_debug_probes -force -quiet xdma480t.ltx -# close_project +close_project diff --git a/nitefury_pcie_xdma_ddr/project/sources/Top.bd b/nitefury_pcie_xdma_ddr/project/sources/Top.bd index 6f0a9b0..ff139be 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/Top.bd +++ b/nitefury_pcie_xdma_ddr/project/sources/Top.bd @@ -3,7 +3,7 @@ "design_info": { "boundary_crc": "0x8F1AA258A84BB33F", "device": "xc7k480tffg1156-2L", - "gen_directory": "../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top", + "gen_directory": "../../../build/my_project.gen/sources_1", "name": "Top", "rev_ctrl_bd_flag": "RevCtrlBdOff", "synth_flow_mode": "Hierarchical", @@ -444,8 +444,8 @@ "components": { "xdma_1": { "vlnv": "xilinx.com:ip:xdma:4.1", - "xci_name": "Top_xdma_1_0", - "xci_path": "ip/Top_xdma_1_0/Top_xdma_1_0.xci", + "xci_name": "Top_xdma_1_1", + "xci_path": "ip/Top_xdma_1_1/Top_xdma_1_1.xci", "inst_hier_path": "xdma_1", "parameters": { "pl_link_cap_max_link_speed": { @@ -1605,9 +1605,6 @@ "BOARD_MIG_PARAM": { "value": "Custom" }, - "MIG_DONT_TOUCH_PARAM": { - "value": "Custom" - }, "RESET_BOARD_INTERFACE": { "value": "Custom" }, @@ -1629,8 +1626,8 @@ }, "xlconstant_0": { "vlnv": "xilinx.com:ip:xlconstant:1.1", - "xci_name": "Top_xlconstant_0_0", - "xci_path": "ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci", + "xci_name": "Top_xlconstant_0_1", + "xci_path": "ip/Top_xlconstant_0_1/Top_xlconstant_0_1.xci", "inst_hier_path": "xlconstant_0" }, "xlconstant_2": { diff --git a/nitefury_pcie_xdma_ddr/project/sources/Top.bda b/nitefury_pcie_xdma_ddr/project/sources/Top.bda index 7d3c147..303a37e 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/Top.bda +++ b/nitefury_pcie_xdma_ddr/project/sources/Top.bda @@ -23,6 +23,44 @@ + 0x0000000100100000 + C_BASEADDR + 0x00000001001FFFFF + C_HIGHADDR + M_AXI + /xdma_1 + M_AXI + SEG_mig_7series_1_c1_s_axi_ctrl_memaddr + xilinx.com:ip:xdma:4.1 + both + /mig_7series_1 + S1_AXI_CTRL + c1_s_axi_ctrl_memmap + c1_s_axi_ctrl_memaddr + xilinx.com:ip:mig_7series:4.2 + register + AC + + + 0x0000000000000000 + C_BASEADDR + 0x000000007FFFFFFF + C_HIGHADDR + M_AXI + /xdma_1 + M_AXI + SEG_mig_7series_1_c1_memaddr + xilinx.com:ip:xdma:4.1 + both + /mig_7series_1 + S1_AXI + c1_memmap + c1_memaddr + xilinx.com:ip:mig_7series:4.2 + memory + AC + + 0x0000000200000000 C_S_AXI_BASEADDR 0x0000000200001FFF @@ -40,23 +78,73 @@ memory AC - + Top BC - - active - 2 - PM - - + 2 Top VR - - - + + 0x0000000080000000 + C_BASEADDR + 0x00000000FFFFFFFF + C_HIGHADDR + M_AXI + /xdma_1 + M_AXI + SEG_mig_7series_1_c0_memaddr + xilinx.com:ip:xdma:4.1 + both + /mig_7series_1 + S0_AXI + c0_memmap + c0_memaddr + xilinx.com:ip:mig_7series:4.2 + memory + AC + + + 0x0000000100000000 + C_BASEADDR + 0x00000001000FFFFF + C_HIGHADDR + M_AXI + /xdma_1 + M_AXI + SEG_mig_7series_1_c0_s_axi_ctrl_memaddr + xilinx.com:ip:xdma:4.1 + both + /mig_7series_1 + S0_AXI_CTRL + c0_s_axi_ctrl_memmap + c0_s_axi_ctrl_memaddr + xilinx.com:ip:mig_7series:4.2 + register + AC + + + active + 2 + PM + + + + + 2 + + + 2 + + + 2 + + + 2 + + 2 diff --git a/nitefury_pcie_xdma_ddr/project/sources/Top.v b/nitefury_pcie_xdma_ddr/project/sources/Top.v new file mode 100644 index 0000000..3fac69a --- /dev/null +++ b/nitefury_pcie_xdma_ddr/project/sources/Top.v @@ -0,0 +1,788 @@ +//Copyright 1986-2022 Xilinx, Inc. All Rights Reserved. +//-------------------------------------------------------------------------------- +//Tool Version: Vivado v.2022.2 (lin64) Build 3671981 Fri Oct 14 04:59:54 MDT 2022 +//Date : Mon May 12 00:48:27 2025 +//Host : deve running 64-bit Ubuntu 22.04.5 LTS +//Command : generate_target Top.bd +//Design : Top +//Purpose : IP block netlist +//-------------------------------------------------------------------------------- +`timescale 1 ps / 1 ps + +(* CORE_GENERATION_INFO = "Top,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=Top,x_ipVersion=1.00.a,x_ipLanguage=VERILOG,numBlks=27,numReposBlks=20,numNonXlnxBlks=0,numHierBlks=7,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,synth_mode=OOC_per_IP}" *) (* HW_HANDOFF = "Top.hwdef" *) +module Top + (C0_DDR3_0_addr, + C0_DDR3_0_ba, + C0_DDR3_0_cas_n, + C0_DDR3_0_ck_n, + C0_DDR3_0_ck_p, + C0_DDR3_0_cke, + C0_DDR3_0_cs_n, + C0_DDR3_0_dq, + C0_DDR3_0_dqs_n, + C0_DDR3_0_dqs_p, + C0_DDR3_0_odt, + C0_DDR3_0_ras_n, + C0_DDR3_0_reset_n, + C0_DDR3_0_we_n, + C0_SYS_CLK_0_clk_n, + C0_SYS_CLK_0_clk_p, + C1_DDR3_0_addr, + C1_DDR3_0_ba, + C1_DDR3_0_cas_n, + C1_DDR3_0_ck_n, + C1_DDR3_0_ck_p, + C1_DDR3_0_cke, + C1_DDR3_0_cs_n, + C1_DDR3_0_dq, + C1_DDR3_0_dqs_n, + C1_DDR3_0_dqs_p, + C1_DDR3_0_odt, + C1_DDR3_0_ras_n, + C1_DDR3_0_reset_n, + C1_DDR3_0_we_n, + C1_SYS_CLK_0_clk_n, + C1_SYS_CLK_0_clk_p, + pci_reset, + pcie_clkin_clk_n, + pcie_clkin_clk_p, + pcie_mgt_0_rxn, + pcie_mgt_0_rxp, + pcie_mgt_0_txn, + pcie_mgt_0_txp, + user_lnk_up_0); + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME C0_DDR3_0, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) output [14:0]C0_DDR3_0_addr; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 BA" *) output [2:0]C0_DDR3_0_ba; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CAS_N" *) output C0_DDR3_0_cas_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CK_N" *) output [0:0]C0_DDR3_0_ck_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CK_P" *) output [0:0]C0_DDR3_0_ck_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CKE" *) output [0:0]C0_DDR3_0_cke; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 CS_N" *) output [0:0]C0_DDR3_0_cs_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 DQ" *) inout [71:0]C0_DDR3_0_dq; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 DQS_N" *) inout [8:0]C0_DDR3_0_dqs_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 DQS_P" *) inout [8:0]C0_DDR3_0_dqs_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 ODT" *) output [0:0]C0_DDR3_0_odt; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 RAS_N" *) output C0_DDR3_0_ras_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 RESET_N" *) output C0_DDR3_0_reset_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C0_DDR3_0 WE_N" *) output C0_DDR3_0_we_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 C0_SYS_CLK_0 CLK_N" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME C0_SYS_CLK_0, CAN_DEBUG false, FREQ_HZ 100000000" *) input C0_SYS_CLK_0_clk_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 C0_SYS_CLK_0 CLK_P" *) input C0_SYS_CLK_0_clk_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 ADDR" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME C1_DDR3_0, AXI_ARBITRATION_SCHEME TDM, BURST_LENGTH 8, CAN_DEBUG false, CAS_LATENCY 11, CAS_WRITE_LATENCY 11, CS_ENABLED true, DATA_MASK_ENABLED true, DATA_WIDTH 8, MEMORY_TYPE COMPONENTS, MEM_ADDR_MAP ROW_COLUMN_BANK, SLOT Single, TIMEPERIOD_PS 1250" *) output [14:0]C1_DDR3_0_addr; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 BA" *) output [2:0]C1_DDR3_0_ba; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CAS_N" *) output C1_DDR3_0_cas_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CK_N" *) output [0:0]C1_DDR3_0_ck_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CK_P" *) output [0:0]C1_DDR3_0_ck_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CKE" *) output [0:0]C1_DDR3_0_cke; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 CS_N" *) output [0:0]C1_DDR3_0_cs_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 DQ" *) inout [71:0]C1_DDR3_0_dq; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 DQS_N" *) inout [8:0]C1_DDR3_0_dqs_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 DQS_P" *) inout [8:0]C1_DDR3_0_dqs_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 ODT" *) output [0:0]C1_DDR3_0_odt; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 RAS_N" *) output C1_DDR3_0_ras_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 RESET_N" *) output C1_DDR3_0_reset_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:ddrx:1.0 C1_DDR3_0 WE_N" *) output C1_DDR3_0_we_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 C1_SYS_CLK_0 CLK_N" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME C1_SYS_CLK_0, CAN_DEBUG false, FREQ_HZ 100000000" *) input C1_SYS_CLK_0_clk_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 C1_SYS_CLK_0 CLK_P" *) input C1_SYS_CLK_0_clk_p; + (* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST.PCI_RESET RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST.PCI_RESET, INSERT_VIP 0, POLARITY ACTIVE_LOW" *) input pci_reset; + (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 pcie_clkin CLK_N" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME pcie_clkin, CAN_DEBUG false, FREQ_HZ 100000000" *) input [0:0]pcie_clkin_clk_n; + (* X_INTERFACE_INFO = "xilinx.com:interface:diff_clock:1.0 pcie_clkin CLK_P" *) input [0:0]pcie_clkin_clk_p; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 rxn" *) input [0:0]pcie_mgt_0_rxn; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 rxp" *) input [0:0]pcie_mgt_0_rxp; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 txn" *) output [0:0]pcie_mgt_0_txn; + (* X_INTERFACE_INFO = "xilinx.com:interface:pcie_7x_mgt:1.0 pcie_mgt_0 txp" *) output [0:0]pcie_mgt_0_txp; + output user_lnk_up_0; + + wire C0_SYS_CLK_0_1_CLK_N; + wire C0_SYS_CLK_0_1_CLK_P; + wire C1_SYS_CLK_0_1_CLK_N; + wire C1_SYS_CLK_0_1_CLK_P; + wire [7:0]M00_ARESETN_2; + wire [63:0]S00_AXI_1_ARADDR; + wire [1:0]S00_AXI_1_ARBURST; + wire [3:0]S00_AXI_1_ARCACHE; + wire [3:0]S00_AXI_1_ARID; + wire [7:0]S00_AXI_1_ARLEN; + wire S00_AXI_1_ARLOCK; + wire [2:0]S00_AXI_1_ARPROT; + wire S00_AXI_1_ARREADY; + wire [2:0]S00_AXI_1_ARSIZE; + wire S00_AXI_1_ARVALID; + wire [63:0]S00_AXI_1_AWADDR; + wire [1:0]S00_AXI_1_AWBURST; + wire [3:0]S00_AXI_1_AWCACHE; + wire [3:0]S00_AXI_1_AWID; + wire [7:0]S00_AXI_1_AWLEN; + wire S00_AXI_1_AWLOCK; + wire [2:0]S00_AXI_1_AWPROT; + wire S00_AXI_1_AWREADY; + wire [2:0]S00_AXI_1_AWSIZE; + wire S00_AXI_1_AWVALID; + wire [3:0]S00_AXI_1_BID; + wire S00_AXI_1_BREADY; + wire [1:0]S00_AXI_1_BRESP; + wire S00_AXI_1_BVALID; + wire [63:0]S00_AXI_1_RDATA; + wire [3:0]S00_AXI_1_RID; + wire S00_AXI_1_RLAST; + wire S00_AXI_1_RREADY; + wire [1:0]S00_AXI_1_RRESP; + wire S00_AXI_1_RVALID; + wire [63:0]S00_AXI_1_WDATA; + wire S00_AXI_1_WLAST; + wire S00_AXI_1_WREADY; + wire [7:0]S00_AXI_1_WSTRB; + wire S00_AXI_1_WVALID; + wire [12:0]axi_bram_ctrl_0_BRAM_PORTA_ADDR; + wire axi_bram_ctrl_0_BRAM_PORTA_CLK; + wire [31:0]axi_bram_ctrl_0_BRAM_PORTA_DIN; + wire [31:0]axi_bram_ctrl_0_BRAM_PORTA_DOUT; + wire axi_bram_ctrl_0_BRAM_PORTA_EN; + wire axi_bram_ctrl_0_BRAM_PORTA_RST; + wire [3:0]axi_bram_ctrl_0_BRAM_PORTA_WE; + wire [31:0]axi_interconnect_0_M00_AXI_ARADDR; + wire axi_interconnect_0_M00_AXI_ARREADY; + wire axi_interconnect_0_M00_AXI_ARVALID; + wire [31:0]axi_interconnect_0_M00_AXI_AWADDR; + wire axi_interconnect_0_M00_AXI_AWREADY; + wire axi_interconnect_0_M00_AXI_AWVALID; + wire axi_interconnect_0_M00_AXI_BREADY; + wire [1:0]axi_interconnect_0_M00_AXI_BRESP; + wire axi_interconnect_0_M00_AXI_BVALID; + wire [31:0]axi_interconnect_0_M00_AXI_RDATA; + wire axi_interconnect_0_M00_AXI_RREADY; + wire [1:0]axi_interconnect_0_M00_AXI_RRESP; + wire axi_interconnect_0_M00_AXI_RVALID; + wire [31:0]axi_interconnect_0_M00_AXI_WDATA; + wire axi_interconnect_0_M00_AXI_WREADY; + wire axi_interconnect_0_M00_AXI_WVALID; + wire [30:0]axi_interconnect_0_M01_AXI_ARADDR; + wire [1:0]axi_interconnect_0_M01_AXI_ARBURST; + wire [3:0]axi_interconnect_0_M01_AXI_ARCACHE; + wire [7:0]axi_interconnect_0_M01_AXI_ARLEN; + wire axi_interconnect_0_M01_AXI_ARLOCK; + wire [2:0]axi_interconnect_0_M01_AXI_ARPROT; + wire [3:0]axi_interconnect_0_M01_AXI_ARQOS; + wire axi_interconnect_0_M01_AXI_ARREADY; + wire [2:0]axi_interconnect_0_M01_AXI_ARSIZE; + wire axi_interconnect_0_M01_AXI_ARVALID; + wire [30:0]axi_interconnect_0_M01_AXI_AWADDR; + wire [1:0]axi_interconnect_0_M01_AXI_AWBURST; + wire [3:0]axi_interconnect_0_M01_AXI_AWCACHE; + wire [7:0]axi_interconnect_0_M01_AXI_AWLEN; + wire axi_interconnect_0_M01_AXI_AWLOCK; + wire [2:0]axi_interconnect_0_M01_AXI_AWPROT; + wire [3:0]axi_interconnect_0_M01_AXI_AWQOS; + wire axi_interconnect_0_M01_AXI_AWREADY; + wire [2:0]axi_interconnect_0_M01_AXI_AWSIZE; + wire axi_interconnect_0_M01_AXI_AWVALID; + wire axi_interconnect_0_M01_AXI_BREADY; + wire [1:0]axi_interconnect_0_M01_AXI_BRESP; + wire axi_interconnect_0_M01_AXI_BVALID; + wire [511:0]axi_interconnect_0_M01_AXI_RDATA; + wire axi_interconnect_0_M01_AXI_RLAST; + wire axi_interconnect_0_M01_AXI_RREADY; + wire [1:0]axi_interconnect_0_M01_AXI_RRESP; + wire axi_interconnect_0_M01_AXI_RVALID; + wire [511:0]axi_interconnect_0_M01_AXI_WDATA; + wire axi_interconnect_0_M01_AXI_WLAST; + wire axi_interconnect_0_M01_AXI_WREADY; + wire [63:0]axi_interconnect_0_M01_AXI_WSTRB; + wire axi_interconnect_0_M01_AXI_WVALID; + wire [31:0]axi_interconnect_0_M02_AXI_ARADDR; + wire axi_interconnect_0_M02_AXI_ARREADY; + wire axi_interconnect_0_M02_AXI_ARVALID; + wire [31:0]axi_interconnect_0_M02_AXI_AWADDR; + wire axi_interconnect_0_M02_AXI_AWREADY; + wire axi_interconnect_0_M02_AXI_AWVALID; + wire axi_interconnect_0_M02_AXI_BREADY; + wire [1:0]axi_interconnect_0_M02_AXI_BRESP; + wire axi_interconnect_0_M02_AXI_BVALID; + wire [31:0]axi_interconnect_0_M02_AXI_RDATA; + wire axi_interconnect_0_M02_AXI_RREADY; + wire [1:0]axi_interconnect_0_M02_AXI_RRESP; + wire axi_interconnect_0_M02_AXI_RVALID; + wire [31:0]axi_interconnect_0_M02_AXI_WDATA; + wire axi_interconnect_0_M02_AXI_WREADY; + wire axi_interconnect_0_M02_AXI_WVALID; + wire [30:0]axi_interconnect_0_M03_AXI_ARADDR; + wire [1:0]axi_interconnect_0_M03_AXI_ARBURST; + wire [3:0]axi_interconnect_0_M03_AXI_ARCACHE; + wire [7:0]axi_interconnect_0_M03_AXI_ARLEN; + wire axi_interconnect_0_M03_AXI_ARLOCK; + wire [2:0]axi_interconnect_0_M03_AXI_ARPROT; + wire [3:0]axi_interconnect_0_M03_AXI_ARQOS; + wire axi_interconnect_0_M03_AXI_ARREADY; + wire [2:0]axi_interconnect_0_M03_AXI_ARSIZE; + wire axi_interconnect_0_M03_AXI_ARVALID; + wire [30:0]axi_interconnect_0_M03_AXI_AWADDR; + wire [1:0]axi_interconnect_0_M03_AXI_AWBURST; + wire [3:0]axi_interconnect_0_M03_AXI_AWCACHE; + wire [7:0]axi_interconnect_0_M03_AXI_AWLEN; + wire axi_interconnect_0_M03_AXI_AWLOCK; + wire [2:0]axi_interconnect_0_M03_AXI_AWPROT; + wire [3:0]axi_interconnect_0_M03_AXI_AWQOS; + wire axi_interconnect_0_M03_AXI_AWREADY; + wire [2:0]axi_interconnect_0_M03_AXI_AWSIZE; + wire axi_interconnect_0_M03_AXI_AWVALID; + wire axi_interconnect_0_M03_AXI_BREADY; + wire [1:0]axi_interconnect_0_M03_AXI_BRESP; + wire axi_interconnect_0_M03_AXI_BVALID; + wire [511:0]axi_interconnect_0_M03_AXI_RDATA; + wire axi_interconnect_0_M03_AXI_RLAST; + wire axi_interconnect_0_M03_AXI_RREADY; + wire [1:0]axi_interconnect_0_M03_AXI_RRESP; + wire axi_interconnect_0_M03_AXI_RVALID; + wire [511:0]axi_interconnect_0_M03_AXI_WDATA; + wire axi_interconnect_0_M03_AXI_WLAST; + wire axi_interconnect_0_M03_AXI_WREADY; + wire [63:0]axi_interconnect_0_M03_AXI_WSTRB; + wire axi_interconnect_0_M03_AXI_WVALID; + wire [12:0]axi_interconnect_0_M04_AXI_ARADDR; + wire [1:0]axi_interconnect_0_M04_AXI_ARBURST; + wire [3:0]axi_interconnect_0_M04_AXI_ARCACHE; + wire [7:0]axi_interconnect_0_M04_AXI_ARLEN; + wire axi_interconnect_0_M04_AXI_ARLOCK; + wire [2:0]axi_interconnect_0_M04_AXI_ARPROT; + wire axi_interconnect_0_M04_AXI_ARREADY; + wire [2:0]axi_interconnect_0_M04_AXI_ARSIZE; + wire axi_interconnect_0_M04_AXI_ARVALID; + wire [12:0]axi_interconnect_0_M04_AXI_AWADDR; + wire [1:0]axi_interconnect_0_M04_AXI_AWBURST; + wire [3:0]axi_interconnect_0_M04_AXI_AWCACHE; + wire [7:0]axi_interconnect_0_M04_AXI_AWLEN; + wire axi_interconnect_0_M04_AXI_AWLOCK; + wire [2:0]axi_interconnect_0_M04_AXI_AWPROT; + wire axi_interconnect_0_M04_AXI_AWREADY; + wire [2:0]axi_interconnect_0_M04_AXI_AWSIZE; + wire axi_interconnect_0_M04_AXI_AWVALID; + wire axi_interconnect_0_M04_AXI_BREADY; + wire [1:0]axi_interconnect_0_M04_AXI_BRESP; + wire axi_interconnect_0_M04_AXI_BVALID; + wire [31:0]axi_interconnect_0_M04_AXI_RDATA; + wire axi_interconnect_0_M04_AXI_RLAST; + wire axi_interconnect_0_M04_AXI_RREADY; + wire [1:0]axi_interconnect_0_M04_AXI_RRESP; + wire axi_interconnect_0_M04_AXI_RVALID; + wire [31:0]axi_interconnect_0_M04_AXI_WDATA; + wire axi_interconnect_0_M04_AXI_WLAST; + wire axi_interconnect_0_M04_AXI_WREADY; + wire [3:0]axi_interconnect_0_M04_AXI_WSTRB; + wire axi_interconnect_0_M04_AXI_WVALID; + wire [14:0]mig_7series_1_C0_DDR3_ADDR; + wire [2:0]mig_7series_1_C0_DDR3_BA; + wire mig_7series_1_C0_DDR3_CAS_N; + wire [0:0]mig_7series_1_C0_DDR3_CKE; + wire [0:0]mig_7series_1_C0_DDR3_CK_N; + wire [0:0]mig_7series_1_C0_DDR3_CK_P; + wire [0:0]mig_7series_1_C0_DDR3_CS_N; + wire [71:0]mig_7series_1_C0_DDR3_DQ; + wire [8:0]mig_7series_1_C0_DDR3_DQS_N; + wire [8:0]mig_7series_1_C0_DDR3_DQS_P; + wire [0:0]mig_7series_1_C0_DDR3_ODT; + wire mig_7series_1_C0_DDR3_RAS_N; + wire mig_7series_1_C0_DDR3_RESET_N; + wire mig_7series_1_C0_DDR3_WE_N; + wire [14:0]mig_7series_1_C1_DDR3_ADDR; + wire [2:0]mig_7series_1_C1_DDR3_BA; + wire mig_7series_1_C1_DDR3_CAS_N; + wire [0:0]mig_7series_1_C1_DDR3_CKE; + wire [0:0]mig_7series_1_C1_DDR3_CK_N; + wire [0:0]mig_7series_1_C1_DDR3_CK_P; + wire [0:0]mig_7series_1_C1_DDR3_CS_N; + wire [71:0]mig_7series_1_C1_DDR3_DQ; + wire [8:0]mig_7series_1_C1_DDR3_DQS_N; + wire [8:0]mig_7series_1_C1_DDR3_DQS_P; + wire [0:0]mig_7series_1_C1_DDR3_ODT; + wire mig_7series_1_C1_DDR3_RAS_N; + wire mig_7series_1_C1_DDR3_RESET_N; + wire mig_7series_1_C1_DDR3_WE_N; + wire mig_7series_1_c0_ui_clk_sync_rst; + wire mig_7series_1_c1_ui_clk; + wire mig_7series_1_c1_ui_clk_sync_rst; + wire mig_7series_1_ui_clk; + wire pci_reset_1; + wire [0:0]pcie_clkin_1_CLK_N; + wire [0:0]pcie_clkin_1_CLK_P; + wire [0:0]util_ds_buf_0_IBUF_OUT; + wire [7:0]util_vector_logic_2_Res; + wire xdma_1_axi_aclk; + wire xdma_1_axi_aresetn; + wire [0:0]xdma_1_pcie_mgt_rxn; + wire [0:0]xdma_1_pcie_mgt_rxp; + wire [0:0]xdma_1_pcie_mgt_txn; + wire [0:0]xdma_1_pcie_mgt_txp; + wire xdma_1_user_lnk_up; + wire [0:0]xlconstant_0_dout; + wire [0:0]xlconstant_2_dout; + + assign C0_DDR3_0_addr[14:0] = mig_7series_1_C0_DDR3_ADDR; + assign C0_DDR3_0_ba[2:0] = mig_7series_1_C0_DDR3_BA; + assign C0_DDR3_0_cas_n = mig_7series_1_C0_DDR3_CAS_N; + assign C0_DDR3_0_ck_n[0] = mig_7series_1_C0_DDR3_CK_N; + assign C0_DDR3_0_ck_p[0] = mig_7series_1_C0_DDR3_CK_P; + assign C0_DDR3_0_cke[0] = mig_7series_1_C0_DDR3_CKE; + assign C0_DDR3_0_cs_n[0] = mig_7series_1_C0_DDR3_CS_N; + assign C0_DDR3_0_odt[0] = mig_7series_1_C0_DDR3_ODT; + assign C0_DDR3_0_ras_n = mig_7series_1_C0_DDR3_RAS_N; + assign C0_DDR3_0_reset_n = mig_7series_1_C0_DDR3_RESET_N; + assign C0_DDR3_0_we_n = mig_7series_1_C0_DDR3_WE_N; + assign C0_SYS_CLK_0_1_CLK_N = C0_SYS_CLK_0_clk_n; + assign C0_SYS_CLK_0_1_CLK_P = C0_SYS_CLK_0_clk_p; + assign C1_DDR3_0_addr[14:0] = mig_7series_1_C1_DDR3_ADDR; + assign C1_DDR3_0_ba[2:0] = mig_7series_1_C1_DDR3_BA; + assign C1_DDR3_0_cas_n = mig_7series_1_C1_DDR3_CAS_N; + assign C1_DDR3_0_ck_n[0] = mig_7series_1_C1_DDR3_CK_N; + assign C1_DDR3_0_ck_p[0] = mig_7series_1_C1_DDR3_CK_P; + assign C1_DDR3_0_cke[0] = mig_7series_1_C1_DDR3_CKE; + assign C1_DDR3_0_cs_n[0] = mig_7series_1_C1_DDR3_CS_N; + assign C1_DDR3_0_odt[0] = mig_7series_1_C1_DDR3_ODT; + assign C1_DDR3_0_ras_n = mig_7series_1_C1_DDR3_RAS_N; + assign C1_DDR3_0_reset_n = mig_7series_1_C1_DDR3_RESET_N; + assign C1_DDR3_0_we_n = mig_7series_1_C1_DDR3_WE_N; + assign C1_SYS_CLK_0_1_CLK_N = C1_SYS_CLK_0_clk_n; + assign C1_SYS_CLK_0_1_CLK_P = C1_SYS_CLK_0_clk_p; + assign pci_reset_1 = pci_reset; + assign pcie_clkin_1_CLK_N = pcie_clkin_clk_n[0]; + assign pcie_clkin_1_CLK_P = pcie_clkin_clk_p[0]; + assign pcie_mgt_0_txn[0] = xdma_1_pcie_mgt_txn; + assign pcie_mgt_0_txp[0] = xdma_1_pcie_mgt_txp; + assign user_lnk_up_0 = xdma_1_user_lnk_up; + assign xdma_1_pcie_mgt_rxn = pcie_mgt_0_rxn[0]; + assign xdma_1_pcie_mgt_rxp = pcie_mgt_0_rxp[0]; + Top_axi_bram_ctrl_0_0 axi_bram_ctrl_0 + (.bram_addr_a(axi_bram_ctrl_0_BRAM_PORTA_ADDR), + .bram_clk_a(axi_bram_ctrl_0_BRAM_PORTA_CLK), + .bram_en_a(axi_bram_ctrl_0_BRAM_PORTA_EN), + .bram_rddata_a(axi_bram_ctrl_0_BRAM_PORTA_DOUT), + .bram_rst_a(axi_bram_ctrl_0_BRAM_PORTA_RST), + .bram_we_a(axi_bram_ctrl_0_BRAM_PORTA_WE), + .bram_wrdata_a(axi_bram_ctrl_0_BRAM_PORTA_DIN), + .s_axi_aclk(xdma_1_axi_aclk), + .s_axi_araddr(axi_interconnect_0_M04_AXI_ARADDR), + .s_axi_arburst(axi_interconnect_0_M04_AXI_ARBURST), + .s_axi_arcache(axi_interconnect_0_M04_AXI_ARCACHE), + .s_axi_aresetn(xdma_1_axi_aresetn), + .s_axi_arlen(axi_interconnect_0_M04_AXI_ARLEN), + .s_axi_arlock(axi_interconnect_0_M04_AXI_ARLOCK), + .s_axi_arprot(axi_interconnect_0_M04_AXI_ARPROT), + .s_axi_arready(axi_interconnect_0_M04_AXI_ARREADY), + .s_axi_arsize(axi_interconnect_0_M04_AXI_ARSIZE), + .s_axi_arvalid(axi_interconnect_0_M04_AXI_ARVALID), + .s_axi_awaddr(axi_interconnect_0_M04_AXI_AWADDR), + .s_axi_awburst(axi_interconnect_0_M04_AXI_AWBURST), + .s_axi_awcache(axi_interconnect_0_M04_AXI_AWCACHE), + .s_axi_awlen(axi_interconnect_0_M04_AXI_AWLEN), + .s_axi_awlock(axi_interconnect_0_M04_AXI_AWLOCK), + .s_axi_awprot(axi_interconnect_0_M04_AXI_AWPROT), + .s_axi_awready(axi_interconnect_0_M04_AXI_AWREADY), + .s_axi_awsize(axi_interconnect_0_M04_AXI_AWSIZE), + .s_axi_awvalid(axi_interconnect_0_M04_AXI_AWVALID), + .s_axi_bready(axi_interconnect_0_M04_AXI_BREADY), + .s_axi_bresp(axi_interconnect_0_M04_AXI_BRESP), + .s_axi_bvalid(axi_interconnect_0_M04_AXI_BVALID), + .s_axi_rdata(axi_interconnect_0_M04_AXI_RDATA), + .s_axi_rlast(axi_interconnect_0_M04_AXI_RLAST), + .s_axi_rready(axi_interconnect_0_M04_AXI_RREADY), + .s_axi_rresp(axi_interconnect_0_M04_AXI_RRESP), + .s_axi_rvalid(axi_interconnect_0_M04_AXI_RVALID), + .s_axi_wdata(axi_interconnect_0_M04_AXI_WDATA), + .s_axi_wlast(axi_interconnect_0_M04_AXI_WLAST), + .s_axi_wready(axi_interconnect_0_M04_AXI_WREADY), + .s_axi_wstrb(axi_interconnect_0_M04_AXI_WSTRB), + .s_axi_wvalid(axi_interconnect_0_M04_AXI_WVALID)); + axi_interconnect_0 axi_interconnect_0 + (.ACLK(xdma_1_axi_aclk), + .ARESETN(xdma_1_axi_aresetn), + .M00_ACLK(mig_7series_1_ui_clk), + .M00_ARESETN(M00_ARESETN_2), + .M00_AXI_araddr(axi_interconnect_0_M00_AXI_ARADDR), + .M00_AXI_arready(axi_interconnect_0_M00_AXI_ARREADY), + .M00_AXI_arvalid(axi_interconnect_0_M00_AXI_ARVALID), + .M00_AXI_awaddr(axi_interconnect_0_M00_AXI_AWADDR), + .M00_AXI_awready(axi_interconnect_0_M00_AXI_AWREADY), + .M00_AXI_awvalid(axi_interconnect_0_M00_AXI_AWVALID), + .M00_AXI_bready(axi_interconnect_0_M00_AXI_BREADY), + .M00_AXI_bresp(axi_interconnect_0_M00_AXI_BRESP), + .M00_AXI_bvalid(axi_interconnect_0_M00_AXI_BVALID), + .M00_AXI_rdata(axi_interconnect_0_M00_AXI_RDATA), + .M00_AXI_rready(axi_interconnect_0_M00_AXI_RREADY), + .M00_AXI_rresp(axi_interconnect_0_M00_AXI_RRESP), + .M00_AXI_rvalid(axi_interconnect_0_M00_AXI_RVALID), + .M00_AXI_wdata(axi_interconnect_0_M00_AXI_WDATA), + .M00_AXI_wready(axi_interconnect_0_M00_AXI_WREADY), + .M00_AXI_wvalid(axi_interconnect_0_M00_AXI_WVALID), + .M01_ACLK(mig_7series_1_ui_clk), + .M01_ARESETN(M00_ARESETN_2), + .M01_AXI_araddr(axi_interconnect_0_M01_AXI_ARADDR), + .M01_AXI_arburst(axi_interconnect_0_M01_AXI_ARBURST), + .M01_AXI_arcache(axi_interconnect_0_M01_AXI_ARCACHE), + .M01_AXI_arlen(axi_interconnect_0_M01_AXI_ARLEN), + .M01_AXI_arlock(axi_interconnect_0_M01_AXI_ARLOCK), + .M01_AXI_arprot(axi_interconnect_0_M01_AXI_ARPROT), + .M01_AXI_arqos(axi_interconnect_0_M01_AXI_ARQOS), + .M01_AXI_arready(axi_interconnect_0_M01_AXI_ARREADY), + .M01_AXI_arsize(axi_interconnect_0_M01_AXI_ARSIZE), + .M01_AXI_arvalid(axi_interconnect_0_M01_AXI_ARVALID), + .M01_AXI_awaddr(axi_interconnect_0_M01_AXI_AWADDR), + .M01_AXI_awburst(axi_interconnect_0_M01_AXI_AWBURST), + .M01_AXI_awcache(axi_interconnect_0_M01_AXI_AWCACHE), + .M01_AXI_awlen(axi_interconnect_0_M01_AXI_AWLEN), + .M01_AXI_awlock(axi_interconnect_0_M01_AXI_AWLOCK), + .M01_AXI_awprot(axi_interconnect_0_M01_AXI_AWPROT), + .M01_AXI_awqos(axi_interconnect_0_M01_AXI_AWQOS), + .M01_AXI_awready(axi_interconnect_0_M01_AXI_AWREADY), + .M01_AXI_awsize(axi_interconnect_0_M01_AXI_AWSIZE), + .M01_AXI_awvalid(axi_interconnect_0_M01_AXI_AWVALID), + .M01_AXI_bready(axi_interconnect_0_M01_AXI_BREADY), + .M01_AXI_bresp(axi_interconnect_0_M01_AXI_BRESP), + .M01_AXI_bvalid(axi_interconnect_0_M01_AXI_BVALID), + .M01_AXI_rdata(axi_interconnect_0_M01_AXI_RDATA), + .M01_AXI_rlast(axi_interconnect_0_M01_AXI_RLAST), + .M01_AXI_rready(axi_interconnect_0_M01_AXI_RREADY), + .M01_AXI_rresp(axi_interconnect_0_M01_AXI_RRESP), + .M01_AXI_rvalid(axi_interconnect_0_M01_AXI_RVALID), + .M01_AXI_wdata(axi_interconnect_0_M01_AXI_WDATA), + .M01_AXI_wlast(axi_interconnect_0_M01_AXI_WLAST), + .M01_AXI_wready(axi_interconnect_0_M01_AXI_WREADY), + .M01_AXI_wstrb(axi_interconnect_0_M01_AXI_WSTRB), + .M01_AXI_wvalid(axi_interconnect_0_M01_AXI_WVALID), + .M02_ACLK(mig_7series_1_c1_ui_clk), + .M02_ARESETN(util_vector_logic_2_Res), + .M02_AXI_araddr(axi_interconnect_0_M02_AXI_ARADDR), + .M02_AXI_arready(axi_interconnect_0_M02_AXI_ARREADY), + .M02_AXI_arvalid(axi_interconnect_0_M02_AXI_ARVALID), + .M02_AXI_awaddr(axi_interconnect_0_M02_AXI_AWADDR), + .M02_AXI_awready(axi_interconnect_0_M02_AXI_AWREADY), + .M02_AXI_awvalid(axi_interconnect_0_M02_AXI_AWVALID), + .M02_AXI_bready(axi_interconnect_0_M02_AXI_BREADY), + .M02_AXI_bresp(axi_interconnect_0_M02_AXI_BRESP), + .M02_AXI_bvalid(axi_interconnect_0_M02_AXI_BVALID), + .M02_AXI_rdata(axi_interconnect_0_M02_AXI_RDATA), + .M02_AXI_rready(axi_interconnect_0_M02_AXI_RREADY), + .M02_AXI_rresp(axi_interconnect_0_M02_AXI_RRESP), + .M02_AXI_rvalid(axi_interconnect_0_M02_AXI_RVALID), + .M02_AXI_wdata(axi_interconnect_0_M02_AXI_WDATA), + .M02_AXI_wready(axi_interconnect_0_M02_AXI_WREADY), + .M02_AXI_wvalid(axi_interconnect_0_M02_AXI_WVALID), + .M03_ACLK(mig_7series_1_c1_ui_clk), + .M03_ARESETN(util_vector_logic_2_Res), + .M03_AXI_araddr(axi_interconnect_0_M03_AXI_ARADDR), + .M03_AXI_arburst(axi_interconnect_0_M03_AXI_ARBURST), + .M03_AXI_arcache(axi_interconnect_0_M03_AXI_ARCACHE), + .M03_AXI_arlen(axi_interconnect_0_M03_AXI_ARLEN), + .M03_AXI_arlock(axi_interconnect_0_M03_AXI_ARLOCK), + .M03_AXI_arprot(axi_interconnect_0_M03_AXI_ARPROT), + .M03_AXI_arqos(axi_interconnect_0_M03_AXI_ARQOS), + .M03_AXI_arready(axi_interconnect_0_M03_AXI_ARREADY), + .M03_AXI_arsize(axi_interconnect_0_M03_AXI_ARSIZE), + .M03_AXI_arvalid(axi_interconnect_0_M03_AXI_ARVALID), + .M03_AXI_awaddr(axi_interconnect_0_M03_AXI_AWADDR), + .M03_AXI_awburst(axi_interconnect_0_M03_AXI_AWBURST), + .M03_AXI_awcache(axi_interconnect_0_M03_AXI_AWCACHE), + .M03_AXI_awlen(axi_interconnect_0_M03_AXI_AWLEN), + .M03_AXI_awlock(axi_interconnect_0_M03_AXI_AWLOCK), + .M03_AXI_awprot(axi_interconnect_0_M03_AXI_AWPROT), + .M03_AXI_awqos(axi_interconnect_0_M03_AXI_AWQOS), + .M03_AXI_awready(axi_interconnect_0_M03_AXI_AWREADY), + .M03_AXI_awsize(axi_interconnect_0_M03_AXI_AWSIZE), + .M03_AXI_awvalid(axi_interconnect_0_M03_AXI_AWVALID), + .M03_AXI_bready(axi_interconnect_0_M03_AXI_BREADY), + .M03_AXI_bresp(axi_interconnect_0_M03_AXI_BRESP), + .M03_AXI_bvalid(axi_interconnect_0_M03_AXI_BVALID), + .M03_AXI_rdata(axi_interconnect_0_M03_AXI_RDATA), + .M03_AXI_rlast(axi_interconnect_0_M03_AXI_RLAST), + .M03_AXI_rready(axi_interconnect_0_M03_AXI_RREADY), + .M03_AXI_rresp(axi_interconnect_0_M03_AXI_RRESP), + .M03_AXI_rvalid(axi_interconnect_0_M03_AXI_RVALID), + .M03_AXI_wdata(axi_interconnect_0_M03_AXI_WDATA), + .M03_AXI_wlast(axi_interconnect_0_M03_AXI_WLAST), + .M03_AXI_wready(axi_interconnect_0_M03_AXI_WREADY), + .M03_AXI_wstrb(axi_interconnect_0_M03_AXI_WSTRB), + .M03_AXI_wvalid(axi_interconnect_0_M03_AXI_WVALID), + .M04_ACLK(xdma_1_axi_aclk), + .M04_ARESETN(xdma_1_axi_aresetn), + .M04_AXI_araddr(axi_interconnect_0_M04_AXI_ARADDR), + .M04_AXI_arburst(axi_interconnect_0_M04_AXI_ARBURST), + .M04_AXI_arcache(axi_interconnect_0_M04_AXI_ARCACHE), + .M04_AXI_arlen(axi_interconnect_0_M04_AXI_ARLEN), + .M04_AXI_arlock(axi_interconnect_0_M04_AXI_ARLOCK), + .M04_AXI_arprot(axi_interconnect_0_M04_AXI_ARPROT), + .M04_AXI_arready(axi_interconnect_0_M04_AXI_ARREADY), + .M04_AXI_arsize(axi_interconnect_0_M04_AXI_ARSIZE), + .M04_AXI_arvalid(axi_interconnect_0_M04_AXI_ARVALID), + .M04_AXI_awaddr(axi_interconnect_0_M04_AXI_AWADDR), + .M04_AXI_awburst(axi_interconnect_0_M04_AXI_AWBURST), + .M04_AXI_awcache(axi_interconnect_0_M04_AXI_AWCACHE), + .M04_AXI_awlen(axi_interconnect_0_M04_AXI_AWLEN), + .M04_AXI_awlock(axi_interconnect_0_M04_AXI_AWLOCK), + .M04_AXI_awprot(axi_interconnect_0_M04_AXI_AWPROT), + .M04_AXI_awready(axi_interconnect_0_M04_AXI_AWREADY), + .M04_AXI_awsize(axi_interconnect_0_M04_AXI_AWSIZE), + .M04_AXI_awvalid(axi_interconnect_0_M04_AXI_AWVALID), + .M04_AXI_bready(axi_interconnect_0_M04_AXI_BREADY), + .M04_AXI_bresp(axi_interconnect_0_M04_AXI_BRESP), + .M04_AXI_bvalid(axi_interconnect_0_M04_AXI_BVALID), + .M04_AXI_rdata(axi_interconnect_0_M04_AXI_RDATA), + .M04_AXI_rlast(axi_interconnect_0_M04_AXI_RLAST), + .M04_AXI_rready(axi_interconnect_0_M04_AXI_RREADY), + .M04_AXI_rresp(axi_interconnect_0_M04_AXI_RRESP), + .M04_AXI_rvalid(axi_interconnect_0_M04_AXI_RVALID), + .M04_AXI_wdata(axi_interconnect_0_M04_AXI_WDATA), + .M04_AXI_wlast(axi_interconnect_0_M04_AXI_WLAST), + .M04_AXI_wready(axi_interconnect_0_M04_AXI_WREADY), + .M04_AXI_wstrb(axi_interconnect_0_M04_AXI_WSTRB), + .M04_AXI_wvalid(axi_interconnect_0_M04_AXI_WVALID), + .S00_ACLK(xdma_1_axi_aclk), + .S00_ARESETN(xdma_1_axi_aresetn), + .S00_AXI_araddr(S00_AXI_1_ARADDR), + .S00_AXI_arburst(S00_AXI_1_ARBURST), + .S00_AXI_arcache(S00_AXI_1_ARCACHE), + .S00_AXI_arid(S00_AXI_1_ARID), + .S00_AXI_arlen(S00_AXI_1_ARLEN), + .S00_AXI_arlock(S00_AXI_1_ARLOCK), + .S00_AXI_arprot(S00_AXI_1_ARPROT), + .S00_AXI_arready(S00_AXI_1_ARREADY), + .S00_AXI_arsize(S00_AXI_1_ARSIZE), + .S00_AXI_arvalid(S00_AXI_1_ARVALID), + .S00_AXI_awaddr(S00_AXI_1_AWADDR), + .S00_AXI_awburst(S00_AXI_1_AWBURST), + .S00_AXI_awcache(S00_AXI_1_AWCACHE), + .S00_AXI_awid(S00_AXI_1_AWID), + .S00_AXI_awlen(S00_AXI_1_AWLEN), + .S00_AXI_awlock(S00_AXI_1_AWLOCK), + .S00_AXI_awprot(S00_AXI_1_AWPROT), + .S00_AXI_awready(S00_AXI_1_AWREADY), + .S00_AXI_awsize(S00_AXI_1_AWSIZE), + .S00_AXI_awvalid(S00_AXI_1_AWVALID), + .S00_AXI_bid(S00_AXI_1_BID), + .S00_AXI_bready(S00_AXI_1_BREADY), + .S00_AXI_bresp(S00_AXI_1_BRESP), + .S00_AXI_bvalid(S00_AXI_1_BVALID), + .S00_AXI_rdata(S00_AXI_1_RDATA), + .S00_AXI_rid(S00_AXI_1_RID), + .S00_AXI_rlast(S00_AXI_1_RLAST), + .S00_AXI_rready(S00_AXI_1_RREADY), + .S00_AXI_rresp(S00_AXI_1_RRESP), + .S00_AXI_rvalid(S00_AXI_1_RVALID), + .S00_AXI_wdata(S00_AXI_1_WDATA), + .S00_AXI_wlast(S00_AXI_1_WLAST), + .S00_AXI_wready(S00_AXI_1_WREADY), + .S00_AXI_wstrb(S00_AXI_1_WSTRB), + .S00_AXI_wvalid(S00_AXI_1_WVALID)); + Top_blk_mem_gen_0_0 blk_mem_gen_0 + (.addra({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,axi_bram_ctrl_0_BRAM_PORTA_ADDR}), + .clka(axi_bram_ctrl_0_BRAM_PORTA_CLK), + .dina(axi_bram_ctrl_0_BRAM_PORTA_DIN), + .douta(axi_bram_ctrl_0_BRAM_PORTA_DOUT), + .ena(axi_bram_ctrl_0_BRAM_PORTA_EN), + .rsta(axi_bram_ctrl_0_BRAM_PORTA_RST), + .wea(axi_bram_ctrl_0_BRAM_PORTA_WE)); + Top_mig_7series_1_0 mig_7series_1 + (.c0_aresetn(xlconstant_0_dout), + .c0_ddr3_addr(mig_7series_1_C0_DDR3_ADDR), + .c0_ddr3_ba(mig_7series_1_C0_DDR3_BA), + .c0_ddr3_cas_n(mig_7series_1_C0_DDR3_CAS_N), + .c0_ddr3_ck_n(mig_7series_1_C0_DDR3_CK_N), + .c0_ddr3_ck_p(mig_7series_1_C0_DDR3_CK_P), + .c0_ddr3_cke(mig_7series_1_C0_DDR3_CKE), + .c0_ddr3_cs_n(mig_7series_1_C0_DDR3_CS_N), + .c0_ddr3_dq(C0_DDR3_0_dq[71:0]), + .c0_ddr3_dqs_n(C0_DDR3_0_dqs_n[8:0]), + .c0_ddr3_dqs_p(C0_DDR3_0_dqs_p[8:0]), + .c0_ddr3_odt(mig_7series_1_C0_DDR3_ODT), + .c0_ddr3_ras_n(mig_7series_1_C0_DDR3_RAS_N), + .c0_ddr3_reset_n(mig_7series_1_C0_DDR3_RESET_N), + .c0_ddr3_we_n(mig_7series_1_C0_DDR3_WE_N), + .c0_s_axi_araddr(axi_interconnect_0_M01_AXI_ARADDR), + .c0_s_axi_arburst(axi_interconnect_0_M01_AXI_ARBURST), + .c0_s_axi_arcache(axi_interconnect_0_M01_AXI_ARCACHE), + .c0_s_axi_arid({1'b0,1'b0,1'b0,1'b0}), + .c0_s_axi_arlen(axi_interconnect_0_M01_AXI_ARLEN), + .c0_s_axi_arlock(axi_interconnect_0_M01_AXI_ARLOCK), + .c0_s_axi_arprot(axi_interconnect_0_M01_AXI_ARPROT), + .c0_s_axi_arqos(axi_interconnect_0_M01_AXI_ARQOS), + .c0_s_axi_arready(axi_interconnect_0_M01_AXI_ARREADY), + .c0_s_axi_arsize(axi_interconnect_0_M01_AXI_ARSIZE), + .c0_s_axi_arvalid(axi_interconnect_0_M01_AXI_ARVALID), + .c0_s_axi_awaddr(axi_interconnect_0_M01_AXI_AWADDR), + .c0_s_axi_awburst(axi_interconnect_0_M01_AXI_AWBURST), + .c0_s_axi_awcache(axi_interconnect_0_M01_AXI_AWCACHE), + .c0_s_axi_awid({1'b0,1'b0,1'b0,1'b0}), + .c0_s_axi_awlen(axi_interconnect_0_M01_AXI_AWLEN), + .c0_s_axi_awlock(axi_interconnect_0_M01_AXI_AWLOCK), + .c0_s_axi_awprot(axi_interconnect_0_M01_AXI_AWPROT), + .c0_s_axi_awqos(axi_interconnect_0_M01_AXI_AWQOS), + .c0_s_axi_awready(axi_interconnect_0_M01_AXI_AWREADY), + .c0_s_axi_awsize(axi_interconnect_0_M01_AXI_AWSIZE), + .c0_s_axi_awvalid(axi_interconnect_0_M01_AXI_AWVALID), + .c0_s_axi_bready(axi_interconnect_0_M01_AXI_BREADY), + .c0_s_axi_bresp(axi_interconnect_0_M01_AXI_BRESP), + .c0_s_axi_bvalid(axi_interconnect_0_M01_AXI_BVALID), + .c0_s_axi_ctrl_araddr(axi_interconnect_0_M00_AXI_ARADDR), + .c0_s_axi_ctrl_arready(axi_interconnect_0_M00_AXI_ARREADY), + .c0_s_axi_ctrl_arvalid(axi_interconnect_0_M00_AXI_ARVALID), + .c0_s_axi_ctrl_awaddr(axi_interconnect_0_M00_AXI_AWADDR), + .c0_s_axi_ctrl_awready(axi_interconnect_0_M00_AXI_AWREADY), + .c0_s_axi_ctrl_awvalid(axi_interconnect_0_M00_AXI_AWVALID), + .c0_s_axi_ctrl_bready(axi_interconnect_0_M00_AXI_BREADY), + .c0_s_axi_ctrl_bresp(axi_interconnect_0_M00_AXI_BRESP), + .c0_s_axi_ctrl_bvalid(axi_interconnect_0_M00_AXI_BVALID), + .c0_s_axi_ctrl_rdata(axi_interconnect_0_M00_AXI_RDATA), + .c0_s_axi_ctrl_rready(axi_interconnect_0_M00_AXI_RREADY), + .c0_s_axi_ctrl_rresp(axi_interconnect_0_M00_AXI_RRESP), + .c0_s_axi_ctrl_rvalid(axi_interconnect_0_M00_AXI_RVALID), + .c0_s_axi_ctrl_wdata(axi_interconnect_0_M00_AXI_WDATA), + .c0_s_axi_ctrl_wready(axi_interconnect_0_M00_AXI_WREADY), + .c0_s_axi_ctrl_wvalid(axi_interconnect_0_M00_AXI_WVALID), + .c0_s_axi_rdata(axi_interconnect_0_M01_AXI_RDATA), + .c0_s_axi_rlast(axi_interconnect_0_M01_AXI_RLAST), + .c0_s_axi_rready(axi_interconnect_0_M01_AXI_RREADY), + .c0_s_axi_rresp(axi_interconnect_0_M01_AXI_RRESP), + .c0_s_axi_rvalid(axi_interconnect_0_M01_AXI_RVALID), + .c0_s_axi_wdata(axi_interconnect_0_M01_AXI_WDATA), + .c0_s_axi_wlast(axi_interconnect_0_M01_AXI_WLAST), + .c0_s_axi_wready(axi_interconnect_0_M01_AXI_WREADY), + .c0_s_axi_wstrb(axi_interconnect_0_M01_AXI_WSTRB), + .c0_s_axi_wvalid(axi_interconnect_0_M01_AXI_WVALID), + .c0_sys_clk_n(C0_SYS_CLK_0_1_CLK_N), + .c0_sys_clk_p(C0_SYS_CLK_0_1_CLK_P), + .c0_ui_clk(mig_7series_1_ui_clk), + .c0_ui_clk_sync_rst(mig_7series_1_c0_ui_clk_sync_rst), + .c1_aresetn(xlconstant_0_dout), + .c1_ddr3_addr(mig_7series_1_C1_DDR3_ADDR), + .c1_ddr3_ba(mig_7series_1_C1_DDR3_BA), + .c1_ddr3_cas_n(mig_7series_1_C1_DDR3_CAS_N), + .c1_ddr3_ck_n(mig_7series_1_C1_DDR3_CK_N), + .c1_ddr3_ck_p(mig_7series_1_C1_DDR3_CK_P), + .c1_ddr3_cke(mig_7series_1_C1_DDR3_CKE), + .c1_ddr3_cs_n(mig_7series_1_C1_DDR3_CS_N), + .c1_ddr3_dq(C1_DDR3_0_dq[71:0]), + .c1_ddr3_dqs_n(C1_DDR3_0_dqs_n[8:0]), + .c1_ddr3_dqs_p(C1_DDR3_0_dqs_p[8:0]), + .c1_ddr3_odt(mig_7series_1_C1_DDR3_ODT), + .c1_ddr3_ras_n(mig_7series_1_C1_DDR3_RAS_N), + .c1_ddr3_reset_n(mig_7series_1_C1_DDR3_RESET_N), + .c1_ddr3_we_n(mig_7series_1_C1_DDR3_WE_N), + .c1_s_axi_araddr(axi_interconnect_0_M03_AXI_ARADDR), + .c1_s_axi_arburst(axi_interconnect_0_M03_AXI_ARBURST), + .c1_s_axi_arcache(axi_interconnect_0_M03_AXI_ARCACHE), + .c1_s_axi_arid({1'b0,1'b0,1'b0,1'b0}), + .c1_s_axi_arlen(axi_interconnect_0_M03_AXI_ARLEN), + .c1_s_axi_arlock(axi_interconnect_0_M03_AXI_ARLOCK), + .c1_s_axi_arprot(axi_interconnect_0_M03_AXI_ARPROT), + .c1_s_axi_arqos(axi_interconnect_0_M03_AXI_ARQOS), + .c1_s_axi_arready(axi_interconnect_0_M03_AXI_ARREADY), + .c1_s_axi_arsize(axi_interconnect_0_M03_AXI_ARSIZE), + .c1_s_axi_arvalid(axi_interconnect_0_M03_AXI_ARVALID), + .c1_s_axi_awaddr(axi_interconnect_0_M03_AXI_AWADDR), + .c1_s_axi_awburst(axi_interconnect_0_M03_AXI_AWBURST), + .c1_s_axi_awcache(axi_interconnect_0_M03_AXI_AWCACHE), + .c1_s_axi_awid({1'b0,1'b0,1'b0,1'b0}), + .c1_s_axi_awlen(axi_interconnect_0_M03_AXI_AWLEN), + .c1_s_axi_awlock(axi_interconnect_0_M03_AXI_AWLOCK), + .c1_s_axi_awprot(axi_interconnect_0_M03_AXI_AWPROT), + .c1_s_axi_awqos(axi_interconnect_0_M03_AXI_AWQOS), + .c1_s_axi_awready(axi_interconnect_0_M03_AXI_AWREADY), + .c1_s_axi_awsize(axi_interconnect_0_M03_AXI_AWSIZE), + .c1_s_axi_awvalid(axi_interconnect_0_M03_AXI_AWVALID), + .c1_s_axi_bready(axi_interconnect_0_M03_AXI_BREADY), + .c1_s_axi_bresp(axi_interconnect_0_M03_AXI_BRESP), + .c1_s_axi_bvalid(axi_interconnect_0_M03_AXI_BVALID), + .c1_s_axi_ctrl_araddr(axi_interconnect_0_M02_AXI_ARADDR), + .c1_s_axi_ctrl_arready(axi_interconnect_0_M02_AXI_ARREADY), + .c1_s_axi_ctrl_arvalid(axi_interconnect_0_M02_AXI_ARVALID), + .c1_s_axi_ctrl_awaddr(axi_interconnect_0_M02_AXI_AWADDR), + .c1_s_axi_ctrl_awready(axi_interconnect_0_M02_AXI_AWREADY), + .c1_s_axi_ctrl_awvalid(axi_interconnect_0_M02_AXI_AWVALID), + .c1_s_axi_ctrl_bready(axi_interconnect_0_M02_AXI_BREADY), + .c1_s_axi_ctrl_bresp(axi_interconnect_0_M02_AXI_BRESP), + .c1_s_axi_ctrl_bvalid(axi_interconnect_0_M02_AXI_BVALID), + .c1_s_axi_ctrl_rdata(axi_interconnect_0_M02_AXI_RDATA), + .c1_s_axi_ctrl_rready(axi_interconnect_0_M02_AXI_RREADY), + .c1_s_axi_ctrl_rresp(axi_interconnect_0_M02_AXI_RRESP), + .c1_s_axi_ctrl_rvalid(axi_interconnect_0_M02_AXI_RVALID), + .c1_s_axi_ctrl_wdata(axi_interconnect_0_M02_AXI_WDATA), + .c1_s_axi_ctrl_wready(axi_interconnect_0_M02_AXI_WREADY), + .c1_s_axi_ctrl_wvalid(axi_interconnect_0_M02_AXI_WVALID), + .c1_s_axi_rdata(axi_interconnect_0_M03_AXI_RDATA), + .c1_s_axi_rlast(axi_interconnect_0_M03_AXI_RLAST), + .c1_s_axi_rready(axi_interconnect_0_M03_AXI_RREADY), + .c1_s_axi_rresp(axi_interconnect_0_M03_AXI_RRESP), + .c1_s_axi_rvalid(axi_interconnect_0_M03_AXI_RVALID), + .c1_s_axi_wdata(axi_interconnect_0_M03_AXI_WDATA), + .c1_s_axi_wlast(axi_interconnect_0_M03_AXI_WLAST), + .c1_s_axi_wready(axi_interconnect_0_M03_AXI_WREADY), + .c1_s_axi_wstrb(axi_interconnect_0_M03_AXI_WSTRB), + .c1_s_axi_wvalid(axi_interconnect_0_M03_AXI_WVALID), + .c1_sys_clk_n(C1_SYS_CLK_0_1_CLK_N), + .c1_sys_clk_p(C1_SYS_CLK_0_1_CLK_P), + .c1_ui_clk(mig_7series_1_c1_ui_clk), + .c1_ui_clk_sync_rst(mig_7series_1_c1_ui_clk_sync_rst), + .sys_rst(xlconstant_2_dout)); + Top_util_ds_buf_0_0 util_ds_buf_0 + (.IBUF_DS_N(pcie_clkin_1_CLK_N), + .IBUF_DS_P(pcie_clkin_1_CLK_P), + .IBUF_OUT(util_ds_buf_0_IBUF_OUT)); + Top_util_vector_logic_1_3 util_vector_logic_1 + (.Op1({mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst,mig_7series_1_c0_ui_clk_sync_rst}), + .Res(M00_ARESETN_2)); + Top_util_vector_logic_1_4 util_vector_logic_2 + (.Op1({mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst,mig_7series_1_c1_ui_clk_sync_rst}), + .Res(util_vector_logic_2_Res)); + Top_xdma_1_1 xdma_1 + (.axi_aclk(xdma_1_axi_aclk), + .axi_aresetn(xdma_1_axi_aresetn), + .cfg_mgmt_addr({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .cfg_mgmt_byte_enable({1'b0,1'b0,1'b0,1'b0}), + .cfg_mgmt_read(1'b0), + .cfg_mgmt_type1_cfg_reg_access(1'b0), + .cfg_mgmt_write(1'b0), + .cfg_mgmt_write_data({1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0,1'b0}), + .m_axi_araddr(S00_AXI_1_ARADDR), + .m_axi_arburst(S00_AXI_1_ARBURST), + .m_axi_arcache(S00_AXI_1_ARCACHE), + .m_axi_arid(S00_AXI_1_ARID), + .m_axi_arlen(S00_AXI_1_ARLEN), + .m_axi_arlock(S00_AXI_1_ARLOCK), + .m_axi_arprot(S00_AXI_1_ARPROT), + .m_axi_arready(S00_AXI_1_ARREADY), + .m_axi_arsize(S00_AXI_1_ARSIZE), + .m_axi_arvalid(S00_AXI_1_ARVALID), + .m_axi_awaddr(S00_AXI_1_AWADDR), + .m_axi_awburst(S00_AXI_1_AWBURST), + .m_axi_awcache(S00_AXI_1_AWCACHE), + .m_axi_awid(S00_AXI_1_AWID), + .m_axi_awlen(S00_AXI_1_AWLEN), + .m_axi_awlock(S00_AXI_1_AWLOCK), + .m_axi_awprot(S00_AXI_1_AWPROT), + .m_axi_awready(S00_AXI_1_AWREADY), + .m_axi_awsize(S00_AXI_1_AWSIZE), + .m_axi_awvalid(S00_AXI_1_AWVALID), + .m_axi_bid(S00_AXI_1_BID), + .m_axi_bready(S00_AXI_1_BREADY), + .m_axi_bresp(S00_AXI_1_BRESP), + .m_axi_bvalid(S00_AXI_1_BVALID), + .m_axi_rdata(S00_AXI_1_RDATA), + .m_axi_rid(S00_AXI_1_RID), + .m_axi_rlast(S00_AXI_1_RLAST), + .m_axi_rready(S00_AXI_1_RREADY), + .m_axi_rresp(S00_AXI_1_RRESP), + .m_axi_rvalid(S00_AXI_1_RVALID), + .m_axi_wdata(S00_AXI_1_WDATA), + .m_axi_wlast(S00_AXI_1_WLAST), + .m_axi_wready(S00_AXI_1_WREADY), + .m_axi_wstrb(S00_AXI_1_WSTRB), + .m_axi_wvalid(S00_AXI_1_WVALID), + .pci_exp_rxn(xdma_1_pcie_mgt_rxn), + .pci_exp_rxp(xdma_1_pcie_mgt_rxp), + .pci_exp_txn(xdma_1_pcie_mgt_txn), + .pci_exp_txp(xdma_1_pcie_mgt_txp), + .sys_clk(util_ds_buf_0_IBUF_OUT), + .sys_rst_n(pci_reset_1), + .user_lnk_up(xdma_1_user_lnk_up), + .usr_irq_req(1'b0)); + Top_xlconstant_0_1 xlconstant_0 + (.dout(xlconstant_0_dout)); + Top_xlconstant_2_0 xlconstant_2 + (.dout(xlconstant_2_dout)); +endmodule diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_0/Top_auto_cc_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_0/Top_auto_cc_0.xci index 9cbcb1f..b9e8f75 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_0/Top_auto_cc_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_0/Top_auto_cc_0.xci @@ -5,7 +5,7 @@ "cell_name": "axi_interconnect_0/m00_couplers/auto_cc", "component_reference": "xilinx.com:ip:axi_clock_converter:2.1", "ip_revision": "26", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_0", + "gen_directory": "../../../../../build/my_project.gen/sources_1/ip/Top_auto_cc_0", "parameters": { "component_parameters": { "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], @@ -61,9 +61,9 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "26" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_0" } ], + "OUTPUTDIR": [ { "value": "../../../../../build/my_project.gen/sources_1/ip/Top_auto_cc_0" } ], "SELECTEDSIMMODEL": [ { "value": "rtl" } ], - "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SHAREDDIR": [ { "value": "../../../../../nitefury_pcie_xdma_ddr/project/sources/ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] } @@ -176,7 +176,7 @@ "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "32", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -304,7 +304,7 @@ "FREQ_HZ": [ { "value": "62500000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_RESET": [ { "value": "S_AXI_ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_1/Top_auto_cc_1.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_1/Top_auto_cc_1.xci index c6e7d52..237f05a 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_1/Top_auto_cc_1.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_1/Top_auto_cc_1.xci @@ -5,7 +5,7 @@ "cell_name": "axi_interconnect_0/m01_couplers/auto_cc", "component_reference": "xilinx.com:ip:axi_clock_converter:2.1", "ip_revision": "26", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_1", + "gen_directory": "../../../../../build/my_project.gen/sources_1/ip/Top_auto_cc_1", "parameters": { "component_parameters": { "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], @@ -53,7 +53,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, @@ -61,9 +61,9 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "26" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_1" } ], + "OUTPUTDIR": [ { "value": "../../../../../build/my_project.gen/sources_1/ip/Top_auto_cc_1" } ], "SELECTEDSIMMODEL": [ { "value": "rtl" } ], - "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SHAREDDIR": [ { "value": "../../../../../nitefury_pcie_xdma_ddr/project/sources/ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] } @@ -176,7 +176,7 @@ "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "32", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -304,7 +304,7 @@ "FREQ_HZ": [ { "value": "62500000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_RESET": [ { "value": "S_AXI_ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_2/Top_auto_cc_2.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_2/Top_auto_cc_2.xci index 708424a..c5c202f 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_2/Top_auto_cc_2.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_2/Top_auto_cc_2.xci @@ -5,7 +5,7 @@ "cell_name": "axi_interconnect_0/m02_couplers/auto_cc", "component_reference": "xilinx.com:ip:axi_clock_converter:2.1", "ip_revision": "26", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_2", + "gen_directory": "../../../../../build/my_project.gen/sources_1/ip/Top_auto_cc_2", "parameters": { "component_parameters": { "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], @@ -53,7 +53,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, @@ -61,9 +61,9 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "26" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_2" } ], + "OUTPUTDIR": [ { "value": "../../../../../build/my_project.gen/sources_1/ip/Top_auto_cc_2" } ], "SELECTEDSIMMODEL": [ { "value": "rtl" } ], - "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SHAREDDIR": [ { "value": "../../../../../nitefury_pcie_xdma_ddr/project/sources/ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] } @@ -176,7 +176,7 @@ "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "32", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -304,7 +304,7 @@ "FREQ_HZ": [ { "value": "62500000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_RESET": [ { "value": "S_AXI_ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_3/Top_auto_cc_3.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_3/Top_auto_cc_3.xci index 3b687bf..6e18ac7 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_3/Top_auto_cc_3.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_3/Top_auto_cc_3.xci @@ -5,7 +5,7 @@ "cell_name": "axi_interconnect_0/m03_couplers/auto_cc", "component_reference": "xilinx.com:ip:axi_clock_converter:2.1", "ip_revision": "26", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_3", + "gen_directory": "../../../../../build/my_project.gen/sources_1/ip/Top_auto_cc_3", "parameters": { "component_parameters": { "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], @@ -53,7 +53,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, @@ -61,9 +61,9 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "26" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_cc_3" } ], + "OUTPUTDIR": [ { "value": "../../../../../build/my_project.gen/sources_1/ip/Top_auto_cc_3" } ], "SELECTEDSIMMODEL": [ { "value": "rtl" } ], - "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SHAREDDIR": [ { "value": "../../../../../nitefury_pcie_xdma_ddr/project/sources/ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] } @@ -176,7 +176,7 @@ "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "32", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -304,7 +304,7 @@ "FREQ_HZ": [ { "value": "62500000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_BUSIF": [ { "value": "S_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_RESET": [ { "value": "S_AXI_ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_0/Top_auto_ds_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_0/Top_auto_ds_0.xci index c518140..65a2456 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_0/Top_auto_ds_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_0/Top_auto_ds_0.xci @@ -5,7 +5,7 @@ "cell_name": "axi_interconnect_0/m00_couplers/auto_ds", "component_reference": "xilinx.com:ip:axi_dwidth_converter:2.1", "ip_revision": "27", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_ds_0", + "gen_directory": "../../../../../build/my_project.gen/sources_1/ip/Top_auto_ds_0", "parameters": { "component_parameters": { "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], @@ -51,7 +51,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, @@ -59,9 +59,9 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "27" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_ds_0" } ], + "OUTPUTDIR": [ { "value": "../../../../../build/my_project.gen/sources_1/ip/Top_auto_ds_0" } ], "SELECTEDSIMMODEL": [ { "value": "rtl" } ], - "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SHAREDDIR": [ { "value": "../../../../../nitefury_pcie_xdma_ddr/project/sources/ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] } diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_1/Top_auto_ds_1.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_1/Top_auto_ds_1.xci index 09d2908..80e8bf0 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_1/Top_auto_ds_1.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_1/Top_auto_ds_1.xci @@ -5,7 +5,7 @@ "cell_name": "axi_interconnect_0/m02_couplers/auto_ds", "component_reference": "xilinx.com:ip:axi_dwidth_converter:2.1", "ip_revision": "27", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_ds_1", + "gen_directory": "../../../../../build/my_project.gen/sources_1/ip/Top_auto_ds_1", "parameters": { "component_parameters": { "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], @@ -51,7 +51,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, @@ -59,9 +59,9 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "27" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_ds_1" } ], + "OUTPUTDIR": [ { "value": "../../../../../build/my_project.gen/sources_1/ip/Top_auto_ds_1" } ], "SELECTEDSIMMODEL": [ { "value": "rtl" } ], - "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SHAREDDIR": [ { "value": "../../../../../nitefury_pcie_xdma_ddr/project/sources/ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] } diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_2/Top_auto_ds_2.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_2/Top_auto_ds_2.xci index 034b28c..1f10216 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_2/Top_auto_ds_2.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_2/Top_auto_ds_2.xci @@ -5,7 +5,7 @@ "cell_name": "axi_interconnect_0/m04_couplers/auto_ds", "component_reference": "xilinx.com:ip:axi_dwidth_converter:2.1", "ip_revision": "27", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_ds_2", + "gen_directory": "../../../../../build/my_project.gen/sources_1/ip/Top_auto_ds_2", "parameters": { "component_parameters": { "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], @@ -51,7 +51,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, @@ -59,9 +59,9 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "27" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_ds_2" } ], + "OUTPUTDIR": [ { "value": "../../../../../build/my_project.gen/sources_1/ip/Top_auto_ds_2" } ], "SELECTEDSIMMODEL": [ { "value": "rtl" } ], - "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SHAREDDIR": [ { "value": "../../../../../nitefury_pcie_xdma_ddr/project/sources/ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] } @@ -172,7 +172,7 @@ "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "32", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -247,7 +247,7 @@ "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -300,7 +300,7 @@ "FREQ_HZ": [ { "value": "62500000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_RESET": [ { "value": "S_AXI_ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_pc_0/Top_auto_pc_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_pc_0/Top_auto_pc_0.xci index 49d0db4..b0ffdca 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_pc_0/Top_auto_pc_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_pc_0/Top_auto_pc_0.xci @@ -5,7 +5,7 @@ "cell_name": "axi_interconnect_0/m00_couplers/auto_pc", "component_reference": "xilinx.com:ip:axi_protocol_converter:2.1", "ip_revision": "27", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_pc_0", + "gen_directory": "../../../../../build/my_project.gen/sources_1/ip/Top_auto_pc_0", "parameters": { "component_parameters": { "SI_PROTOCOL": [ { "value": "AXI4", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], @@ -51,7 +51,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, @@ -59,9 +59,9 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "27" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_pc_0" } ], + "OUTPUTDIR": [ { "value": "../../../../../build/my_project.gen/sources_1/ip/Top_auto_pc_0" } ], "SELECTEDSIMMODEL": [ { "value": "rtl" } ], - "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SHAREDDIR": [ { "value": "../../../../../nitefury_pcie_xdma_ddr/project/sources/ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] } diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_pc_1/Top_auto_pc_1.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_pc_1/Top_auto_pc_1.xci index d334106..2207ef3 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_pc_1/Top_auto_pc_1.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_pc_1/Top_auto_pc_1.xci @@ -5,7 +5,7 @@ "cell_name": "axi_interconnect_0/m02_couplers/auto_pc", "component_reference": "xilinx.com:ip:axi_protocol_converter:2.1", "ip_revision": "27", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_pc_1", + "gen_directory": "../../../../../build/my_project.gen/sources_1/ip/Top_auto_pc_1", "parameters": { "component_parameters": { "SI_PROTOCOL": [ { "value": "AXI4", "value_src": "user", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], @@ -51,7 +51,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, @@ -59,9 +59,9 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "27" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_pc_1" } ], + "OUTPUTDIR": [ { "value": "../../../../../build/my_project.gen/sources_1/ip/Top_auto_pc_1" } ], "SELECTEDSIMMODEL": [ { "value": "rtl" } ], - "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SHAREDDIR": [ { "value": "../../../../../nitefury_pcie_xdma_ddr/project/sources/ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] } diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_us_0/Top_auto_us_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_us_0/Top_auto_us_0.xci index ccfba49..26fd983 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_us_0/Top_auto_us_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_us_0/Top_auto_us_0.xci @@ -5,7 +5,7 @@ "cell_name": "axi_interconnect_0/s00_couplers/auto_us", "component_reference": "xilinx.com:ip:axi_dwidth_converter:2.1", "ip_revision": "27", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_us_0", + "gen_directory": "../../../../../build/my_project.gen/sources_1/ip/Top_auto_us_0", "parameters": { "component_parameters": { "PROTOCOL": [ { "value": "AXI4", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "usage": "all" } ], @@ -51,7 +51,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, @@ -59,9 +59,9 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "27" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_auto_us_0" } ], + "OUTPUTDIR": [ { "value": "../../../../../build/my_project.gen/sources_1/ip/Top_auto_us_0" } ], "SELECTEDSIMMODEL": [ { "value": "rtl" } ], - "SHAREDDIR": [ { "value": "../../ipshared" } ], + "SHAREDDIR": [ { "value": "../../../../../nitefury_pcie_xdma_ddr/project/sources/ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], "SYNTHESISFLOW": [ { "value": "OUT_OF_CONTEXT" } ] } @@ -176,7 +176,7 @@ "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -255,7 +255,7 @@ "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -308,7 +308,7 @@ "FREQ_HZ": [ { "value": "62500000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_BUSIF": [ { "value": "S_AXI:M_AXI", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_RESET": [ { "value": "S_AXI_ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci index dda03df..1f9fb8b 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci @@ -5,7 +5,7 @@ "cell_name": "axi_bram_ctrl_0", "component_reference": "xilinx.com:ip:axi_bram_ctrl:4.1", "ip_revision": "7", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_axi_bram_ctrl_0_0", + "gen_directory": "../../../build/my_project.gen/sources_1/ip/Top_axi_bram_ctrl_0_0", "parameters": { "component_parameters": { "DATA_WIDTH": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -62,7 +62,7 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "7" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_axi_bram_ctrl_0_0" } ], + "OUTPUTDIR": [ { "value": "../../../build/my_project.gen/sources_1/ip/Top_axi_bram_ctrl_0_0" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "../../ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], @@ -144,7 +144,7 @@ "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "256", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -229,7 +229,7 @@ "FREQ_HZ": [ { "value": "62500000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci index 2782815..caa0cb1 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci @@ -5,7 +5,7 @@ "cell_name": "axi_interconnect_0", "component_reference": "xilinx.com:ip:axi_interconnect:2.1", "ip_revision": "28", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_axi_interconnect_0_0", + "gen_directory": "../../../build/my_project.gen/sources_1/ip/Top_axi_interconnect_0_0", "parameters": { "component_parameters": { "NUM_SI": [ { "value": "1", "value_src": "user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -343,7 +343,7 @@ "IPCONTEXT": [ { "value": "IP_Integrator_AppCore" } ], "IPREVISION": [ { "value": "28" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_axi_interconnect_0_0" } ], + "OUTPUTDIR": [ { "value": "../../../build/my_project.gen/sources_1/ip/Top_axi_interconnect_0_0" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "../../ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci index 1f62790..697d081 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci @@ -5,7 +5,7 @@ "cell_name": "blk_mem_gen_0", "component_reference": "xilinx.com:ip:blk_mem_gen:8.4", "ip_revision": "5", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_blk_mem_gen_0_0", + "gen_directory": "../../../build/my_project.gen/sources_1/ip/Top_blk_mem_gen_0_0", "parameters": { "component_parameters": { "Component_Name": [ { "value": "Top_blk_mem_gen_0_0", "resolve_type": "user", "usage": "all" } ], @@ -177,7 +177,7 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "5" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_blk_mem_gen_0_0" } ], + "OUTPUTDIR": [ { "value": "../../../build/my_project.gen/sources_1/ip/Top_blk_mem_gen_0_0" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "../../ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci index 5036b3f..2f61b3a 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci @@ -5,12 +5,12 @@ "cell_name": "mig_7series_1", "component_reference": "xilinx.com:ip:mig_7series:4.2", "ip_revision": "1", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_mig_7series_1_0", + "gen_directory": "../../../build/my_project.gen/sources_1/ip/Top_mig_7series_1_0", "parameters": { "component_parameters": { "XML_INPUT_FILE": [ { "value": "mig_b.prj", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "RESET_BOARD_INTERFACE": [ { "value": "Custom", "value_src": "user", "resolve_type": "user", "usage": "all" } ], - "MIG_DONT_TOUCH_PARAM": [ { "value": "Custom", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "MIG_DONT_TOUCH_PARAM": [ { "value": "Custom", "value_src": "user_prop", "resolve_type": "user", "usage": "all" } ], "BOARD_MIG_PARAM": [ { "value": "Custom", "value_src": "user", "resolve_type": "user", "usage": "all" } ], "Component_Name": [ { "value": "Top_mig_7series_1_0", "resolve_type": "user", "usage": "all" } ] }, @@ -1182,7 +1182,7 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "1" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_mig_7series_1_0" } ], + "OUTPUTDIR": [ { "value": "../../../build/my_project.gen/sources_1/ip/Top_mig_7series_1_0" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "../../ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci index b45eca2..e3b1273 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci @@ -5,7 +5,7 @@ "cell_name": "util_ds_buf_0", "component_reference": "xilinx.com:ip:util_ds_buf:2.2", "ip_revision": "29", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_util_ds_buf_0_0", + "gen_directory": "../../../build/my_project.gen/sources_1/ip/Top_util_ds_buf_0_0", "parameters": { "component_parameters": { "C_SIZE": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -48,7 +48,7 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "29" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_util_ds_buf_0_0" } ], + "OUTPUTDIR": [ { "value": "../../../build/my_project.gen/sources_1/ip/Top_util_ds_buf_0_0" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "../../ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci index c9b9c65..31aa2c5 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci @@ -5,7 +5,7 @@ "cell_name": "util_vector_logic_1", "component_reference": "xilinx.com:ip:util_vector_logic:2.0", "ip_revision": "2", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_util_vector_logic_1_3", + "gen_directory": "../../../build/my_project.gen/sources_1/ip/Top_util_vector_logic_1_3", "parameters": { "component_parameters": { "Component_Name": [ { "value": "Top_util_vector_logic_1_3", "resolve_type": "user", "usage": "all" } ], @@ -36,7 +36,7 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "2" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_util_vector_logic_1_3" } ], + "OUTPUTDIR": [ { "value": "../../../build/my_project.gen/sources_1/ip/Top_util_vector_logic_1_3" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "../../ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci index 6292957..913a01a 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci @@ -5,7 +5,7 @@ "cell_name": "util_vector_logic_2", "component_reference": "xilinx.com:ip:util_vector_logic:2.0", "ip_revision": "2", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_util_vector_logic_1_4", + "gen_directory": "../../../build/my_project.gen/sources_1/ip/Top_util_vector_logic_1_4", "parameters": { "component_parameters": { "Component_Name": [ { "value": "Top_util_vector_logic_1_4", "resolve_type": "user", "usage": "all" } ], @@ -36,7 +36,7 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "2" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_util_vector_logic_1_4" } ], + "OUTPUTDIR": [ { "value": "../../../build/my_project.gen/sources_1/ip/Top_util_vector_logic_1_4" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "../../ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci index eece37a..ba35c97 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci @@ -5,7 +5,7 @@ "cell_name": "axi_interconnect_0/xbar", "component_reference": "xilinx.com:ip:axi_crossbar:2.1", "ip_revision": "28", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xbar_0", + "gen_directory": "../../../build/my_project.gen/sources_1/ip/Top_xbar_0", "parameters": { "component_parameters": { "ADDR_RANGES": [ { "value": "1", "value_src": "propagated", "value_permission": "bd_and_user", "resolve_type": "user", "format": "long", "usage": "all" } ], @@ -1259,7 +1259,7 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "28" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xbar_0" } ], + "OUTPUTDIR": [ { "value": "../../../build/my_project.gen/sources_1/ip/Top_xbar_0" } ], "SELECTEDSIMMODEL": [ { "value": "rtl" } ], "SHAREDDIR": [ { "value": "../../ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], @@ -1361,7 +1361,7 @@ "FREQ_HZ": [ { "value": "62500000", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "user", "format": "long", "usage": "all" } ], "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_BUSIF": [ { "value": "M00_AXI:M01_AXI:M02_AXI:M03_AXI:M04_AXI:M05_AXI:M06_AXI:M07_AXI:M08_AXI:M09_AXI:M10_AXI:M11_AXI:M12_AXI:M13_AXI:M14_AXI:M15_AXI:S00_AXI:S01_AXI:S02_AXI:S03_AXI:S04_AXI:S05_AXI:S06_AXI:S07_AXI:S08_AXI:S09_AXI:S10_AXI:S11_AXI:S12_AXI:S13_AXI:S14_AXI:S15_AXI", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "ASSOCIATED_RESET": [ { "value": "ARESETN", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], @@ -1401,7 +1401,7 @@ "NUM_WRITE_OUTSTANDING": [ { "value": "2", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user_prop", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -1474,7 +1474,7 @@ "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -1549,7 +1549,7 @@ "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_ips_inferred": true, "is_static_object": false } ], @@ -1624,7 +1624,7 @@ "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], @@ -1699,7 +1699,7 @@ "NUM_WRITE_OUTSTANDING": [ { "value": "8", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], @@ -1774,7 +1774,7 @@ "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], "MAX_BURST_LENGTH": [ { "value": "32", "value_src": "propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "usage": "simulation.tlm", "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "usage": "simulation.tlm", "is_static_object": false } ], "NUM_READ_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], "NUM_WRITE_THREADS": [ { "value": "1", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "simulation.tlm", "is_static_object": false } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci index ba1035a..2da88d7 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci @@ -5,7 +5,7 @@ "cell_name": "xdma_1", "component_reference": "xilinx.com:ip:xdma:4.1", "ip_revision": "20", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xdma_1_0", + "gen_directory": "../../../build/my_project.gen/sources_1/ip/Top_xdma_1_0", "parameters": { "component_parameters": { "Component_Name": [ { "value": "Top_xdma_1_0", "resolve_type": "user", "usage": "all" } ], @@ -1294,7 +1294,7 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "20" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xdma_1_0" } ], + "OUTPUTDIR": [ { "value": "../../../build/my_project.gen/sources_1/ip/Top_xdma_1_0" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "../../ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_1/Top_xdma_1_1.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_1/Top_xdma_1_1.xci new file mode 100644 index 0000000..c98b6e4 --- /dev/null +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_1/Top_xdma_1_1.xci @@ -0,0 +1,1592 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "Top_xdma_1_1", + "cell_name": "xdma_1", + "component_reference": "xilinx.com:ip:xdma:4.1", + "ip_revision": "20", + "gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xdma_1_1", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "Top_xdma_1_1", "resolve_type": "user", "usage": "all" } ], + "functional_mode": [ { "value": "DMA", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "mode_selection": [ { "value": "Basic", "resolve_type": "user", "usage": "all" } ], + "device_port_type": [ { "value": "PCI_Express_Endpoint_device", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "pcie_blk_locn": [ { "value": "X0Y0", "resolve_type": "user", "usage": "all" } ], + "pl_link_cap_max_link_width": [ { "value": "X1", "resolve_type": "user", "usage": "all" } ], + "pl_link_cap_max_link_speed": [ { "value": "5.0_GT/s", "value_src": "user", "resolve_type": "user", "usage": "all" } ], + "ref_clk_freq": [ { "value": "100_MHz", "resolve_type": "user", "usage": "all" } ], + "drp_clk_sel": [ { "value": "Internal", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "free_run_freq": [ { "value": "100_MHz", "resolve_type": "user", "usage": "all" } ], + "axi_addr_width": [ { "value": "64", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "axi_data_width": [ { "value": "64_bit", "resolve_type": "user", "usage": "all" } ], + "axisten_freq": [ { "value": "62.5", "resolve_type": "user", "usage": "all" } ], + "en_axi_slave_if": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "en_axi_master_if": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "pipe_sim": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "en_ext_ch_gt_drp": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "en_pcie_drp": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "dedicate_perst": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "sys_reset_polarity": [ { "value": "ACTIVE_LOW", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "mcap_enablement": [ { "value": "None", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "mcap_fpga_bitstream_version": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "ext_startup_primitive": [ { "value": "false", "resolve_type": "user", "format": "bool", "enabled": false, "usage": "all" } ], + "enable_code": [ { "value": "0000", "resolve_type": "user", "usage": "all" } ], + "vendor_id": [ { "value": "10EE", "resolve_type": "user", "usage": "all" } ], + "pf0_device_id": [ { "value": "7021", "resolve_type": "user", "usage": "all" } ], + "pf0_revision_id": [ { "value": "00", "resolve_type": "user", "usage": "all" } ], + "pf0_subsystem_vendor_id": [ { "value": "10EE", "resolve_type": "user", "usage": "all" } ], + "pf0_subsystem_id": [ { "value": "0007", "resolve_type": "user", "usage": "all" } ], + "pf0_Use_Class_Code_Lookup_Assistant": [ { "value": "false", "resolve_type": "user", "usage": "all" } ], + "pf0_base_class_menu": [ { "value": "Simple_communication_controllers", "resolve_type": "user", "usage": "all" } ], + "pf0_class_code_base": [ { "value": "07", "resolve_type": "user", "usage": "all" } ], + "pf0_sub_class_interface_menu": [ { "value": "16450_compatible_serial_controller", "resolve_type": "user", "usage": "all" } ], + "pf0_class_code_sub": [ { "value": "00", "resolve_type": "user", "usage": "all" } ], + "pf0_class_code_interface": [ { "value": "01", "resolve_type": "user", "usage": "all" } ], + "pf0_class_code": [ { "value": "070001", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "axilite_master_en": [ { "value": "false", "resolve_type": "user", "usage": "all" } ], + "axilite_master_size": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "axilite_master_scale": [ { "value": "Megabytes", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "xdma_en": [ { "value": "true", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "xdma_size": [ { "value": "64", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "xdma_scale": [ { "value": "Kilobytes", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "axist_bypass_en": [ { "value": "false", "resolve_type": "user", "usage": "all" } ], + "axist_bypass_size": [ { "value": "1", "resolve_type": "user", "format": "long", "enabled": false, "usage": "all" } ], + "axist_bypass_scale": [ { "value": "Megabytes", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "pciebar2axibar_axil_master": [ { "value": "0x00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "pciebar2axibar_xdma": [ { "value": "0x0000000000000000", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "pciebar2axibar_axist_bypass": [ { "value": "0x0000000000000000", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "pf0_interrupt_pin": [ { "value": "INTA", "resolve_type": "user", "usage": "all" } ], + "pf0_msi_enabled": [ { "value": "true", "resolve_type": "user", "usage": "all" } ], + "pf0_msi_cap_multimsgcap": [ { "value": "1_vector", "resolve_type": "user", "usage": "all" } ], + "comp_timeout": [ { "value": "50ms", "resolve_type": "user", "usage": "all" } ], + "timeout0_sel": [ { "value": "14", "resolve_type": "user", "usage": "all" } ], + "timeout1_sel": [ { "value": "15", "resolve_type": "user", "usage": "all" } ], + "timeout_mult": [ { "value": "3", "resolve_type": "user", "usage": "all" } ], + "old_bridge_timeout": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Shared_Logic": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], + "Shared_Logic_Clk": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Shared_Logic_Both": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Shared_Logic_Gtc": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Shared_Logic_Gtc_7xG2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Shared_Logic_Clk_7xG2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "Shared_Logic_Both_7xG2": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "en_transceiver_status_ports": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "xdma_rnum_chnl": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], + "xdma_wnum_chnl": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], + "xdma_axilite_slave": [ { "value": "false", "resolve_type": "user", "usage": "all" } ], + "xdma_num_usr_irq": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], + "xdma_rnum_rids": [ { "value": "32", "resolve_type": "user", "format": "long", "usage": "all" } ], + "xdma_wnum_rids": [ { "value": "16", "resolve_type": "user", "format": "long", "usage": "all" } ], + "SYS_RST_N_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "PCIE_BOARD_INTERFACE": [ { "value": "Custom", "resolve_type": "user", "usage": "all" } ], + "EGW_IS_PARENT_IP": [ { "value": "1", "resolve_type": "user", "usage": "all" } ], + "en_gt_selection": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "select_quad": [ { "value": "GTH_Quad_128", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "RX_PPM_OFFSET": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "RX_SSC_PPM": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "all" } ], + "INS_LOSS_NYQ": [ { "value": "15", "resolve_type": "user", "format": "float", "usage": "all" } ], + "PHY_LP_TXPRESET": [ { "value": "4", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "coreclk_freq": [ { "value": "500", "resolve_type": "user", "usage": "all" } ], + "plltype": [ { "value": "QPLL1", "resolve_type": "user", "usage": "all" } ], + "xdma_axi_intf_mm": [ { "value": "AXI_Memory_Mapped", "resolve_type": "user", "usage": "all" } ], + "xdma_pcie_64bit_en": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "silicon_rev": [ { "value": "Pre-Production", "resolve_type": "user", "usage": "all" } ], + "xdma_dsc_bypass": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "performance": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "pcie_extended_tag": [ { "value": "true", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "rx_detect": [ { "value": "Default", "resolve_type": "user", "usage": "all" } ], + "pf0_link_status_slot_clock_config": [ { "value": "true", "resolve_type": "user", "usage": "all" } ], + "dsc_bypass_rd": [ { "value": "0000", "resolve_type": "user", "usage": "all" } ], + "dsc_bypass_wr": [ { "value": "0000", "resolve_type": "user", "usage": "all" } ], + "xdma_sts_ports": [ { "value": "false", "resolve_type": "user", "format": "bool", "usage": "all" } ], + "pf0_msix_enabled": [ { "value": "false", "resolve_type": "user", "usage": "all" } ], + "pf0_msix_cap_table_size": [ { "value": "000", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "pf0_msix_cap_table_offset": [ { "value": "00000000", "resolve_type": "user", "enabled": false, "usage": "all" } ], + "pf0_msix_cap_table_bir": [ { "value": "BAR_0", "resolve_type": "user", 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"value": "Top_xdma_1_1_axi_aclk", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "CLK": [ { "physical_name": "axi_aclk" } ] + } + }, + "RST.axi_aresetn": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "master", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "axi_aresetn" } ] + } + }, + "RST.sys_rst_n": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "BOARD.ASSOCIATED_PARAM": [ { "value": "SYS_RST_N_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "TYPE": [ { "value": "PCIE_PERST", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "RST": [ { "physical_name": "sys_rst_n" } ] + } + }, + "RST.user_reset": { + "vlnv": "xilinx.com:signal:reset:1.0", + "abstraction_type": "xilinx.com:signal:reset_rtl:1.0", + "mode": "slave", + "parameters": { + "POLARITY": [ { "value": "ACTIVE_HIGH", "value_src": "constant", "usage": "all" } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + } + }, + "M_AXI": { + "vlnv": "xilinx.com:interface:aximm:1.0", + "abstraction_type": "xilinx.com:interface:aximm_rtl:1.0", + "mode": "master", + "address_space_ref": "M_AXI", + "parameters": { + "NUM_READ_OUTSTANDING": [ { "value": "32", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "NUM_WRITE_OUTSTANDING": [ { "value": "16", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ], + "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ], + "HAS_BURST.VALUE_SRC": [ { "value": "CONSTANT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], + "DATA_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "62500000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_1_axi_aclk", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] + }, + "port_maps": { + "ARADDR": [ { "physical_name": "m_axi_araddr" } ], + "ARBURST": [ { "physical_name": "m_axi_arburst" } ], + "ARCACHE": [ { "physical_name": "m_axi_arcache" } ], + "ARID": [ { "physical_name": "m_axi_arid" } ], + "ARLEN": [ { "physical_name": "m_axi_arlen" } ], + "ARLOCK": [ { "physical_name": "m_axi_arlock" } ], + "ARPROT": [ { "physical_name": "m_axi_arprot" } ], + "ARREADY": [ { "physical_name": "m_axi_arready" } ], + "ARSIZE": [ { "physical_name": "m_axi_arsize" } ], + "ARVALID": [ { "physical_name": "m_axi_arvalid" } ], + "AWADDR": [ { "physical_name": "m_axi_awaddr" } ], + "AWBURST": [ { "physical_name": "m_axi_awburst" } ], + "AWCACHE": [ { "physical_name": "m_axi_awcache" } ], + "AWID": [ { "physical_name": "m_axi_awid" } ], + "AWLEN": [ { "physical_name": "m_axi_awlen" } ], + "AWLOCK": [ { "physical_name": "m_axi_awlock" } ], + "AWPROT": [ { "physical_name": "m_axi_awprot" } ], + "AWREADY": [ { "physical_name": "m_axi_awready" } ], + "AWSIZE": [ { "physical_name": "m_axi_awsize" } ], + "AWVALID": [ { "physical_name": "m_axi_awvalid" } ], + "BID": [ { "physical_name": "m_axi_bid" } ], + "BREADY": [ { "physical_name": "m_axi_bready" } ], + "BRESP": [ { "physical_name": "m_axi_bresp" } ], + "BVALID": [ { "physical_name": "m_axi_bvalid" } ], + "RDATA": [ { "physical_name": "m_axi_rdata" } ], + "RID": [ { "physical_name": "m_axi_rid" } ], + "RLAST": [ { "physical_name": "m_axi_rlast" } ], + "RREADY": [ { "physical_name": "m_axi_rready" } ], + "RRESP": [ { "physical_name": "m_axi_rresp" } ], + "RVALID": [ { "physical_name": "m_axi_rvalid" } ], + "WDATA": [ { "physical_name": "m_axi_wdata" } ], + "WLAST": [ { "physical_name": "m_axi_wlast" } ], + "WREADY": [ { "physical_name": "m_axi_wready" } ], + "WSTRB": [ { "physical_name": "m_axi_wstrb" } ], + "WVALID": [ { "physical_name": "m_axi_wvalid" } ] + } + }, + "pcie_cfg_mgmt": { + "vlnv": "xilinx.com:interface:pcie_cfg_mgmt:1.0", + "abstraction_type": "xilinx.com:interface:pcie_cfg_mgmt_rtl:1.0", + "mode": "slave", + "port_maps": { + "ADDR": [ { "physical_name": "cfg_mgmt_addr" } ], + "BYTE_EN": [ { "physical_name": "cfg_mgmt_byte_enable" } ], + "READ_DATA": [ { "physical_name": "cfg_mgmt_read_data" } ], + "READ_EN": [ { "physical_name": "cfg_mgmt_read" } ], + "READ_WRITE_DONE": [ { "physical_name": "cfg_mgmt_read_write_done" } ], + "TYPE1_CFG_REG_ACCESS": [ { "physical_name": "cfg_mgmt_type1_cfg_reg_access" } ], + "WRITE_DATA": [ { "physical_name": "cfg_mgmt_write_data" } ], + "WRITE_EN": [ { "physical_name": "cfg_mgmt_write" } ] + } + }, + "pcie_mgt": { + "vlnv": "xilinx.com:interface:pcie_7x_mgt:1.0", + "abstraction_type": "xilinx.com:interface:pcie_7x_mgt_rtl:1.0", + "mode": "master", + "parameters": { + "BOARD.ASSOCIATED_PARAM": [ { "value": "PCIE_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ] + }, + "port_maps": { + "rxn": [ { "physical_name": "pci_exp_rxn" } ], + "rxp": [ { "physical_name": "pci_exp_rxp" } ], + "txn": [ { "physical_name": "pci_exp_txn" } ], + "txp": [ { "physical_name": "pci_exp_txp" } ] + } + } + }, + "address_spaces": { + "M_AXI": { + "range": "16777216T", + "width": "64" + }, + "M_AXI_LITE": { + "range": "4G", + "width": "32" + }, + "M_AXI_BYPASS": { + "range": "16777216T", + "width": "64" + }, + "M_AXI_B": { + "range": "16777216T", + "width": "64" + } + }, + "memory_maps": { + "S_AXI_LITE": { + "address_blocks": { + "CTL0": { + "base_address": "0", + "range": "65536", + "usage": "memory", + "access": "read-write", + "parameters": { + "OFFSET_BASE_PARAM": [ { "value": "baseaddr" } ], + "OFFSET_HIGH_PARAM": [ { "value": "highaddr" } ] + } + } + } + }, + "S_AXI_B": { + "address_blocks": { + "BAR0": { + "base_address": "0", + "range": "1048576", + "usage": "memory", + "access": "read-write", + "parameters": { + "OFFSET_BASE_PARAM": [ { "value": "axibar_0" } ], + "OFFSET_HIGH_PARAM": [ { "value": "axibar_highaddr_0" } ] + } + } + } + } + } + } + } +} \ No newline at end of file diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci index 0b330b9..be90095 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci @@ -5,7 +5,7 @@ "cell_name": "xlconstant_0", "component_reference": "xilinx.com:ip:xlconstant:1.1", "ip_revision": "7", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xlconstant_0_0", + "gen_directory": "../../../build/my_project.gen/sources_1/ip/Top_xlconstant_0_0", "parameters": { "component_parameters": { "Component_Name": [ { "value": "Top_xlconstant_0_0", "resolve_type": "user", "usage": "all" } ], @@ -35,7 +35,7 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "7" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xlconstant_0_0" } ], + "OUTPUTDIR": [ { "value": "../../../build/my_project.gen/sources_1/ip/Top_xlconstant_0_0" } ], "SELECTEDSIMMODEL": [ { "value": "" } ], "SHAREDDIR": [ { "value": "../../ipshared" } ], "SWVERSION": [ { "value": "2022.2" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_1/Top_xlconstant_0_1.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_1/Top_xlconstant_0_1.xci new file mode 100644 index 0000000..18e6622 --- /dev/null +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_1/Top_xlconstant_0_1.xci @@ -0,0 +1,51 @@ +{ + "schema": "xilinx.com:schema:json_instance:1.0", + "ip_inst": { + "xci_name": "Top_xlconstant_0_1", + "cell_name": "xlconstant_0", + "component_reference": "xilinx.com:ip:xlconstant:1.1", + "ip_revision": "7", + "gen_directory": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xlconstant_0_1", + "parameters": { + "component_parameters": { + "Component_Name": [ { "value": "Top_xlconstant_0_1", "resolve_type": "user", "usage": "all" } ], + "CONST_WIDTH": [ { "value": "1", "resolve_type": "user", "format": "long", "usage": "all" } ], + "CONST_VAL": [ { "value": "1", "resolve_type": "user", "usage": "all" } ] + }, + "model_parameters": { + "CONST_WIDTH": [ { "value": "1", "resolve_type": "generated", "format": "long", "usage": "all" } ], + "CONST_VAL": [ { "value": "0x1", "resolve_type": "generated", "format": "bitString", "usage": "all" } ] + }, + "project_parameters": { + "ARCHITECTURE": [ { "value": "kintex7" } ], + "BASE_BOARD_PART": [ { "value": "" } ], + "BOARD_CONNECTIONS": [ { "value": "" } ], + "DEVICE": [ { "value": "xc7k480t" } ], + "PACKAGE": [ { "value": "ffg1156" } ], + "PREFHDL": [ { "value": "VERILOG" } ], + "SILICON_REVISION": [ { "value": "" } ], + "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], + "SPEEDGRADE": [ { "value": "-2L" } ], + "STATIC_POWER": [ { "value": "" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], + "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], + "USE_RDI_GENERATION": [ { "value": "TRUE" } ] + }, + "runtime_parameters": { + "IPCONTEXT": [ { "value": "IP_Integrator" } ], + "IPREVISION": [ { "value": "7" } ], + "MANAGED": [ { "value": "TRUE" } ], + "OUTPUTDIR": [ { "value": "../../../../../../nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xlconstant_0_1" } ], + "SELECTEDSIMMODEL": [ { "value": "" } ], + "SHAREDDIR": [ { "value": "../../../../../../xc7k480t/nitefury_pcie_xdma_ddr/project/sources/ipshared" } ], + "SWVERSION": [ { "value": "2022.2" } ], + "SYNTHESISFLOW": [ { "value": "GLOBAL" } ] + } + }, + "boundary": { + "ports": { + "dout": [ { "direction": "out", "size_left": "0", "size_right": "0" } ] + } + } + } +} \ No newline at end of file diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci index 74f503e..e1a63c3 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci @@ -5,7 +5,7 @@ "cell_name": "xlconstant_2", "component_reference": "xilinx.com:ip:xlconstant:1.1", "ip_revision": "7", - "gen_directory": "../../../build/nitefury_xdma_ddr_github.gen/sources_1/bd/Top/ip/Top_xlconstant_2_0", + "gen_directory": "../../../build/my_project.gen/sources_1/ip/Top_xlconstant_2_0", "parameters": { "component_parameters": { "Component_Name": [ { "value": "Top_xlconstant_2_0", "resolve_type": "user", "usage": "all" } ], @@ -35,7 +35,7 @@ "IPCONTEXT": [ { "value": "IP_Integrator" } ], "IPREVISION": [ { "value": "7" } ], "MANAGED": [ { "value": "TRUE" } ], - "OUTPUTDIR": [ { "value": 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