From d1ce19df57d5df290fc9301f88fe713d4d98b158 Mon Sep 17 00:00:00 2001 From: Colin <> Date: Sun, 11 May 2025 00:07:51 +0800 Subject: [PATCH] Update nitefury_pcie_xdma_ddr. --- nitefury_pcie_xdma_ddr/.gitignore | 2 +- nitefury_pcie_xdma_ddr/project/o.tcl | 22 +++++++++++++++++-- .../ip/Top_auto_cc_1/Top_auto_cc_1.xci | 2 +- .../ip/Top_auto_cc_2/Top_auto_cc_2.xci | 2 +- .../ip/Top_auto_cc_3/Top_auto_cc_3.xci | 2 +- .../ip/Top_auto_ds_0/Top_auto_ds_0.xci | 2 +- .../ip/Top_auto_ds_1/Top_auto_ds_1.xci | 2 +- .../ip/Top_auto_ds_2/Top_auto_ds_2.xci | 2 +- .../ip/Top_auto_pc_0/Top_auto_pc_0.xci | 2 +- .../ip/Top_auto_pc_1/Top_auto_pc_1.xci | 2 +- .../ip/Top_auto_us_0/Top_auto_us_0.xci | 2 +- .../Top_axi_bram_ctrl_0_0.xci | 2 +- .../Top_axi_interconnect_0_0.xci | 2 +- .../Top_blk_mem_gen_0_0.xci | 2 +- .../Top_mig_7series_1_0.xci | 2 +- .../Top_util_ds_buf_0_0.xci | 2 +- .../Top_util_vector_logic_1_3.xci | 2 +- .../Top_util_vector_logic_1_4.xci | 2 +- .../sources/ip/Top_xbar_0/Top_xbar_0.xci | 2 +- .../sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci | 2 +- .../Top_xlconstant_0_0/Top_xlconstant_0_0.xci | 2 +- .../Top_xlconstant_2_0/Top_xlconstant_2_0.xci | 2 +- 22 files changed, 41 insertions(+), 23 deletions(-) diff --git a/nitefury_pcie_xdma_ddr/.gitignore b/nitefury_pcie_xdma_ddr/.gitignore index b195813..efe9a88 100644 --- a/nitefury_pcie_xdma_ddr/.gitignore +++ b/nitefury_pcie_xdma_ddr/.gitignore @@ -1 +1 @@ -nitefury_xdma_ddr \ No newline at end of file +nitefury_xdma_ddr_github \ No newline at end of file diff --git a/nitefury_pcie_xdma_ddr/project/o.tcl b/nitefury_pcie_xdma_ddr/project/o.tcl index 0dcdde3..ac1ae72 100644 --- a/nitefury_pcie_xdma_ddr/project/o.tcl +++ b/nitefury_pcie_xdma_ddr/project/o.tcl @@ -15,11 +15,29 @@ create_project my_project ./my_project -part xc7k480tffg1156-2L -force # add_file ../uart_inst.xci add_file ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci +add_file ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci + +generate_target all [get_ips Top_axi_bram_ctrl_0_0] +generate_target all [get_ips Top_xlconstant_2_0] + + + +# add_file ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci +# add_file ../sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci +# add_file ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci +# add_file ../sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci +# add_file ../sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci +# add_file ../sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci +# add_file ../sources/ip/Top_xbar_0/Top_xbar_0.xci +# add_file ../sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci +# add_file ../sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci +# add_file ../sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci +# add_file ../sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci + -# 生成IP输出文件（RTL、约束、网表等） -generate_target -force all [get_ips Top_axi_bram_ctrl_0_0] synth_ip [get_ips Top_axi_bram_ctrl_0_0] +synth_ip [get_ips Top_xlconstant_2_0] # write_ip_tcl -help # write_ip_tcl -force -verbose [get_ips uart_inst] ./uart_inst.tcl \ No newline at end of file diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_1/Top_auto_cc_1.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_1/Top_auto_cc_1.xci index 0dd49c7..c6e7d52 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_1/Top_auto_cc_1.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_1/Top_auto_cc_1.xci @@ -46,7 +46,7 @@ "ARCHITECTURE": [ { "value": "kintex7" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7k480ti" } ], + "DEVICE": [ { "value": "xc7k480t" } ], "PACKAGE": [ { "value": "ffg1156" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_2/Top_auto_cc_2.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_2/Top_auto_cc_2.xci index 73fcb12..708424a 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_2/Top_auto_cc_2.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_2/Top_auto_cc_2.xci @@ -46,7 +46,7 @@ "ARCHITECTURE": [ { "value": "kintex7" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7k480ti" } ], + "DEVICE": [ { "value": "xc7k480t" } ], "PACKAGE": [ { "value": "ffg1156" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_3/Top_auto_cc_3.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_3/Top_auto_cc_3.xci index 1fc87fc..3b687bf 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_3/Top_auto_cc_3.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_cc_3/Top_auto_cc_3.xci @@ -46,7 +46,7 @@ "ARCHITECTURE": [ { "value": "kintex7" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7k480ti" } ], + "DEVICE": [ { "value": "xc7k480t" } ], "PACKAGE": [ { "value": "ffg1156" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_0/Top_auto_ds_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_0/Top_auto_ds_0.xci index 1f0cda3..c518140 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_0/Top_auto_ds_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_0/Top_auto_ds_0.xci @@ -44,7 +44,7 @@ "ARCHITECTURE": [ { "value": "kintex7" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7k480ti" } ], + "DEVICE": [ { "value": "xc7k480t" } ], "PACKAGE": [ { "value": "ffg1156" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_1/Top_auto_ds_1.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_1/Top_auto_ds_1.xci index 25ce4ec..09d2908 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_1/Top_auto_ds_1.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_1/Top_auto_ds_1.xci @@ -44,7 +44,7 @@ "ARCHITECTURE": [ { "value": "kintex7" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7k480ti" } ], + "DEVICE": [ { "value": "xc7k480t" } ], "PACKAGE": [ { "value": "ffg1156" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_2/Top_auto_ds_2.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_2/Top_auto_ds_2.xci index d5e8866..034b28c 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_2/Top_auto_ds_2.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_ds_2/Top_auto_ds_2.xci @@ -44,7 +44,7 @@ "ARCHITECTURE": [ { "value": "kintex7" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7k480ti" } ], + "DEVICE": [ { "value": "xc7k480t" } ], "PACKAGE": [ { "value": "ffg1156" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_pc_0/Top_auto_pc_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_pc_0/Top_auto_pc_0.xci index 921789b..49d0db4 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_pc_0/Top_auto_pc_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_pc_0/Top_auto_pc_0.xci @@ -44,7 +44,7 @@ "ARCHITECTURE": [ { "value": "kintex7" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7k480ti" } ], + "DEVICE": [ { "value": "xc7k480t" } ], "PACKAGE": [ { "value": "ffg1156" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_pc_1/Top_auto_pc_1.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_pc_1/Top_auto_pc_1.xci index 59fab92..d334106 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_pc_1/Top_auto_pc_1.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_pc_1/Top_auto_pc_1.xci @@ -44,7 +44,7 @@ "ARCHITECTURE": [ { "value": "kintex7" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7k480ti" } ], + "DEVICE": [ { "value": "xc7k480t" } ], "PACKAGE": [ { "value": "ffg1156" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_us_0/Top_auto_us_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_us_0/Top_auto_us_0.xci index 4693fbc..ccfba49 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_us_0/Top_auto_us_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_auto_us_0/Top_auto_us_0.xci @@ -44,7 +44,7 @@ "ARCHITECTURE": [ { "value": "kintex7" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7k480ti" } ], + "DEVICE": [ { "value": "xc7k480t" } ], "PACKAGE": [ { "value": "ffg1156" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci index 8c2a2e8..82239e9 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci @@ -47,7 +47,7 @@ "ARCHITECTURE": [ { "value": "kintex7" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7k480ti" } ], + "DEVICE": [ { "value": "xc7k480t" } ], "PACKAGE": [ { "value": "ffg1156" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci index 89a6957..55728f4 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci @@ -328,7 +328,7 @@ "ARCHITECTURE": [ { "value": "kintex7" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7k480ti" } ], + "DEVICE": [ { "value": "xc7k480t" } ], "PACKAGE": [ { "value": "ffg1156" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci index 35c0ad2..59eff7d 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci @@ -162,7 +162,7 @@ "ARCHITECTURE": [ { "value": "kintex7" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7k480ti" } ], + "DEVICE": [ { "value": "xc7k480t" } ], "PACKAGE": [ { "value": "ffg1156" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci index 59946e8..1de546c 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci @@ -1167,7 +1167,7 @@ "ARCHITECTURE": [ { "value": "kintex7" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7k480ti" } ], + "DEVICE": [ { "value": "xc7k480t" } ], "PACKAGE": [ { "value": "ffg1156" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci index 3ceac93..5405fc3 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci @@ -33,7 +33,7 @@ "ARCHITECTURE": [ { "value": "kintex7" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7k480ti" } ], + "DEVICE": [ { "value": "xc7k480t" } ], "PACKAGE": [ { "value": "ffg1156" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci index 9e591a9..82771c7 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci @@ -21,7 +21,7 @@ "ARCHITECTURE": [ { "value": "kintex7" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7k480ti" } ], + "DEVICE": [ { "value": "xc7k480t" } ], "PACKAGE": [ { "value": "ffg1156" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci index 03f47fc..344f059 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci @@ -21,7 +21,7 @@ "ARCHITECTURE": [ { "value": "kintex7" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7k480ti" } ], + "DEVICE": [ { "value": "xc7k480t" } ], "PACKAGE": [ { "value": "ffg1156" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci index 071c042..12efc03 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci @@ -1244,7 +1244,7 @@ "ARCHITECTURE": [ { "value": "kintex7" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7k480ti" } ], + "DEVICE": [ { "value": "xc7k480t" } ], "PACKAGE": [ { "value": "ffg1156" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci index fdf4b6b..dab91b3 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci @@ -1279,7 +1279,7 @@ "ARCHITECTURE": [ { "value": "kintex7" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7k480ti" } ], + "DEVICE": [ { "value": "xc7k480t" } ], "PACKAGE": [ { "value": "ffg1156" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci index 4d3010b..361a6fb 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci @@ -20,7 +20,7 @@ "ARCHITECTURE": [ { "value": "kintex7" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7k480ti" } ], + "DEVICE": [ { "value": "xc7k480t" } ], "PACKAGE": [ { "value": "ffg1156" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ], diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci index eab826f..58039cc 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci @@ -20,7 +20,7 @@ "ARCHITECTURE": [ { "value": "kintex7" } ], "BASE_BOARD_PART": [ { "value": "" } ], "BOARD_CONNECTIONS": [ { "value": "" } ], - "DEVICE": [ { "value": "xc7k480ti" } ], + "DEVICE": [ { "value": "xc7k480t" } ], "PACKAGE": [ { "value": "ffg1156" } ], "PREFHDL": [ { "value": "VERILOG" } ], "SILICON_REVISION": [ { "value": "" } ],