From e8cf5bf65e9f5005d99af569fdaa46fbd52e825a Mon Sep 17 00:00:00 2001 From: Colin <> Date: Sun, 11 May 2025 16:27:43 +0800 Subject: [PATCH] Update nitefury_pcie_xdma_ddr/project --- nitefury_pcie_xdma_ddr/project/o.tcl | 112 ++++++++++++++---- .../project/sources/Top.bda | 104 ++-------------- .../Top_axi_bram_ctrl_0_0.xci | 2 +- .../Top_axi_interconnect_0_0.xci | 2 +- .../Top_blk_mem_gen_0_0.xci | 4 +- .../Top_mig_7series_1_0.xci | 2 +- .../sources/ip/Top_mig_7series_1_0/mig_a.prj | 2 +- .../sources/ip/Top_mig_7series_1_0/mig_b.prj | 2 +- .../Top_util_ds_buf_0_0.xci | 2 +- .../Top_util_vector_logic_1_3.xci | 2 +- .../Top_util_vector_logic_1_4.xci | 2 +- .../sources/ip/Top_xbar_0/Top_xbar_0.xci | 2 +- .../sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci | 78 ++++++------ .../Top_xlconstant_0_0/Top_xlconstant_0_0.xci | 2 +- .../Top_xlconstant_2_0/Top_xlconstant_2_0.xci | 2 +- 15 files changed, 150 insertions(+), 170 deletions(-) diff --git a/nitefury_pcie_xdma_ddr/project/o.tcl b/nitefury_pcie_xdma_ddr/project/o.tcl index ac1ae72..e5deaf9 100644 --- a/nitefury_pcie_xdma_ddr/project/o.tcl +++ b/nitefury_pcie_xdma_ddr/project/o.tcl @@ -1,9 +1,13 @@ -# 创建Vivado工程（非图形界面模式） -create_project my_project ./my_project -part xc7k480tffg1156-2L -force + + +create_project -force my_project +set_property SOURCE_MGMT_MODE None [current_project] +set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1] +set_property PART xc7k480tffg1156-2L [current_project] + # # 生成IP核（以AXI UART Lite为例） # create_ip -name axi_uartlite -vendor xilinx.com -library ip -version 2.0 -module_name uart_inst - # # 配置IP参数 # set_property -dict [list \ # CONFIG.C_BAUDRATE {115200} \ @@ -13,31 +17,95 @@ create_project my_project ./my_project -part xc7k480tffg1156-2L -force # ] [get_ips uart_inst] +create_ip -name axi_interconnect -vendor xilinx.com -library ip -version 1.7 -module_name axi_interconnect_0 +generate_target -force all [get_ips axi_interconnect_0] +synth_ip [get_ips axi_interconnect_0] + + + + # add_file ../uart_inst.xci -add_file ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci -add_file ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci +# import_ip ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci +# import_ip ../sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci +# import_ip ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci +import_ip ../sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci -generate_target all [get_ips Top_axi_bram_ctrl_0_0] -generate_target all [get_ips Top_xlconstant_2_0] +# upgrade_ip [get_ips Top_axi_interconnect_0_0] +# # set_property GENERATE_SYNTH_CHECKPOINT true Top_axi_interconnect_0_0 +# generate_target -force all [get_ips Top_axi_interconnect_0_0] +# synth_ip [get_ips Top_axi_interconnect_0_0] +# import_ip ../sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci +# import_ip ../sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci +# import_ip ../sources/ip/Top_xbar_0/Top_xbar_0.xci +# import_ip ../sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci +# import_ip ../sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci +# import_ip ../sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci +# import_ip ../sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci -# add_file ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci -# add_file ../sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci -# add_file ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci -# add_file ../sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci -# add_file ../sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci -# add_file ../sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci -# add_file ../sources/ip/Top_xbar_0/Top_xbar_0.xci -# add_file ../sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci -# add_file ../sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci -# add_file ../sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci -# add_file ../sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci +# generate_target all [get_ips Top_axi_bram_ctrl_0_0] +# generate_target all [get_ips Top_util_vector_logic_1_3] +# generate_target all [get_ips Top_xlconstant_2_0] +# generate_target all [get_ips Top_axi_interconnect_0_0] +# generate_target all [get_ips Top_util_vector_logic_1_4] +# generate_target all [get_ips Top_blk_mem_gen_0_0] +# generate_target all [get_ips Top_xbar_0] +# generate_target all [get_ips Top_mig_7series_1_0] +# generate_target all [get_ips Top_xdma_1_0] +# generate_target all [get_ips Top_util_ds_buf_0_0] +# generate_target all [get_ips Top_xlconstant_0_0] + +# synth_ip [get_ips Top_axi_bram_ctrl_0_0] +# synth_ip [get_ips Top_util_vector_logic_1_3] +# synth_ip [get_ips Top_xlconstant_2_0] +# synth_ip [get_ips Top_axi_interconnect_0_0] +# synth_ip [get_ips Top_util_vector_logic_1_4] +# synth_ip [get_ips Top_blk_mem_gen_0_0] +# synth_ip [get_ips Top_xbar_0] +# synth_ip [get_ips Top_mig_7series_1_0] +# synth_ip [get_ips Top_xdma_1_0] +# synth_ip [get_ips Top_util_ds_buf_0_0] +# synth_ip [get_ips Top_xlconstant_0_0] +# add_file ../sources/Top_wrapper.v +# add_file ../sources/Top.bd + +# add_file -fileset constrs_1 ../normal.xdc + +# set_property TOP Top_wrapper [current_fileset] + +# set_property GENERIC { FREQ=100000000 SECS=1 } -objects [get_filesets sources_1] + +# close_project + +# open_project my_project + +# # Synthesis + +# # PRESYNTH +# # set_property DESIGN_MODE GateLvl [current_fileset] +# reset_run synth_1 +# launch_runs synth_1 +# wait_on_run synth_1 +# #report_property [get_runs synth_1] +# if { [get_property STATUS [get_runs synth_1]] ne "synth_design Complete!" } { exit 1 } + +# # Place and Route + +# reset_run impl_1 +# launch_runs impl_1 +# wait_on_run impl_1 +# #report_property [get_runs impl_1] +# if { [get_property STATUS [get_runs impl_1]] ne "route_design Complete!" } { exit 1 } + +# # Bitstream generation + +# open_run impl_1 +# # write_bitstream -force xdma480t +# # write_debug_probes -force -quiet xdma480t.ltx + +# close_project -synth_ip [get_ips Top_axi_bram_ctrl_0_0] -synth_ip [get_ips Top_xlconstant_2_0] -# write_ip_tcl -help -# write_ip_tcl -force -verbose [get_ips uart_inst] ./uart_inst.tcl \ No newline at end of file diff --git a/nitefury_pcie_xdma_ddr/project/sources/Top.bda b/nitefury_pcie_xdma_ddr/project/sources/Top.bda index 035e9db..7d3c147 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/Top.bda +++ b/nitefury_pcie_xdma_ddr/project/sources/Top.bda @@ -23,63 +23,6 @@ - 0x0000000000000000 - C_BASEADDR - 0x000000007FFFFFFF - C_HIGHADDR - M_AXI - /xdma_1 - M_AXI - SEG_mig_7series_1_c1_memaddr - xilinx.com:ip:xdma:4.1 - both - /mig_7series_1 - S1_AXI - c1_memmap - c1_memaddr - xilinx.com:ip:mig_7series:4.2 - memory - AC - - - 0x0000000100100000 - C_BASEADDR - 0x00000001001FFFFF - C_HIGHADDR - M_AXI - /xdma_1 - M_AXI - SEG_mig_7series_1_c1_s_axi_ctrl_memaddr - xilinx.com:ip:xdma:4.1 - both - /mig_7series_1 - S1_AXI_CTRL - c1_s_axi_ctrl_memmap - c1_s_axi_ctrl_memaddr - xilinx.com:ip:mig_7series:4.2 - register - AC - - - 0x0000000100000000 - C_BASEADDR - 0x00000001000FFFFF - C_HIGHADDR - M_AXI - /xdma_1 - M_AXI - SEG_mig_7series_1_c0_s_axi_ctrl_memaddr - xilinx.com:ip:xdma:4.1 - both - /mig_7series_1 - S0_AXI_CTRL - c0_s_axi_ctrl_memmap - c0_s_axi_ctrl_memaddr - xilinx.com:ip:mig_7series:4.2 - register - AC - - 0x0000000200000000 C_S_AXI_BASEADDR 0x0000000200001FFF @@ -97,54 +40,23 @@ memory AC - - 0x0000000080000000 - C_BASEADDR - 0x00000000FFFFFFFF - C_HIGHADDR - M_AXI - /xdma_1 - M_AXI - SEG_mig_7series_1_c0_memaddr - xilinx.com:ip:xdma:4.1 - both - /mig_7series_1 - S0_AXI - c0_memmap - c0_memaddr - xilinx.com:ip:mig_7series:4.2 - memory - AC + + Top + BC - + active 2 PM - + 2 Top VR - - Top - BC - - - - - 2 - - - 2 - - - 2 - - - 2 - - + + + 2 diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci index 82239e9..dda03df 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci @@ -54,7 +54,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci index 55728f4..2782815 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci @@ -335,7 +335,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci index 59eff7d..1f62790 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci @@ -156,7 +156,7 @@ "C_DISABLE_WARN_BHV_RANGE": [ { "value": "0", "resolve_type": "generated", "format": "long", "usage": "all" } ], "C_COUNT_36K_BRAM": [ { "value": "2", "resolve_type": "generated", "usage": "all" } ], "C_COUNT_18K_BRAM": [ { "value": "0", "resolve_type": "generated", "usage": "all" } ], - "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 5.10587 mW", "resolve_type": "generated", "usage": "all" } ] + "C_EST_POWER_SUMMARY": [ { "value": "Estimated Power for IP : 5.3746 mW", "resolve_type": "generated", "usage": "all" } ] }, "project_parameters": { "ARCHITECTURE": [ { "value": "kintex7" } ], @@ -169,7 +169,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci index 1de546c..5036b3f 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci @@ -1174,7 +1174,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/mig_a.prj b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/mig_a.prj index ab244a4..796d3d5 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/mig_a.prj +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/mig_a.prj @@ -19,7 +19,7 @@ Enabled - xc7k480ti-ffg1156/-2L + xc7k480t-ffg1156/-2L 4.2 diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/mig_b.prj b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/mig_b.prj index f86087e..9fbb15e 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/mig_b.prj +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_mig_7series_1_0/mig_b.prj @@ -19,7 +19,7 @@ Enabled - xc7k480ti-ffg1156/-2L + xc7k480t-ffg1156/-2L 4.2 diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci index 5405fc3..b45eca2 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci @@ -40,7 +40,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci index 82771c7..c9b9c65 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci @@ -28,7 +28,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci index 344f059..6292957 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci @@ -28,7 +28,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci index 12efc03..eece37a 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xbar_0/Top_xbar_0.xci @@ -1251,7 +1251,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci index dab91b3..ba1035a 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci @@ -1286,7 +1286,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, @@ -1366,13 +1366,13 @@ "abstraction_type": "xilinx.com:signal:clock_rtl:1.0", "mode": "slave", "parameters": { - "FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_util_ds_buf_0_0_IBUF_OUT", "value_src": "default_prop", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_BUSIF": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_RESET": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "100000000", "value_src": "ip_propagated", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_util_ds_buf_0_0_IBUF_OUT", "value_src": "default_prop", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_BUSIF": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_RESET": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { @@ -1387,10 +1387,10 @@ "ASSOCIATED_BUSIF": [ { "value": "M_AXI:S_AXI_B:M_AXI_LITE:S_AXI_LITE:M_AXI_BYPASS:M_AXI_B:S_AXIS_C2H_0:S_AXIS_C2H_1:S_AXIS_C2H_2:S_AXIS_C2H_3:M_AXIS_H2C_0:M_AXIS_H2C_1:M_AXIS_H2C_2:M_AXIS_H2C_3:sc0_ats_m_axis_cq:sc0_ats_m_axis_rc:sc0_ats_s_axis_cc:sc0_ats_s_axis_rq:sc1_ats_m_axis_cq:sc1_ats_m_axis_rc:sc1_ats_s_axis_cc:sc1_ats_s_axis_rq:cxs_tx:cxs_rx", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], "ASSOCIATED_RESET": [ { "value": "axi_aresetn", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], "FREQ_HZ": [ { "value": "62500000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "usage": "all" } ], - "FREQ_TOLERANCE_HZ": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "ASSOCIATED_PORT": [ { "value": "", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_TOLERANCE_HZ": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "ASSOCIATED_PORT": [ { "value": "", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { @@ -1416,7 +1416,7 @@ "parameters": { "BOARD.ASSOCIATED_PARAM": [ { "value": "SYS_RST_N_BOARD_INTERFACE", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], "TYPE": [ { "value": "PCIE_PERST", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], - "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "POLARITY": [ { "value": "ACTIVE_LOW", "value_src": "user", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { @@ -1443,32 +1443,32 @@ "SUPPORTS_NARROW_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ], "HAS_BURST": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "format": "long", "usage": "all" } ], "HAS_BURST.VALUE_SRC": [ { "value": "CONSTANT", "value_src": "constant", "value_permission": "bd", "usage": "all" } ], - "DATA_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "FREQ_HZ": [ { "value": "62500000", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ID_WIDTH": [ { "value": "4", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ADDR_WIDTH": [ { "value": "64", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "WUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "RUSER_WIDTH": [ { "value": "0", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_LOCK": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_PROT": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_CACHE": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_QOS": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_REGION": [ { "value": "0", "value_src": "constant", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_BRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "HAS_RRESP": [ { "value": "1", "value_src": "auto", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "MAX_BURST_LENGTH": [ { "value": "256", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "PHASE": [ { "value": "0.0", "value_permission": "bd", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], - "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "value_permission": "bd", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], - "NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "RUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], - "WUSER_BITS_PER_BYTE": [ { "value": "0", "value_permission": "bd", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "DATA_WIDTH": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PROTOCOL": [ { "value": "AXI4", "value_src": "auto", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "FREQ_HZ": [ { "value": "62500000", "value_src": "user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ID_WIDTH": [ { "value": "4", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ADDR_WIDTH": [ { "value": "64", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "AWUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "ARUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_WIDTH": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_WIDTH": [ { "value": "0", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "BUSER_WIDTH": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "READ_WRITE_MODE": [ { "value": "READ_WRITE", "value_src": "auto", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_LOCK": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_PROT": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_CACHE": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_QOS": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_REGION": [ { "value": "0", "value_src": "constant", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_WSTRB": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_BRESP": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "HAS_RRESP": [ { "value": "1", "value_src": "auto", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "MAX_BURST_LENGTH": [ { "value": "256", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "PHASE": [ { "value": "0.0", "resolve_type": "generated", "format": "float", "is_ips_inferred": true, "is_static_object": false } ], + "CLK_DOMAIN": [ { "value": "Top_xdma_1_0_axi_aclk", "resolve_type": "generated", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_READ_THREADS": [ { "value": "1", "value_src": "user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "NUM_WRITE_THREADS": [ { "value": "1", "value_src": "user", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "RUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], + "WUSER_BITS_PER_BYTE": [ { "value": "0", "resolve_type": "generated", "format": "long", "is_ips_inferred": true, "is_static_object": false } ], "INSERT_VIP": [ { "value": "0", "resolve_type": "user", "format": "long", "usage": "simulation.rtl", "is_ips_inferred": true, "is_static_object": false } ] }, "port_maps": { diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci index 361a6fb..0b330b9 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci @@ -27,7 +27,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] }, diff --git a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci index 58039cc..74f503e 100644 --- a/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci +++ b/nitefury_pcie_xdma_ddr/project/sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci @@ -27,7 +27,7 @@ "SIMULATOR_LANGUAGE": [ { "value": "MIXED" } ], "SPEEDGRADE": [ { "value": "-2L" } ], "STATIC_POWER": [ { "value": "" } ], - "TEMPERATURE_GRADE": [ { "value": "I" } ], + "TEMPERATURE_GRADE": [ { "value": "E" } ], "USE_RDI_CUSTOMIZATION": [ { "value": "TRUE" } ], "USE_RDI_GENERATION": [ { "value": "TRUE" } ] },