diff --git a/constraints/MEMORY_CH0.ucf b/constraints/MEMORY_CH0.ucf new file mode 100644 index 0000000..25d4bbb --- /dev/null +++ b/constraints/MEMORY_CH0.ucf @@ -0,0 +1,117 @@ +NET "ddr3_dq[0]" LOC = "AG17" | ; +NET "ddr3_dq[1]" LOC = "AG16" | ; +NET "ddr3_dq[2]" LOC = "AH17" | ; +NET "ddr3_dq[3]" LOC = "AJ19" | ; +NET "ddr3_dq[4]" LOC = "AH18" | ; +NET "ddr3_dq[5]" LOC = "AH19" | ; +NET "ddr3_dq[6]" LOC = "AJ16" | ; +NET "ddr3_dq[7]" LOC = "AJ17" | ; +NET "ddr3_dq[8]" LOC = "AL20" | ; +NET "ddr3_dq[9]" LOC = "AN17" | ; +NET "ddr3_dq[10]" LOC = "AL19" | ; +NET "ddr3_dq[11]" LOC = "AM16" | ; +NET "ddr3_dq[12]" LOC = "AL18" | ; +NET "ddr3_dq[13]" LOC = "AL16" | ; +NET "ddr3_dq[14]" LOC = "AM20" | ; +NET "ddr3_dq[15]" LOC = "AN18" | ; +NET "ddr3_dq[16]" LOC = "AL23" | ; +NET "ddr3_dq[17]" LOC = "AN20" | ; +NET "ddr3_dq[18]" LOC = "AK23" | ; +NET "ddr3_dq[19]" LOC = "AP19" | ; +NET "ddr3_dq[20]" LOC = "AN22" | ; +NET "ddr3_dq[21]" LOC = "AN19" | ; +NET "ddr3_dq[22]" LOC = "AM22" | ; +NET "ddr3_dq[23]" LOC = "AP20" | ; +NET "ddr3_dq[24]" LOC = "AJ21" | ; +NET "ddr3_dq[25]" LOC = "AH22" | ; +NET "ddr3_dq[26]" LOC = "AK21" | ; +NET "ddr3_dq[27]" LOC = "AG21" | ; +NET "ddr3_dq[28]" LOC = "AG22" | ; +NET "ddr3_dq[29]" LOC = "AG20" | ; +NET "ddr3_dq[30]" LOC = "AH23" | ; +NET "ddr3_dq[31]" LOC = "AG23" | ; +NET "ddr3_dq[32]" LOC = "AJ32" | ; +NET "ddr3_dq[33]" LOC = "AK32" | ; +NET "ddr3_dq[34]" LOC = "AK31" | ; +NET "ddr3_dq[35]" LOC = "AL30" | ; +NET "ddr3_dq[36]" LOC = "AL34" | ; +NET "ddr3_dq[37]" LOC = "AL31" | ; +NET "ddr3_dq[38]" LOC = "AK34" | ; +NET "ddr3_dq[39]" LOC = "AL29" | ; +NET "ddr3_dq[40]" LOC = "AJ34" | ; +NET "ddr3_dq[41]" LOC = "AH32" | ; +NET "ddr3_dq[42]" LOC = "AJ30" | ; +NET "ddr3_dq[43]" LOC = "AH34" | ; +NET "ddr3_dq[44]" LOC = "AF31" | ; +NET "ddr3_dq[45]" LOC = "AG30" | ; +NET "ddr3_dq[46]" LOC = "AG31" | ; +NET "ddr3_dq[47]" LOC = "AF30" | ; +NET "ddr3_dq[48]" LOC = "AE32" | ; +NET "ddr3_dq[49]" LOC = "AC33" | ; +NET "ddr3_dq[50]" LOC = "AF33" | ; +NET "ddr3_dq[51]" LOC = "AC32" | ; +NET "ddr3_dq[52]" LOC = "AD34" | ; +NET "ddr3_dq[53]" LOC = "AC34" | ; +NET "ddr3_dq[54]" LOC = "AE33" | ; +NET "ddr3_dq[55]" LOC = "AE31" | ; +NET "ddr3_dq[56]" LOC = "AE26" | ; +NET "ddr3_dq[57]" LOC = "AF29" | ; +NET "ddr3_dq[58]" LOC = "AE24" | ; +NET "ddr3_dq[59]" LOC = "AF28" | ; +NET "ddr3_dq[60]" LOC = "AF24" | ; +NET "ddr3_dq[61]" LOC = "AG25" | ; +NET "ddr3_dq[62]" LOC = "AF26" | ; +NET "ddr3_dq[63]" LOC = "AF25" | ; +NET "ddr3_dq[64]" LOC = "AN34" | ; +NET "ddr3_dq[65]" LOC = "AP30" | ; +NET "ddr3_dq[66]" LOC = "AM33" | ; +NET "ddr3_dq[67]" LOC = "AN29" | ; +NET "ddr3_dq[68]" LOC = "AP32" | ; +NET "ddr3_dq[69]" LOC = "AP29" | ; +NET "ddr3_dq[70]" LOC = "AM31" | ; +NET "ddr3_dq[71]" LOC = "AP31" | ; +NET "ddr3_dqs_p[0]" LOC = "AK16" | ; +NET "ddr3_dqs_n[0]" LOC = "AK17" | ; +NET "ddr3_dqs_p[1]" LOC = "AM17" | ; +NET "ddr3_dqs_n[1]" LOC = "AM18" | ; +NET "ddr3_dqs_p[2]" LOC = "AP21" | ; +NET "ddr3_dqs_n[2]" LOC = "AP22" | ; +NET "ddr3_dqs_p[3]" LOC = "AH20" | ; +NET "ddr3_dqs_n[3]" LOC = "AJ20" | ; +NET "ddr3_dqs_p[4]" LOC = "AK33" | ; +NET "ddr3_dqs_n[4]" LOC = "AL33" | ; +NET "ddr3_dqs_p[5]" LOC = "AG33" | ; +NET "ddr3_dqs_n[5]" LOC = "AH33" | ; +NET "ddr3_dqs_p[6]" LOC = "AE34" | ; +NET "ddr3_dqs_n[6]" LOC = "AF34" | ; +NET "ddr3_dqs_p[7]" LOC = "AE27" | ; +NET "ddr3_dqs_n[7]" LOC = "AE28" | ; +NET "ddr3_dqs_p[8]" LOC = "AN32" | ; +NET "ddr3_dqs_n[8]" LOC = "AP33" | ; +NET "ddr3_addr[0]" LOC = "AK27" | ; +NET "ddr3_addr[1]" LOC = "AN23" | ; +NET "ddr3_addr[2]" LOC = "AL24" | ; +NET "ddr3_addr[3]" LOC = "AK26" | ; +NET "ddr3_addr[4]" LOC = "AH24" | ; +NET "ddr3_addr[5]" LOC = "AH25" | ; +NET "ddr3_addr[6]" LOC = "AL26" | ; +NET "ddr3_addr[7]" LOC = "AJ24" | ; +NET "ddr3_addr[8]" LOC = "AJ25" | ; +NET "ddr3_addr[9]" LOC = "AM23" | ; +NET "ddr3_addr[10]" LOC = "AL28" | ; +NET "ddr3_addr[11]" LOC = "AL25" | ; +NET "ddr3_addr[12]" LOC = "AM25" | ; +NET "ddr3_addr[13]" LOC = "AK24" | ; +NET "ddr3_addr[14]" LOC = "AM27" | ; +NET "ddr3_ba[0]" LOC = "AM26" | ; +NET "ddr3_ba[1]" LOC = "AP24" | ; +NET "ddr3_ba[2]" LOC = "AN28" | ; +NET "ddr3_cas_n" LOC = "AP26" | ; +NET "ddr3_ck_n[0]" LOC = "AP25" | ; +NET "ddr3_ck_p[0]" LOC = "AN25" | ; +NET "ddr3_cke[0]" LOC = "AP27" | ; +NET "ddr3_cs_n[0]" LOC = "AK28" | ; +NET "ddr3_odt[0]" LOC = "AK29" | ; +NET "ddr3_ras_n" LOC = "AJ29" | ; +NET "ddr3_reset_n" LOC = "AD31" | ; +NET "ddr3_we_n" LOC = "AN27" | ; diff --git a/constraints/MEMORY_CH1.ucf b/constraints/MEMORY_CH1.ucf new file mode 100644 index 0000000..62c7e7d --- /dev/null +++ b/constraints/MEMORY_CH1.ucf @@ -0,0 +1,117 @@ +NET "ddr3_dq[0]" LOC = "A29" | ; +NET "ddr3_dq[1]" LOC = "B33" | ; +NET "ddr3_dq[2]" LOC = "A31" | ; +NET "ddr3_dq[3]" LOC = "C33" | ; +NET "ddr3_dq[4]" LOC = "C32" | ; +NET "ddr3_dq[5]" LOC = "A30" | ; +NET "ddr3_dq[6]" LOC = "B30" | ; +NET "ddr3_dq[7]" LOC = "A33" | ; +NET "ddr3_dq[8]" LOC = "D31" | ; +NET "ddr3_dq[9]" LOC = "F33" | ; +NET "ddr3_dq[10]" LOC = "D30" | ; +NET "ddr3_dq[11]" LOC = "D29" | ; +NET "ddr3_dq[12]" LOC = "E33" | ; +NET "ddr3_dq[13]" LOC = "E34" | ; +NET "ddr3_dq[14]" LOC = "E31" | ; +NET "ddr3_dq[15]" LOC = "F34" | ; +NET "ddr3_dq[16]" LOC = "B23" | ; +NET "ddr3_dq[17]" LOC = "A21" | ; +NET "ddr3_dq[18]" LOC = "C23" | ; +NET "ddr3_dq[19]" LOC = "B20" | ; +NET "ddr3_dq[20]" LOC = "B22" | ; +NET "ddr3_dq[21]" LOC = "A23" | ; +NET "ddr3_dq[22]" LOC = "C20" | ; +NET "ddr3_dq[23]" LOC = "B21" | ; +NET "ddr3_dq[24]" LOC = "G31" | ; +NET "ddr3_dq[25]" LOC = "G32" | ; +NET "ddr3_dq[26]" LOC = "F29" | ; +NET "ddr3_dq[27]" LOC = "F31" | ; +NET "ddr3_dq[28]" LOC = "E29" | ; +NET "ddr3_dq[29]" LOC = "G33" | ; +NET "ddr3_dq[30]" LOC = "H33" | ; +NET "ddr3_dq[31]" LOC = "H32" | ; +NET "ddr3_dq[32]" LOC = "B18" | ; +NET "ddr3_dq[33]" LOC = "C17" | ; +NET "ddr3_dq[34]" LOC = "C19" | ; +NET "ddr3_dq[35]" LOC = "B16" | ; +NET "ddr3_dq[36]" LOC = "A18" | ; +NET "ddr3_dq[37]" LOC = "A16" | ; +NET "ddr3_dq[38]" LOC = "C18" | ; +NET "ddr3_dq[39]" LOC = "B17" | ; +NET "ddr3_dq[40]" LOC = "K27" | ; +NET "ddr3_dq[41]" LOC = "L24" | ; +NET "ddr3_dq[42]" LOC = "K24" | ; +NET "ddr3_dq[43]" LOC = "L28" | ; +NET "ddr3_dq[44]" LOC = "K26" | ; +NET "ddr3_dq[45]" LOC = "M27" | ; +NET "ddr3_dq[46]" LOC = "L25" | ; +NET "ddr3_dq[47]" LOC = "M26" | ; +NET "ddr3_dq[48]" LOC = "F16" | ; +NET "ddr3_dq[49]" LOC = "E18" | ; +NET "ddr3_dq[50]" LOC = "E16" | ; +NET "ddr3_dq[51]" LOC = "H19" | ; +NET "ddr3_dq[52]" LOC = "H17" | ; +NET "ddr3_dq[53]" LOC = "H20" | ; +NET "ddr3_dq[54]" LOC = "E17" | ; +NET "ddr3_dq[55]" LOC = "H18" | ; +NET "ddr3_dq[56]" LOC = "D20" | ; +NET "ddr3_dq[57]" LOC = "F21" | ; +NET "ddr3_dq[58]" LOC = "E23" | ; +NET "ddr3_dq[59]" LOC = "G21" | ; +NET "ddr3_dq[60]" LOC = "G20" | ; +NET "ddr3_dq[61]" LOC = "D21" | ; +NET "ddr3_dq[62]" LOC = "F20" | ; +NET "ddr3_dq[63]" LOC = "F23" | ; +NET "ddr3_dq[64]" LOC = "L34" | ; +NET "ddr3_dq[65]" LOC = "K34" | ; +NET "ddr3_dq[66]" LOC = "K31" | ; +NET "ddr3_dq[67]" LOC = "K33" | ; +NET "ddr3_dq[68]" LOC = "L31" | ; +NET "ddr3_dq[69]" LOC = "J30" | ; +NET "ddr3_dq[70]" LOC = "L33" | ; +NET "ddr3_dq[71]" LOC = "J34" | ; +NET "ddr3_dqs_p[0]" LOC = "B31" | ; +NET "ddr3_dqs_n[0]" LOC = "B32" | ; +NET "ddr3_dqs_p[1]" LOC = "D34" | ; +NET "ddr3_dqs_n[1]" LOC = "C34" | ; +NET "ddr3_dqs_p[2]" LOC = "A19" | ; +NET "ddr3_dqs_n[2]" LOC = "A20" | ; +NET "ddr3_dqs_p[3]" LOC = "H29" | ; +NET "ddr3_dqs_n[3]" LOC = "H30" | ; +NET "ddr3_dqs_p[4]" LOC = "D16" | ; +NET "ddr3_dqs_n[4]" LOC = "D17" | ; +NET "ddr3_dqs_p[5]" LOC = "K28" | ; +NET "ddr3_dqs_n[5]" LOC = "K29" | ; +NET "ddr3_dqs_p[6]" LOC = "G17" | ; +NET "ddr3_dqs_n[6]" LOC = "G18" | ; +NET "ddr3_dqs_p[7]" LOC = "G22" | ; +NET "ddr3_dqs_n[7]" LOC = "G23" | ; +NET "ddr3_dqs_p[8]" LOC = "K32" | ; +NET "ddr3_dqs_n[8]" LOC = "J32" | ; +NET "ddr3_addr[0]" LOC = "E27" | ; +NET "ddr3_addr[1]" LOC = "C27" | ; +NET "ddr3_addr[2]" LOC = "B28" | ; +NET "ddr3_addr[3]" LOC = "D27" | ; +NET "ddr3_addr[4]" LOC = "C24" | ; +NET "ddr3_addr[5]" LOC = "D24" | ; +NET "ddr3_addr[6]" LOC = "C25" | ; +NET "ddr3_addr[7]" LOC = "A24" | ; +NET "ddr3_addr[8]" LOC = "A25" | ; +NET "ddr3_addr[9]" LOC = "J24" | ; +NET "ddr3_addr[10]" LOC = "F26" | ; +NET "ddr3_addr[11]" LOC = "D26" | ; +NET "ddr3_addr[12]" LOC = "H25" | ; +NET "ddr3_addr[13]" LOC = "D25" | ; +NET "ddr3_addr[14]" LOC = "B26" | ; +NET "ddr3_ba[0]" LOC = "F24" | ; +NET "ddr3_ba[1]" LOC = "J25" | ; +NET "ddr3_ba[2]" LOC = "E24" | ; +NET "ddr3_cas_n" LOC = "E26" | ; +NET "ddr3_ck_n[0]" LOC = "A26" | ; +NET "ddr3_ck_p[0]" LOC = "B25" | ; +NET "ddr3_cke[0]" LOC = "A28" | ; +NET "ddr3_cs_n[0]" LOC = "F28" | ; +NET "ddr3_odt[0]" LOC = "B27" | ; +NET "ddr3_ras_n" LOC = "E28" | ; +NET "ddr3_reset_n" LOC = "F18" | ; +NET "ddr3_we_n" LOC = "F25" | ; diff --git a/constraints/physical_pinout.xlsx b/constraints/physical_pinout.xlsx new file mode 100644 index 0000000..926ae82 Binary files /dev/null and b/constraints/physical_pinout.xlsx differ diff --git a/constraints/ypcb003381p1.xdc b/constraints/ypcb003381p1.xdc new file mode 100644 index 0000000..5cca179 --- /dev/null +++ b/constraints/ypcb003381p1.xdc @@ -0,0 +1,132 @@ +###################### PCI Express ###################### +set_property PACKAGE_PIN F2 [get_ports {pci_express_x8_txp[0]}] +set_property PACKAGE_PIN H2 [get_ports {pci_express_x8_txp[1]}] +set_property PACKAGE_PIN K2 [get_ports {pci_express_x8_txp[2]}] +set_property PACKAGE_PIN M2 [get_ports {pci_express_x8_txp[3]}] +set_property PACKAGE_PIN N4 [get_ports {pci_express_x8_txp[4]}] +set_property PACKAGE_PIN P2 [get_ports {pci_express_x8_txp[5]}] +set_property PACKAGE_PIN T2 [get_ports {pci_express_x8_txp[6]}] +set_property PACKAGE_PIN U4 [get_ports {pci_express_x8_txp[7]}] +set_property PACKAGE_PIN J8 [get_ports pcie_refclk_clk_p] +set_property PACKAGE_PIN Y26 [get_ports pcie_perstn] +set_property IOSTANDARD LVCMOS18 [get_ports pcie_perstn] + +###################### Sensor ###################### +set_property PACKAGE_PIN P25 [get_ports alert_lm73_tri_i] +set_property IOSTANDARD LVCMOS18 [get_ports alert_lm73_tri_i] +set_property PACKAGE_PIN N24 [get_ports iic_lm73_scl_io] +set_property IOSTANDARD LVCMOS18 [get_ports iic_lm73_scl_io] +set_property PACKAGE_PIN N25 [get_ports iic_lm73_sda_io] +set_property IOSTANDARD LVCMOS18 [get_ports iic_lm73_sda_io] + +###################### SMBus ###################### +set_property PACKAGE_PIN R26 [get_ports iic_pcie_scl_io] +set_property PACKAGE_PIN R27 [get_ports iic_pcie_sda_io] +set_property IOSTANDARD LVCMOS18 [get_ports iic_pcie_scl_io] +set_property IOSTANDARD LVCMOS18 [get_ports iic_pcie_sda_io] + +###################### LED ###################### +set_property PACKAGE_PIN P30 [get_ports {led_3bits_tri_o[0]}] +set_property PACKAGE_PIN M30 [get_ports {led_3bits_tri_o[1]}] +set_property PACKAGE_PIN N30 [get_ports {led_3bits_tri_o[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {led_3bits_tri_o[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {led_3bits_tri_o[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {led_3bits_tri_o[0]}] + +###################### Misc ###################### +set_property PACKAGE_PIN AA28 [get_ports SYS_CLK] +set_property IOSTANDARD LVCMOS18 [get_ports SYS_CLK] +set_property PACKAGE_PIN R28 [get_ports SYS_RSTN] +set_property IOSTANDARD LVCMOS18 [get_ports SYS_RSTN] + +###################### Linear Flash ###################### +set_property PACKAGE_PIN AD26 [get_ports {bpi_flash_addr[1]}] +set_property PACKAGE_PIN AC25 [get_ports {bpi_flash_addr[2]}] +set_property PACKAGE_PIN AC29 [get_ports {bpi_flash_addr[3]}] +set_property PACKAGE_PIN AC28 [get_ports {bpi_flash_addr[4]}] +set_property PACKAGE_PIN AD27 [get_ports {bpi_flash_addr[5]}] +set_property PACKAGE_PIN AC27 [get_ports {bpi_flash_addr[6]}] +set_property PACKAGE_PIN AB25 [get_ports {bpi_flash_addr[7]}] +set_property PACKAGE_PIN AB28 [get_ports {bpi_flash_addr[8]}] +set_property PACKAGE_PIN AB27 [get_ports {bpi_flash_addr[9]}] +set_property PACKAGE_PIN AB26 [get_ports {bpi_flash_addr[10]}] +set_property PACKAGE_PIN AA26 [get_ports {bpi_flash_addr[11]}] +set_property PACKAGE_PIN AA31 [get_ports {bpi_flash_addr[12]}] +set_property PACKAGE_PIN AA30 [get_ports {bpi_flash_addr[13]}] +set_property PACKAGE_PIN AB33 [get_ports {bpi_flash_addr[14]}] +set_property PACKAGE_PIN AB32 [get_ports {bpi_flash_addr[15]}] +set_property PACKAGE_PIN Y32 [get_ports {bpi_flash_addr[16]}] +set_property PACKAGE_PIN P32 [get_ports {bpi_flash_addr[17]}] +set_property PACKAGE_PIN R32 [get_ports {bpi_flash_addr[18]}] +set_property PACKAGE_PIN U33 [get_ports {bpi_flash_addr[19]}] +set_property PACKAGE_PIN T31 [get_ports {bpi_flash_addr[20]}] +set_property PACKAGE_PIN T30 [get_ports {bpi_flash_addr[21]}] +set_property PACKAGE_PIN U31 [get_ports {bpi_flash_addr[22]}] +set_property PACKAGE_PIN U30 [get_ports {bpi_flash_addr[23]}] +set_property PACKAGE_PIN N34 [get_ports {bpi_flash_addr[24]}] +set_property PACKAGE_PIN P34 [get_ports {bpi_flash_addr[25]}] +set_property PACKAGE_PIN AA33 [get_ports {bpi_flash_dq_io[0]}] +set_property PACKAGE_PIN AA34 [get_ports {bpi_flash_dq_io[1]}] +set_property PACKAGE_PIN Y33 [get_ports {bpi_flash_dq_io[2]}] +set_property PACKAGE_PIN Y34 [get_ports {bpi_flash_dq_io[3]}] +set_property PACKAGE_PIN V32 [get_ports {bpi_flash_dq_io[4]}] +set_property PACKAGE_PIN V33 [get_ports {bpi_flash_dq_io[5]}] +set_property PACKAGE_PIN W31 [get_ports {bpi_flash_dq_io[6]}] +set_property PACKAGE_PIN W32 [get_ports {bpi_flash_dq_io[7]}] +set_property PACKAGE_PIN W30 [get_ports {bpi_flash_dq_io[8]}] +set_property PACKAGE_PIN V25 [get_ports {bpi_flash_dq_io[9]}] +set_property PACKAGE_PIN W25 [get_ports {bpi_flash_dq_io[10]}] +set_property PACKAGE_PIN V29 [get_ports {bpi_flash_dq_io[11]}] +set_property PACKAGE_PIN W29 [get_ports {bpi_flash_dq_io[12]}] +set_property PACKAGE_PIN V28 [get_ports {bpi_flash_dq_io[13]}] +set_property PACKAGE_PIN W24 [get_ports {bpi_flash_dq_io[14]}] +set_property PACKAGE_PIN T34 [get_ports bpi_flash_wen] +set_property PACKAGE_PIN T33 [get_ports bpi_flash_oen] +set_property PACKAGE_PIN V30 [get_ports bpi_flash_ce_n] +set_property PACKAGE_PIN Y24 [get_ports {bpi_flash_dq_io[15]}] +set_property PACKAGE_PIN M31 [get_ports bpi_flash_adv_ldn] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[25]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[24]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[23]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[22]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[21]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[20]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[19]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[18]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[17]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[16]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[15]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[14]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[13]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[12]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[11]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[10]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[9]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[8]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_addr[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_dq_io[15]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_dq_io[14]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_dq_io[13]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_dq_io[12]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_dq_io[11]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_dq_io[10]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_dq_io[9]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_dq_io[8]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_dq_io[7]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_dq_io[6]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_dq_io[5]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_dq_io[4]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_dq_io[3]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_dq_io[2]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_dq_io[1]}] +set_property IOSTANDARD LVCMOS18 [get_ports {bpi_flash_dq_io[0]}] +set_property IOSTANDARD LVCMOS18 [get_ports bpi_flash_adv_ldn] +set_property IOSTANDARD LVCMOS18 [get_ports bpi_flash_ce_n] +set_property IOSTANDARD LVCMOS18 [get_ports bpi_flash_oen] +set_property IOSTANDARD LVCMOS18 [get_ports bpi_flash_wen]