# 创建Vivado工程（非图形界面模式）
create_project my_project ./my_project -part xc7k480tffg1156-2L -force

# # 生成IP核（以AXI UART Lite为例）
# create_ip -name axi_uartlite -vendor xilinx.com -library ip -version 2.0 -module_name uart_inst

# # 配置IP参数
# set_property -dict [list \
#     CONFIG.C_BAUDRATE {115200} \
#     CONFIG.C_S_AXI_ACLK_FREQ_HZ {100000000} \
#     CONFIG.C_DATA_BITS {8} \
#     CONFIG.C_USE_PARITY {0} \
# ] [get_ips uart_inst]


# add_file ../uart_inst.xci
add_file  ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci
add_file  ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci

generate_target all [get_ips Top_axi_bram_ctrl_0_0]
generate_target all [get_ips Top_xlconstant_2_0]



# add_file ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci
# add_file ../sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci
# add_file ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci
# add_file ../sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci
# add_file ../sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci
# add_file ../sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci
# add_file ../sources/ip/Top_xbar_0/Top_xbar_0.xci
# add_file ../sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci
# add_file ../sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci
# add_file ../sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci
# add_file ../sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci



synth_ip [get_ips Top_axi_bram_ctrl_0_0]
synth_ip [get_ips Top_xlconstant_2_0]

# write_ip_tcl -help
# write_ip_tcl -force -verbose [get_ips uart_inst] ./uart_inst.tcl