create_project -force my_project
set_property SOURCE_MGMT_MODE None [current_project]
set_property STEPS.SYNTH_DESIGN.ARGS.ASSERT true [get_runs synth_1]
set_property PART xc7k480tffg1156-2L [current_project]


# # 生成IP核（以AXI UART Lite为例）
# create_ip -name axi_uartlite -vendor xilinx.com -library ip -version 2.0 -module_name uart_inst
# # 配置IP参数
# set_property -dict [list \
#     CONFIG.C_BAUDRATE {115200} \
#     CONFIG.C_S_AXI_ACLK_FREQ_HZ {100000000} \
#     CONFIG.C_DATA_BITS {8} \
#     CONFIG.C_USE_PARITY {0} \
# ] [get_ips uart_inst]


create_ip -name axi_interconnect -vendor xilinx.com -library ip -version 1.7 -module_name axi_interconnect_0
generate_target -force all [get_ips axi_interconnect_0]
synth_ip [get_ips axi_interconnect_0]




# add_file ../uart_inst.xci
# import_ip ../sources/ip/Top_axi_bram_ctrl_0_0/Top_axi_bram_ctrl_0_0.xci
# import_ip ../sources/ip/Top_util_vector_logic_1_3/Top_util_vector_logic_1_3.xci
# import_ip ../sources/ip/Top_xlconstant_2_0/Top_xlconstant_2_0.xci
import_ip ../sources/ip/Top_axi_interconnect_0_0/Top_axi_interconnect_0_0.xci

# upgrade_ip [get_ips Top_axi_interconnect_0_0]
# # set_property GENERATE_SYNTH_CHECKPOINT true Top_axi_interconnect_0_0
# generate_target -force all [get_ips Top_axi_interconnect_0_0]
# synth_ip [get_ips Top_axi_interconnect_0_0]


# import_ip ../sources/ip/Top_util_vector_logic_1_4/Top_util_vector_logic_1_4.xci
# import_ip ../sources/ip/Top_blk_mem_gen_0_0/Top_blk_mem_gen_0_0.xci
# import_ip ../sources/ip/Top_xbar_0/Top_xbar_0.xci
# import_ip ../sources/ip/Top_mig_7series_1_0/Top_mig_7series_1_0.xci
# import_ip ../sources/ip/Top_xdma_1_0/Top_xdma_1_0.xci
# import_ip ../sources/ip/Top_util_ds_buf_0_0/Top_util_ds_buf_0_0.xci
# import_ip ../sources/ip/Top_xlconstant_0_0/Top_xlconstant_0_0.xci

# generate_target all [get_ips Top_axi_bram_ctrl_0_0]
# generate_target all [get_ips Top_util_vector_logic_1_3]
# generate_target all [get_ips Top_xlconstant_2_0]
# generate_target all [get_ips Top_axi_interconnect_0_0]
# generate_target all [get_ips Top_util_vector_logic_1_4]
# generate_target all [get_ips Top_blk_mem_gen_0_0]
# generate_target all [get_ips Top_xbar_0]
# generate_target all [get_ips Top_mig_7series_1_0]
# generate_target all [get_ips Top_xdma_1_0]
# generate_target all [get_ips Top_util_ds_buf_0_0]
# generate_target all [get_ips Top_xlconstant_0_0]

# synth_ip [get_ips Top_axi_bram_ctrl_0_0]
# synth_ip [get_ips Top_util_vector_logic_1_3]
# synth_ip [get_ips Top_xlconstant_2_0]
# synth_ip [get_ips Top_axi_interconnect_0_0]
# synth_ip [get_ips Top_util_vector_logic_1_4]
# synth_ip [get_ips Top_blk_mem_gen_0_0]
# synth_ip [get_ips Top_xbar_0]
# synth_ip [get_ips Top_mig_7series_1_0]
# synth_ip [get_ips Top_xdma_1_0]
# synth_ip [get_ips Top_util_ds_buf_0_0]
# synth_ip [get_ips Top_xlconstant_0_0]


# add_file ../sources/Top_wrapper.v
# add_file ../sources/Top.bd

# add_file -fileset constrs_1 ../normal.xdc

# set_property TOP Top_wrapper [current_fileset]

# set_property GENERIC { FREQ=100000000 SECS=1 } -objects [get_filesets sources_1]

# close_project

# open_project my_project

# # Synthesis

# # PRESYNTH
# # set_property DESIGN_MODE GateLvl [current_fileset]
# reset_run synth_1
# launch_runs synth_1
# wait_on_run synth_1
# #report_property [get_runs synth_1]
# if { [get_property STATUS [get_runs synth_1]] ne "synth_design Complete!" } { exit 1 }

# # Place and Route

# reset_run impl_1
# launch_runs impl_1
# wait_on_run impl_1
# #report_property [get_runs impl_1]
# if { [get_property STATUS [get_runs impl_1]] ne "route_design Complete!" } { exit 1 }

# # Bitstream generation

# open_run impl_1
# # write_bitstream -force xdma480t
# # write_debug_probes -force -quiet xdma480t.ltx

# close_project