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Colin ae5c8778ea Pass nitefury_pcie_xdma_ddr tcl write bit stream.		2025-05-12 17:19:33 +08:00
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project	Pass nitefury_pcie_xdma_ddr tcl write bit stream.	2025-05-12 17:19:33 +08:00
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README.md	Add nitefury_pcie_xdma_ddr.	2025-05-10 13:29:27 +08:00
dma_test.py	Add nitefury_pcie_xdma_ddr.	2025-05-10 13:29:27 +08:00
nitefury_xdma_ddr.zip	Add nitefury_pcie_xdma_ddr.	2025-05-10 13:29:27 +08:00

nitefury_pcie_xdma_ddr

Interface Xilinx XDMA PCIe with DDR3 using MIG-IP on Artix-7 FPGA using Nitefury dev board

Follow the step by step guide on our website:- https://fpganinjas.io/xdma-pcie-vivado/