388 lines
12 KiB
Systemverilog
Executable File
388 lines
12 KiB
Systemverilog
Executable File
`ifndef DMA_DEFINES_SVH
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`define DMA_DEFINES_SVH
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`include "dma_defines.vh"
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`include "pcie_dma_attr_defines.svh"
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// Interface Includes at bottom of file (use some structures defined in this file)
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`define IF_MI_CONVERSION_M \
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always_comb begin \
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ifc.wadr = wadr;\
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ifc.wen = wen;\
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ifc.wpar = wpar;\
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ifc.wdat = wdat;\
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ifc.ren = ren;\
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ifc.radr = radr;\
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rpar = ifc.rpar;\
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rdat = ifc.rdat;\
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rsbe = ifc.rsbe;\
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rdbe = ifc.rdbe;\
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end
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`define IF_MI_CONVERSION_S \
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always_comb begin \
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wadr = ifc.wadr;\
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wen = ifc.wen;\
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wpar = ifc.wpar;\
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wdat = ifc.wdat;\
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ren = ifc.ren;\
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radr = ifc.radr;\
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ifc.rpar = rpar;\
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ifc.rdat = rdat;\
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ifc.rsbe = rsbe;\
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ifc.rdbe = rdbe;\
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end
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typedef struct packed {
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logic spl;
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logic [`ADR_WIDTH-1:0] adr;
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logic [`RID_WIDTH-1:0] rid;
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logic [`LEN_WIDTH-1:0] byte_len; // byte length
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logic [`DID_WIDTH-1:0] did;
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logic [7:0] fnc; // function
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} rrq_t;
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// Descriptor Sideband Info (Context RAM to DSC_CPLI_RAM)
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typedef struct packed {
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logic wbi; // Do writeback/interrupt on descriptor completion
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logic wbi_chk; // Check status before writeback/interrupt
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logic [`QID_WIDTH-1:0] qid; // Q ID
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logic [3:0] qst;
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logic [7:0] fnc;
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logic [15:0] cidx;
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} dsc_sbi_t; // 10 + 4 + 8 + 16 = 54
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typedef struct packed {
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logic sop;
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logic eop;
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logic wbk;
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logic [4:0] err;
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logic [3:0] errc;
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//logic [`DAT_WIDTH/32-1:0] wen; // dword write enable
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logic [`RID_WIDTH-1:0] rid;
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logic [`DID_WIDTH-1:0] did;
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logic [5:0] lba; // Last beat length adjustment (AXI ST C2H)
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logic [`DAT_WIDTH/8-1:0] par;
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logic [`DAT_WIDTH-1:0] dat;
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} rcp_t;
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typedef struct packed {
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logic err;
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logic [`ADR_WIDTH-1:0] adr;
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logic [`RID_WIDTH-1:0] rid;
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logic [`LEN_WIDTH-1:0] byte_len; // byte length
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logic [5:0] aln; // Source alignment
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logic eop;
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logic eod;
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logic eor;
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} wrq_t;
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typedef struct packed {
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logic [`DAT_WIDTH/8-1:0] par;
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logic [`DAT_WIDTH-1:0] dat;
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} wpl_t;
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typedef struct packed {
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logic [`RID_WIDTH-1:0] rid;
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logic [4:0] err;
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} wcp_t;
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typedef struct packed {
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logic [31:0] dat;
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} wbrq_t;
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typedef struct packed {
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logic [3:0] be;
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logic rd;
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logic wr;
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logic [31:0] dat;
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logic [31:0] adr;
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logic [7:0] func;
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} trq_t;
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typedef struct packed {
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logic vld;
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logic [31:0] dat;
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} tcp_t;
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typedef struct packed {
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logic run;
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logic c2h_wbk_ena;
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logic noninc;
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logic [`ADR_WIDTH-1:0] cdc_wbk_adr;
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} creg_t;
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typedef struct packed {
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logic [63:0] par; // 136:73 Parity filled later
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logic [5:0] seq1; // 72:67 Sequence Num 1
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logic [5:0] seq0; // 66:61 Sequence Num 0
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logic [23:0] tph; // 60:45 TPH St Tag
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// 44:43 TPH Ind Tag
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// 42:39 TPH Type
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// 38:37 TPH Present
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logic disc; // 36 Discontinue
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logic [3:0] eop1_ptr; // 35:32 EOP 1 Ptr
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logic [3:0] eop0_ptr; // 31:28 EOP 0 Ptr
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logic eop1; // 27 EOP 1
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logic eop0; // 26 EOP 0
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logic [1:0] sop1_ptr; // 25:24 SOP 1 Ptr
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logic [1:0] sop0_ptr; // 23:22 SOP 0 Ptr
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logic sop1; // 21 SOP 1
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logic sop0; // 20 SOP 0
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logic [3:0] adr; // 19:16 Address offset - Address aligned mode only
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logic [3:0] lbe1;
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logic [3:0] lbe0;
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logic [3:0] fbe1;
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logic [3:0] fbe0;
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} rq_usr_straddle_t;
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typedef struct packed {
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logic [76:0] rsv;
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logic [31:0] par; // 59:28
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logic [3:0] seq; // 27:24
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logic [11:0] tph; // 23:12
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logic dis; // 11
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logic [2:0] adr; // 10:8
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logic [3:0] lbe; // 7:4
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logic [3:0] fbe; // 3:0
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} rq_usr_nostraddle_t;
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typedef union packed {
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rq_usr_straddle_t rqu_str;
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rq_usr_nostraddle_t rqu_nstr;
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} rq_usr_t;
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typedef struct packed {
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logic [12:0] pcie_mrrs;
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logic [12:0] pcie_mps;
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logic [12:0] axi_mrrs;
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logic [12:0] axi_mps;
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} cfg_dma_t;
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typedef struct packed {
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logic ecrc;
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logic [2:0] attr;
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logic [2:0] tc;
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logic rid_en;
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logic [15:0] cpl_id;
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logic [7:0] tag;
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logic [15:0] req_id;
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logic poison;
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logic [3:0] req;
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logic [10:0] len;
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logic [63:0] adr;
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} rq_hdr_fields_t;
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typedef struct packed {
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logic [23:0] dw3_misc;
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logic [7:0] tag;
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logic [16:0] dw2_misc;
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logic [3:0] req;
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logic [10:0] len;
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logic [63:0] adr;
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} rq_hdr_compact_t;
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typedef struct packed {
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logic [31:0] dw3;
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logic [31:0] dw2;
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logic [31:0] dw1;
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logic [31:0] dw0;
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} rq_hdr_dwords_t;
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typedef union packed {
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rq_hdr_fields_t rqh_f;
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rq_hdr_compact_t rqh_c;
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rq_hdr_dwords_t rqh_d;
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} rq_hdr_t;
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typedef struct packed {
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logic tlast;
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logic [`MULTQ_C2H_TUSER_WIDTH-1:0] tuser;
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logic [`DAT_WIDTH/8-1:0] tkeep;
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logic [`DAT_WIDTH/8-1:0] tparity;
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logic [`DAT_WIDTH-1:0] tdata;
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} dma_s_axis_t;
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typedef struct packed {
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logic [`DID_WIDTH-1:0] waddr;
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logic [`DID_WIDTH-1:0] raddr;
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logic [`DAT_WIDTH/8-1:0] wen;
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} dat_bram_cmd_t;
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typedef struct packed {
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logic [`DAT_WIDTH-1:0] dat;
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logic [`DAT_WIDTH/8-1:0] parity; // Even parity
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}dat_bram_dat_t;
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typedef struct packed {
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logic tlast;
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logic [`MULTQ_H2C_TUSER_WIDTH-1:0] tuser;
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logic [`DAT_WIDTH/8-1:0] tkeep;
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logic [`DAT_WIDTH/8-1:0] tparity;
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logic [`DAT_WIDTH-1:0] tdata;
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} dma_m_axis_t;
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// Descriptor Completion Memory Interface
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typedef struct packed {
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logic [`DAT_WIDTH-1:0] rdat;
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logic rbe;
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}dsc_cpl_bram_out_t;
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typedef struct packed {
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logic wen;
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logic [`DSC_DID_WIDTH-1:0] waddr;
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logic [`DAT_WIDTH-1:0] wdat;
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logic [`DSC_RID_WIDTH-1:0] raddr;
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}dsc_cpl_bram_in_t;
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// XDMA Descriptor Memory Interface
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//typedef struct packed {
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//logic [255:0] rdat;
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//logic rbe;
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//}dsc_bram_out_t;
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typedef struct packed {
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logic wen;
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logic [`DSC_DID_WIDTH-1:0] waddr;
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logic [255:0] wdat;
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logic [`DSC_RID_WIDTH-1:0] raddr;
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}dsc_bram_in_t;
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//
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typedef struct packed {
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logic [7:0] func;
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//logic [3:0] be;
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} dma_axil_user_t;
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// Descriptor Completion
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typedef struct packed {
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logic [63:0] wadr;
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logic [63:0] radr;
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logic [27:0] len;
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logic eop;
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logic cpl;
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logic stp;
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} dcp_t;
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// Descriptor In (user descriptors -> dma)
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typedef struct packed {
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logic [`QID_WIDTH-1:0] qid; // Q ID
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logic [1:0] chn; // Channel
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logic [3:0] qst; // Q status
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logic [2:0] fmt; // Format
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logic [255:0] dsc;
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logic [3:0] vld;
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} dma_dsc_in_t;
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// Descriptor In Credits (dma credits -> user)
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typedef struct packed {
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logic vld;
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logic [8:0] num;
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logic [`QID_WIDTH-1:0] qid;
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} dma_dsc_in_crd_t;
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// Descriptor Out (dma descriptors -> user)
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typedef struct packed {
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logic wbi;
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logic wbi_chk;
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logic [15:0] cidx;
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logic [`QID_WIDTH-1:0] qid; // Q ID
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logic [1:0] chn; // Channel
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logic [3:0] qst; // Q status
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logic [2:0] siz; // Format
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logic dir; // Direction
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logic [3:0] vld;
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logic [255:0] dsc;
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} dma_dsc_block_t;
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typedef struct packed {
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logic wbi;
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logic wbi_chk;
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logic [15:0] cidx;
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logic [`QID_WIDTH-1:0] qid; // Q ID
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logic [1:0] chn; // Channel
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logic [3:0] qst; // Q status
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logic [2:0] siz; // Format
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logic dir; // Direction
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logic [255:0] dsc;
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} dma_dsc_t;
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// Descriptor Out Credits (user credits -> dma)
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typedef struct packed {
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logic vld;
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logic [8:0] num;
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logic [`QID_WIDTH-1:0] qid;
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logic [1:0] chn;
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logic clr;
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} dma_dsc_out_crd_t;
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// Interface Conversion
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`define PCIE_CC_TO_DMA_CC_IF(pcie_cc, dma_cc) \
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assign pcie_cc.axis_cc_tvalid = dma_cc.tvalid; \
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assign pcie_cc.axis_cc_tdata = 'h0 | dma_cc.tdata; \
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assign pcie_cc.axis_cc_tuser = 'h0 | dma_cc.tuser; \
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assign pcie_cc.axis_cc_tkeep = 'h0 | dma_cc.tkeep; \
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assign pcie_cc.axis_cc_tlast = dma_cc.tlast; \
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assign dma_cc.tready = 'h0 | pcie_cc.axis_cc_tready;
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`define PCIE_CQ_TO_DMA_CQ_IF(pcie_cq, dma_cq) \
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assign dma_cq.tvalid = | pcie_cq.axis_cq_tvalid; \
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assign dma_cq.tdata = 'h0 | pcie_cq.axis_cq_tdata; \
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assign dma_cq.tuser = 'h0 | pcie_cq.axis_cq_tuser; \
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assign dma_cq.tkeep = 'h0 | pcie_cq.axis_cq_tkeep; \
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assign dma_cq.tlast = | pcie_cq.axis_cq_tlast; \
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assign pcie_cq.axis_cq_tready = 'h0 | dma_cq.tready;
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`define PCIE_RC_TO_DMA_RC_IF(pcie_rc, dma_rc) \
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assign dma_rc.tvalid = | pcie_rc.axis_rc_tvalid; \
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assign dma_rc.tdata = 'h0 | pcie_rc.axis_rc_tdata; \
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assign dma_rc.tuser = 'h0 | pcie_rc.axis_rc_tuser; \
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assign dma_rc.tkeep = 'h0 | pcie_rc.axis_rc_tkeep; \
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assign dma_rc.tlast = | pcie_rc.axis_rc_tlast; \
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assign pcie_rc.axis_rc_tready = 'h0 | dma_rc.tready;
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`define PCIE_RQ_TO_DMA_RQ_IF(pcie_rq, dma_rq) \
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assign pcie_rq.axis_rq_tvalid = dma_rq.tvalid; \
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assign pcie_rq.axis_rq_tdata = 'h0 | dma_rq.tdata; \
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assign pcie_rq.axis_rq_tuser = 'h0 | dma_rq.tuser; \
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assign pcie_rq.axis_rq_tkeep = 'h0 | dma_rq.tkeep; \
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assign pcie_rq.axis_rq_tlast = dma_rq.tlast; \
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assign dma_rq.tready = 'h0 | pcie_rq.axis_rq_tready;
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`include "dma_pcie_axis_cc_if.svh"
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`include "dma_pcie_axis_cq_if.svh"
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`include "dma_pcie_axis_rc_if.svh"
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`include "dma_pcie_axis_rq_if.svh"
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//`include "dma_pcie_c2h_axis_if.svh"
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`include "dma_pcie_c2h_crdt_if.svh"
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`include "dma_pcie_dsc_in_if.svh"
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`include "dma_pcie_dsc_out_if.svh"
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`include "dma_pcie_fabric_input_if.svh"
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`include "dma_pcie_fabric_output_if.svh"
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`include "dma_pcie_gic_if.svh"
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//`include "dma_pcie_h2c_axis_if.svh"
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`include "dma_pcie_h2c_crdt_if.svh"
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`include "dma_pcie_mi_16Bx2048_4Bwe_ram_if.svh"
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`include "dma_pcie_mi_2Bx2048_ram_if.svh"
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`include "dma_pcie_mi_4Bx2048_4Bwe_ram_if.svh"
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`include "dma_pcie_mi_64Bx128_32Bwe_ram_if.svh"
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`include "dma_pcie_mi_64Bx256_32Bwe_ram_if.svh"
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`include "dma_pcie_mi_64Bx512_32Bwe_ram_if.svh"
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`include "dma_pcie_mi_64Bx1024_32Bwe_ram_if.svh"
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`include "dma_pcie_mi_64Bx2048_32Bwe_ram_if.svh"
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`include "dma_pcie_mi_8Bx2048_4Bwe_ram_if.svh"
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`include "dma_pcie_mi_dsc_cpld_if.svh"
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`include "dma_pcie_mi_dsc_cpli_if.svh"
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`include "dma_pcie_misc_input_if.svh"
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`include "dma_pcie_misc_output_if.svh"
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`endif
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