colin

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• Joined on 2023-12-30

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colin pushed to stable at colin/Hazard3 2025-03-30 18:37:03 +08:00

2e649e2c86 Add softuart to soc_cxxrtl test.

464bd40440 Add softuart.

d2942fe094 Add uart software lib.

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colin pushed to stable at colin/Hazard3 2025-03-29 16:22:23 +08:00

393499537d Refine tb main.

colin pushed to master at colin/abstractaccelerator 2025-03-29 00:13:05 +08:00

0d7f1f8511 更新 Readme.md

colin pushed to stable at colin/Hazard3 2025-03-27 23:48:46 +08:00

aaad0d85a5 Enable aph port off soc, and print prints.

colin created branch stable in colin/Hazard3 2025-03-27 16:03:04 +08:00

colin pushed to stable at colin/Hazard3 2025-03-27 16:03:04 +08:00

5ec810907e Refine soc_cxxrtl and pass demo.

616da81d63 Add soc_cxxrtl simulation.

787da131a1 Merge pull request #28 from Wren6991/fix-21

c57e9f4c9b Coding style change for Verilator compatibility (fixes #21)

8272910121 Merge pull request #23 from Wren6991/fix-dm-abstractauto-regno

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colin created repository colin/Hazard3 2025-03-27 16:02:42 +08:00

colin pushed to master at colin/abstractaccelerator 2025-03-26 10:50:10 +08:00

8d862ff126 更新 Readme.md

colin pushed to master at colin/abstractaccelerator 2025-03-25 11:11:43 +08:00

973950cc1b add VexRiscv remote-bitbang support, but fail current.

3ca3f614fe Add jtag dpi in murax.

202042c913 Add Vexriscv demo and murax.

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colin pushed to master at colin/abstractaccelerator 2025-03-24 20:35:09 +08:00

f03117dfd7 更新 Readme.md

colin pushed to master at colin/abstractaccelerator 2025-03-24 20:06:13 +08:00

21c76636a6 更新 Readme.md

colin pushed to master at colin/abstractaccelerator 2025-03-24 19:53:48 +08:00

901194a252 更新 Readme.md

colin pushed to master at colin/abstractaccelerator 2025-03-24 19:43:31 +08:00

0ad3f6a5dc 更新 Readme.md

colin pushed to master at colin/abstractaccelerator 2025-03-24 17:35:13 +08:00

1c449f1f68 更新 Readme.md

colin pushed to master at colin/Witllm 2025-03-18 15:58:25 +08:00

cda7f04e49 Fix model path.

colin pushed to master at colin/Witllm 2025-03-14 17:38:41 +08:00

7faf629d45 Refine seed config.

colin pushed to master at colin/Witllm 2025-03-13 23:02:36 +08:00

e3493163f3 Update configuration to str for tensorboard.

colin pushed to master at colin/Witllm 2025-03-13 16:52:51 +08:00

b3817f84fe Refine model of wit.

colin pushed to master at colin/Witllm 2025-03-13 14:29:31 +08:00

f411b1cc5e donot use auto optimizer.

colin pushed to master at colin/Witllm 2025-03-12 20:02:19 +08:00

990e27ba15 Fix train define.