colin
/
cores-swerv-el2
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Add temp fpga file : synth.sh

This commit is contained in:
colin 2022-03-09 14:44:11 +00:00
parent 9950499ac5
commit dc1509b921
3 changed files with 6 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
demo/jtag/synth.sh
View File

@ -19,12 +19,11 @@ RTL=$(cat ../../soc/soc_top.mk)
rtl_files=""
rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/el2_pdef.vh "
rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/common_defines.vh "
rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/pd_defines.vh "
# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/common_defines.vh "
# # rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/pic_map_auto.h "
# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/el2_pdef.vh "
# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/el2_param.vh "
# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/pic_map_auto.h "
for src in $RTL; do
rtl_files="$rtl_files $SOC/$src"
@ -39,6 +38,7 @@ filelist=""
for file in $rtl_files; do
filelist="$filelist $file"
done
# sv2v $filelist > gen/soc_top.v
sv2v -Ibuild $filelist > gen/soc_top.v
{

2
soc/soc_sim.sv
View File

@ -170,6 +170,8 @@ module soc_sim (
fd = $fopen("console.log", "w");
commit_count = 0;
$readmemh("program.hex", rvsoc.lmem.mem);
$readmemh("program.hex", rvsoc.imem.mem);
end
assign rst_l = cycleCnt > 20;

3
soc/soc_top.sv
View File

@ -296,9 +296,6 @@ module soc_top (
nmi_vector = 32'hee000000;
nmi_int = 0;
$readmemh("program.hex", lmem.mem);
$readmemh("program.hex", imem.mem);
end
el2_swerv_wrapper rvtop (