Add temp fpga file : synth.sh
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@ -19,12 +19,11 @@ RTL=$(cat ../../soc/soc_top.mk)
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rtl_files=""
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rtl_files=""
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rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/el2_pdef.vh "
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rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/common_defines.vh "
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rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/pd_defines.vh "
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rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/pd_defines.vh "
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# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/common_defines.vh "
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# # rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/pic_map_auto.h "
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# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/el2_pdef.vh "
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# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/el2_param.vh "
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# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/el2_param.vh "
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# rtl_files+=" /home/colin/develop/Cores-SweRV-EL2/demo/jtag/build/pic_map_auto.h "
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for src in $RTL; do
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for src in $RTL; do
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rtl_files="$rtl_files $SOC/$src"
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rtl_files="$rtl_files $SOC/$src"
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@ -39,6 +38,7 @@ filelist=""
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for file in $rtl_files; do
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for file in $rtl_files; do
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filelist="$filelist $file"
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filelist="$filelist $file"
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done
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done
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# sv2v $filelist > gen/soc_top.v
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sv2v -Ibuild $filelist > gen/soc_top.v
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sv2v -Ibuild $filelist > gen/soc_top.v
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{
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{
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@ -170,6 +170,8 @@ module soc_sim (
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fd = $fopen("console.log", "w");
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fd = $fopen("console.log", "w");
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commit_count = 0;
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commit_count = 0;
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$readmemh("program.hex", rvsoc.lmem.mem);
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$readmemh("program.hex", rvsoc.imem.mem);
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end
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end
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assign rst_l = cycleCnt > 20;
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assign rst_l = cycleCnt > 20;
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@ -296,9 +296,6 @@ module soc_top (
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nmi_vector = 32'hee000000;
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nmi_vector = 32'hee000000;
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nmi_int = 0;
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nmi_int = 0;
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$readmemh("program.hex", lmem.mem);
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$readmemh("program.hex", imem.mem);
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end
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end
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el2_swerv_wrapper rvtop (
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el2_swerv_wrapper rvtop (
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