42 lines
1.3 KiB
INI
42 lines
1.3 KiB
INI
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# Probe config specific to ULX3S.
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adapter driver ft232r
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ft232r_vid_pid 0x0403 0x6015
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# Note adapter_khz doesn't do anything because this is bitbanged JTAG on aux
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# UART pins, but... it's mandatory
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adapter speed 1000
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ft232r_tck_num DSR
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ft232r_tms_num DCD
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ft232r_tdi_num RI
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ft232r_tdo_num CTS
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# trst/srst are not used but must have different values than above
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ft232r_trst_num RTS
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ft232r_srst_num DTR
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# This is the ID for the *FPGA's* chip TAP. (note this ID is for 85F version
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# of ULX3S -- if you have a different ECP5 size you can either enter the
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# correct ID for your ECP5, or remove the -expected-id part). We are going to
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# expose processor debug through a pair of custom DRs on this TAP.
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set _CHIPNAME lfe5u85
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jtag newtap lfe5u85 hazard3 -expected-id 0x41113043 -irlen 8 -irmask 0xFF -ircapture 0x5
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# We expose the DTMCS/DMI DRs you would find on a normal RISC-V JTAG-DTM via
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# the ECP5 TAP's ER1/ER2 private instructions. As long as you use the correct
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# IR length for the ECP5 TAP, and use the new instructions, the ECP5 TAP
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# looks a lot like a JTAG-DTM.
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set _TARGETNAME $_CHIPNAME.hazard3
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target create $_TARGETNAME riscv -chain-position $_TARGETNAME
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riscv set_ir dtmcs 0x32
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riscv set_ir dmi 0x38
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# That's it, it's a normal RISC-V processor now :)
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gdb_report_data_abort enable
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init
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halt
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