Hazard3/test/sim/hello_multicore/Makefile

SRCS := ../common/init.S main.c
APP  := hello_multicore
CCFLAGS = -march=rv32imac_zicsr_zifencei_zba_zbb_zbkb_zbs -Os

DOTF := tb_multicore.f
TBEXEC := ../tb_cxxrtl/tb_multicore

include ../common/src_only_app.mk
Add minimal multicore launch code 2021-12-17 09:24:11 +08:00			`SRCS := ../common/init.S main.c`
			`APP := hello_multicore`
Standardise on a single ISA variant for default test builds, and align this with the lightweight toolchain config in the Readme (Automated test builds for multiple ISA variants still yet to be implemented) 2024-08-08 04:34:27 +08:00			`CCFLAGS = -march=rv32imac_zicsr_zifencei_zba_zbb_zbkb_zbs -Os`
Add minimal multicore launch code 2021-12-17 09:24:11 +08:00
Hook up hello_multicore to automatically build and use the multicore testbench variant 2024-08-08 10:16:03 +08:00			`DOTF := tb_multicore.f`
			`TBEXEC := ../tb_cxxrtl/tb_multicore`

Add minimal multicore launch code 2021-12-17 09:24:11 +08:00			`include ../common/src_only_app.mk`