Standardise on a single ISA variant for default test builds, and align this with the lightweight toolchain config in the Readme

(Automated test builds for multiple ISA variants still yet to be implemented)

Readme.md

@@ -130,7 +130,7 @@ export PATH="$PATH:/opt/riscv/gcc14-no-zcmp/bin"
 For a faster build and a smaller install size, use this `./configure` line instead:
 
 ```bash
-./configure --with-gcc-src=$(pwd)/gcc-14 --prefix=/opt/riscv/gcc14-no-zcmp --with-arch=rv32imac_zicsr --with-abi=ilp32
+./configure --with-gcc-src=$(pwd)/gcc-14 --prefix=/opt/riscv/gcc14-no-zcmp --with-arch=rv32imac_zicsr_zifencei_zba_zbb_zbkb_zbs --with-abi=ilp32
 ```
 
 Adjust the `--with-arch` line as necessary for your Hazard3 configuration. You may need to adjust architectures used in software Makefiles in this repository to fit your chosen architecture variant.
@@ -159,14 +159,14 @@ All going well you should see something like:
 ```
 $ make
 mkdir -p tmp/
-riscv32-unknown-elf-gcc -march=rv32imc -Os ../common/init.S main.c -T ../common/memmap.ld -I../common -o tmp/hellow.elf
+riscv32-unknown-elf-gcc -march=rv32imac_zicsr_zifencei_zba_zbb_zbkb_zbs -Os -Wl,--no-warn-rwx-segments ../common/init.S main.c -T ../common/memmap.ld -I../common -o tmp/hellow.elf
 riscv32-unknown-elf-objcopy -O binary tmp/hellow.elf tmp/hellow.bin
 riscv32-unknown-elf-objdump -h tmp/hellow.elf > tmp/hellow.dis
 riscv32-unknown-elf-objdump -d tmp/hellow.elf >> tmp/hellow.dis
 ../tb_cxxrtl/tb --bin tmp/hellow.bin --vcd tmp/hellow_run.vcd --cycles 100000
 Hello world from Hazard3 + CXXRTL!
 CPU requested halt. Exit code 123
-Ran for 601 cycles
+Ran for 897 cycles
 ```
 
 This will have created a waveform dump called `tmp/hellow_run.vcd` which you can view with GTKWave:
@@ -175,6 +175,8 @@ This will have created a waveform dump called `tmp/hellow_run.vcd` which you can
 gtkwave tmp/hellow_run.vcd
 ```
 
+Installing GTKWave on Ubuntu 24.04 is just `sudo apt install gtkwave`.
+
 # Loading Hello World with the Debugger
 
 Invoking the simulator built in the previous step, with no arguments, shows the following usage message:

test/formal/instruction_fetch_match/disasm.py

@@ -10,7 +10,7 @@ with open("disasm.s", "w") as f:
 	for instr in prog:
 		f.write(f".word {instr}")
 
-system("riscv32-unknown-elf-gcc -march=rv32imac_zicsr_zba_zbb_zbc_zbs_zbkb_zifencei -c disasm.s")
+system("riscv32-unknown-elf-gcc -march=rv32imac_zicsr_zifencei_zba_zbb_zbkb_zbs -c disasm.s")
 # -d fails to disassemble compressed instructions (sometimes?) so use -D -j .text instead
 system("riscv32-unknown-elf-objdump -D -j .text -M numeric,no-aliases disasm.o")
 

test/sim/coremark/dist/barebones/core_portme.mak

@@ -19,15 +19,21 @@
 #	Use this flag to define how to to get an executable (e.g -o)
 OUTFLAG= -o
 
-MARCH        = rv32ima_zicsr_zba_zbb_zbs_zbkb
+# Note removing C (compressed) support tends to slightly improve performance
+# by eliminating alignment nops. This is really a toolchain issue because
+# most 2-byte alignment nops could also be eliminated by selectively
+# expanding 16-bit instructions to 32-bit.
+MARCH        = rv32imac_zicsr_zifencei_zba_zbb_zbkb_zbs
 CROSS_PREFIX = riscv32-unknown-elf-
 
 CC           =  $(CROSS_PREFIX)gcc
 LD           =  $(CROSS_PREFIX)gcc
 AS           =  $(CROSS_PREFIX)gcc
 
-# If compressed instructions are enabled, you also want: -falign-functions=4 -falign-jumps=4 -falign-loops=4
-PORT_CFLAGS = -O3 -g -march=$(MARCH) -mbranch-cost=1 -funroll-all-loops --param max-inline-insns-auto=200 -finline-limit=10000 -fno-code-hoisting -fno-if-conversion2
+# Slightly shorter alternative when compressed instructions are not used:
+# PORT_CFLAGS = -O3 -g -march=$(MARCH) -mbranch-cost=1 -funroll-all-loops --param max-inline-insns-auto=200 -finline-limit=10000 -fno-code-hoisting -fno-if-conversion2
+PORT_CFLAGS = -O3 -g -march=$(MARCH) -mbranch-cost=1 -funroll-all-loops --param max-inline-insns-auto=200 -finline-limit=10000 -fno-code-hoisting -fno-if-conversion2 -falign-functions=4 -falign-jumps=4 -falign-loops=4
+
 FLAGS_STR = "$(PORT_CFLAGS) $(XCFLAGS) $(XLFLAGS) $(LFLAGS_END)"
 CFLAGS = $(PORT_CFLAGS) -I$(PORT_DIR) -I. -DFLAGS_STR=\"$(FLAGS_STR)\" 
 

test/sim/dhrystone/Makefile

@@ -1,6 +1,6 @@
 SRCS       := ../common/init.S src/dhrystone_main.c src/dhrystone.c src/util.c
 APP        := dhrystone
-CCFLAGS    := -O3 -fno-inline -march=rv32im_zicsr_zba_zbb_zbs
+CCFLAGS    := -O3 -fno-inline -march=rv32imac_zicsr_zifencei_zba_zbb_zbkb_zbs -Wno-implicit-function-declaration -Wno-implicit-int
 MAX_CYCLES := 1000000
 
 include ../common/src_only_app.mk

test/sim/hello_multicore/Makefile

@@ -1,5 +1,5 @@
 SRCS := ../common/init.S main.c
 APP  := hello_multicore
-CCFLAGS = -march=rv32imc -Os
+CCFLAGS = -march=rv32imac_zicsr_zifencei_zba_zbb_zbkb_zbs -Os
 
 include ../common/src_only_app.mk

test/sim/hellow/Makefile

@@ -1,6 +1,6 @@
 SRCS := ../common/init.S main.c
 APP  := hellow
-CCFLAGS = -march=rv32imac_zicsr_zba_zbb_zbc_zbs -Os
-AFLAGS = -march=rv32imac_zicsr_zba_zbb_zbc_zbs
+CCFLAGS = -march=rv32imac_zicsr_zifencei_zba_zbb_zbkb_zbs -Os
+AFLAGS = -march=rv32imac_zicsr_zifencei_zba_zbb_zbkb_zbs
 
 include ../common/src_only_app.mk

test/sim/sw_testcases/Makefile

@@ -1,6 +1,6 @@
 APP        := hellow
 SRCS        = ../common/init.S $(APP).c $(EXTRA_SRCS_$(APP))
-CCFLAGS    := -march=rv32imac_zicsr_zifencei_zba_zbb_zbc_zbkb -Os
+CCFLAGS    := -march=rv32imac_zicsr_zifencei_zba_zbb_zbkb_zbs -Os
 MAX_CYCLES := 1000000
 INCDIR     := include ../common