Hazard3/test/sim/sw_testcases/Makefile

APP        := hellow
SRCS        = ../common/init.S $(APP).c $(EXTRA_SRCS_$(APP))
CCFLAGS    := -march=rv32imac_zicsr -Os
MAX_CYCLES := 1000000
INCDIR     := include ../common

EXTRA_SRCS_irq_preempt_set_in_irq := ../common/irq_dispatch.S
EXTRA_SRCS_irq_set_all_with_pri   := ../common/irq_dispatch.S

include ../common/src_only_app.mk
Add IRQ tests. Disable waves by default in runtests 2021-12-12 23:53:04 +08:00			`APP := hellow`
Fix a couple of bugs in preemption priority update, add simple IRQ preemption test 2022-08-08 05:04:42 +08:00			`SRCS = ../common/init.S $(APP).c $(EXTRA_SRCS_$(APP))`
Add zicsr to march in makefiles 2022-05-24 23:17:07 +08:00			`CCFLAGS := -march=rv32imac_zicsr -Os`
Add IRQ tests. Disable waves by default in runtests 2021-12-12 23:53:04 +08:00			`MAX_CYCLES := 1000000`
Fix lockup on misaligned AMO. Add tests for misaligned/faulting AMOs. 2021-12-13 02:28:23 +08:00			`INCDIR := include ../common`
Add IRQ tests. Disable waves by default in runtests 2021-12-12 23:53:04 +08:00
Fix a couple of bugs in preemption priority update, add simple IRQ preemption test 2022-08-08 05:04:42 +08:00			`EXTRA_SRCS_irq_preempt_set_in_irq := ../common/irq_dispatch.S`
- Fix signal named priority, which is a keyword in SV - Fix incorrect HIGHEST_WINS behaviour in one-hot selector - Add test for asserting 32 IRQs at 16 priorities at once - Add an entry counter to the soft dispatch code so tests can check the number of times hardware entered the vector 2022-08-08 06:17:03 +08:00			`EXTRA_SRCS_irq_set_all_with_pri := ../common/irq_dispatch.S`
First plausibly working AMOs. Add AMOs to instruction timings list 2021-12-05 07:44:22 +08:00
			`include ../common/src_only_app.mk`