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Add no_rw_check attribute to regfile memory to avoid recent Yosys area regression

This commit is contained in:
Luke Wren 2022-09-04 23:56:14 +01:00
parent 787a7ec372
commit 18c64bd633
1 changed files with 6 additions and 0 deletions
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6
hdl/hazard3_regfile_1w2r.v
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@ -51,6 +51,12 @@ if (RESET_REGS) begin: real_dualport_reset
end end
end else begin: real_dualport_noreset end else begin: real_dualport_noreset
// This should be inference-compatible on FPGAs with dual-port BRAMs // This should be inference-compatible on FPGAs with dual-port BRAMs
`ifdef YOSYS
`ifdef FPGA_ICE40
// We do not require write-to-read bypass logic on the BRAM
(* no_rw_check *)
`endif
`endif
reg [W_DATA-1:0] mem [0:N_REGS-1]; reg [W_DATA-1:0] mem [0:N_REGS-1];
always @ (posedge clk) begin always @ (posedge clk) begin