Use .f for riscv-formal tb dependencies, small reshuffling of directories

.gitmodules

@@ -8,5 +8,5 @@
 	path = scripts
 	url = https://github.com/Wren6991/fpgascripts
 [submodule "test/formal/riscv-formal"]
-	path = test/formal/riscv-formal
+	path = test/formal/riscv-formal/riscv-formal
 	url = https://github.com/Wren6991/riscv-formal.git

sourceme

@@ -1 +1,3 @@
 export PATH="$PATH:$PWD/scripts"
+export PROJ_ROOT=$PWD
+export HDL=$PROJ_ROOT/hdl

test/formal/riscv-formal

@@ -1 +0,0 @@
-Subproject commit 7dd18d861e76e01c6ce27adce1c9cc2f5b36e4c1

test/formal/riscv-formal/riscv-formal

@@ -0,0 +1 @@
+Subproject commit 8bede6ceb93ac66641bbd74a99d65a80140bc31c

test/formal/riscv-formal/tb/hazard3_rvfi.f

@@ -0,0 +1,4 @@
+file hazard3_rvfi_wrapper.v
+include .
+file $PROJ_ROOT/test/formal/common/ahbl_slave_assumptions.v
+list $HDL/hazard3.f

test/formal/riscv-formal/tb/hazard3_rvfi_wrapper.v

@@ -87,7 +87,12 @@ ahbl_slave_assumptions #(
 // Device Under Test
 // ----------------------------------------------------------------------------
 
-(* keep *) `rvformal_rand_reg [15:0] irq;
+// FIXME IRQs are tied off because riscv-formal doesn't accept the
+// nonsequential pc_wdata when an instruction is followed by an interrupt
+// (and the rvfi_intr signal doesn't do anything)
+
+wire [15:0] irq = 0;
+// (* keep *) `rvformal_rand_reg [15:0] irq;
 
 hazard3_cpu_2port #(
 	.RESET_VECTOR  (0),