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Double-step() after clock posedge to workaround CXXRTL port propagation issue

This commit is contained in:
Luke Wren 2021-07-18 16:03:53 +01:00
parent ce5cc1f150
commit 2618ae0c07
2 changed files with 4 additions and 0 deletions
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2
test/sim/openocd/tb.cpp
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@ -161,6 +161,7 @@ int main(int argc, char **argv) {
top.p_trst__n.set<bool>(true);
top.p_rst__n.set<bool>(true);
top.step();
top.step(); // workaround for github.com/YosysHQ/yosys/issues/2780
for (int64_t cycle = 0; cycle < max_cycles || max_cycles == 0; ++cycle) {
top.p_clk.set<bool>(false);
@ -169,6 +170,7 @@ int main(int argc, char **argv) {
vcd.sample(cycle * 2);
top.p_clk.set<bool>(true);
top.step();
top.step(); // workaround for github.com/YosysHQ/yosys/issues/2780
// Most bitbang commands complete in one cycle (e.g. TCK/TMS/TDI
// writes) but reads take 0 cycles, step=false.

2
test/sim/tb_cxxrtl/tb.cpp
View File

@ -122,6 +122,7 @@ int main(int argc, char **argv) {
top.p_clk.set<bool>(false);
top.p_rst__n.set<bool>(true);
top.step();
top.step(); // workaround for github.com/YosysHQ/yosys/issues/2780
for (int64_t cycle = 0; cycle < max_cycles; ++cycle) {
top.p_clk.set<bool>(false);
@ -130,6 +131,7 @@ int main(int argc, char **argv) {
vcd.sample(cycle * 2);
top.p_clk.set<bool>(true);
top.step();
top.step(); // workaround for github.com/YosysHQ/yosys/issues/2780
// Handle current data phase, then move current address phase to data phase
uint32_t rdata = 0;
if (bus_trans && bus_write) {