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Make CPU regfile nonresettable when FPGA symbol is defined, to support BRAM inference

This commit is contained in:
Luke Wren 2021-07-13 01:10:55 +01:00
parent 93c7039ea1
commit 307955c810
3 changed files with 3 additions and 12 deletions
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2
hdl/hazard3_core.v
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@ -707,6 +707,8 @@ hazard3_regfile_1w2r #(
.RESET_REGS(1), .RESET_REGS(1),
`elsif FORMAL `elsif FORMAL
.RESET_REGS(1), .RESET_REGS(1),
`elsif FPGA
.RESET_REGS(0),
`else `else
.RESET_REGS(1), .RESET_REGS(1),
`endif `endif

2
test/sim/debug_module_vectors/tb.f
View File

@ -1,4 +1,4 @@
file tb.v file tb.v
list $HDL/hazard3.f list $HDL/hazard3.f
file $HDL/debug/dm/hazard3_dm.v list $HDL/debug/dm/hazard3_dm.f

11
test/sim/debug_openocd_bitbang/tb.cpp
View File

@ -38,14 +38,6 @@ void exit_help(std::string errtext = "") {
exit(-1); exit(-1);
} }
enum cmdstate {
S_IDLE = 0,
S_WRITE_SETUP,
S_WRITE_ACCESS,
S_READ_SETUP,
S_READ_ACCESS
};
int main(int argc, char **argv) { int main(int argc, char **argv) {
if (argc < 2) if (argc < 2)
@ -179,9 +171,6 @@ int main(int argc, char **argv) {
top.p_rst__n.set<bool>(true); top.p_rst__n.set<bool>(true);
top.step(); top.step();
cmdstate state = S_IDLE;
int idle_counter = 0;
for (int64_t cycle = 0; cycle < max_cycles; ++cycle) { for (int64_t cycle = 0; cycle < max_cycles; ++cycle) {
top.p_clk.set<bool>(false); top.p_clk.set<bool>(false);
top.step(); top.step();