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Fix incorrect tracking of predictedness of fetch data phase. Fixes performance regression in RV32IMC CoreMark (now runs faster, as it should.)

This commit is contained in:
Luke Wren 2022-06-25 11:32:56 +01:00
parent 979e80be99
commit 31efd07042
2 changed files with 3 additions and 4 deletions
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5
hdl/hazard3_decode.v
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@ -131,9 +131,8 @@ assign d_pc = pc;
// Frontend should mark the whole instruction, and nothing but the // Frontend should mark the whole instruction, and nothing but the
// instruction, as a predicted branch. This goes wrong when we execute the // instruction, as a predicted branch. This goes wrong when we execute the
// address containing the predicted branch twice with different 16-bit // address containing the predicted branch twice with different 16-bit
// alignments! We don't care about performance in this case(it took BMC to // alignments (!). We need to issue a branch-to-self to get back on a linear
// find it), but need to issue a branch-to-self to get back on a linear path, // path, otherwise PC and CIR will diverge and we will misexecute.
// otherwise PC and CIR will diverge and we will misexecute.
wire partial_predicted_branch = !d_starved && wire partial_predicted_branch = !d_starved &&
|BRANCH_PREDICTOR && d_instr_is_32bit && ^fd_cir_predbranch; |BRANCH_PREDICTOR && d_instr_is_32bit && ^fd_cir_predbranch;

2
hdl/hazard3_frontend.v
View File

@ -386,7 +386,7 @@ always @ (posedge clk or negedge rst_n) begin
}; };
end end
mem_data_predbranch <= mem_data_predbranch <=
|BRANCH_PREDICTOR && btb_match_current_addr ? ( |BRANCH_PREDICTOR && btb_match_word ? (
btb_src_addr[1] ? 2'b10 : btb_src_addr[1] ? 2'b10 :
btb_src_size ? 2'b11 : 2'b01 btb_src_size ? 2'b11 : 2'b01
) : ) :